LIS33DE
MEMS motion sensor
3-axis - ±2g/±8g smart digital output “nano” accelerometer
Features
■
2.16 V to 3.6 V supply voltage
■
1.8 V compatible IOs
■
< 1 mW power consumption
■
± 2g/± 8g dynamically selectable full-scale
■
I2C/SPI digital output interface
■
Programmable interrupt generator
■
Embedded self test
■
10000g high shock survivability
■
ECOPACK® RoHS and “Green” compliant
(see Section 8)
LGA 16 (3x3x1mm3)
Applications
■
Portrait - landascape image rotation in mobile
phones and PDA
■
Motion activated user interfaces
■
Gaming
■
Motion triggered wake-up
The LIS33DE has dynamically user selectable full
scales of ±2g/±8g and it is capable of measuring
accelerations with an output data rate of 100 Hz
or 400 Hz.
A self-test capability allows the user to check the
functioning of the sensor in the final application.
Description
The LIS33DE is an ultra compact low-power three
axis linear accelerometer belonging to the “nano”
family of ST motion sensors. It includes a sensing
element and an IC interface able to provide the
measured acceleration to the external world
through I2C/SPI serial interface.
The sensing element is manufactured using a
dedicated process developed by ST to produce
inertial sensors and actuators in silicon.
Table 1.
The IC interface is manufactured using a CMOS
process that allows to design a dedicated circuit
which is trimmed to better match the sensing
element characteristics.
The device may be configured to generate inertial
wake-up/free-fall interrupt signals when a
programmable acceleration threshold is crossed
at least in one of the three axis. Thresholds and
timing of interrupt generator are programmable by
the end user on the fly.
The LIS33DE is available in plastic Thin Land
Grid Array package (LGA) and it is designed to
operate over an extended temperature range from
-40°C to +85°C.
Device summary
Order code
Temp range, ° C
Package
Packing
LIS33DE
-40 to +85
LGA 16
Tray
LIS33DETR
-40 to +85
LGA 16
Tape and reel
April 2009
Doc ID 15596 Rev 1
1/31
www.st.com
31
Contents
LIS33DE
Contents
1
2
3
4
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.2
Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.3
Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
5
2.3.1
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1
5.2
6
2/31
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.3
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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LIS33DE
7
Contents
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2
CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3
CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 23
7.4
STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5
OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.6
OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7
OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8
FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.9
FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.10
FF_WU_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.11
FF_WU_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of tables
LIS33DE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
4/31
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mechanical characteristics @ Vdd=2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics @ Vdd=2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transfer when Master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transfer when Master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 17
Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CTRL_REG1 (20h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CTRL_REG1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CTRL_REG2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CTRL_REG2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CTRL_REG3 (22h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CTRL_REG3 (22h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data signal on INT pad control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STATUS_REG (27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STATUS_REG (27h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OUT_X (29h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OUT_Y (2Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OUT_Z (2Dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FF_WU_CFG (30h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FF_WU_CFG (30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FF_WU_SRC (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FF_WU_SRC (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FF_WU_THS (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_THS (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_DURATION (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_DURATION (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 15596 Rev 1
LIS33DE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LIS33DE electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LGA 16: mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 15596 Rev 1
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Block diagram and pin description
LIS33DE
1
Block diagram and pin description
1.1
Block diagram
Figure 1.
Block diagram
X+
Y+
CS
CHARGE
AMPLIFIER
Z+
a
I2C
A/D
MUX
CONVERTER
SCL/SPC
SDA/SDO/SDI
CONTROL LOGIC
SPI
Z-
SDO
YX-
SELF TEST
1.2
CONTROL LOGIC
TRIMMING
CIRCUITS
REFERENCE
CLOCK
&
INTERRUPT GEN.
Pin description
Figure 2.
Pin connection
Z
Pin 1 indicator
X
1
13
1
9
5
Y
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
6/31
Doc ID 15596 Rev 1
(BOTTOM VIEW)
INT
LIS33DE
Block diagram and pin description
Table 2.
Pin description
Pin#
Name
Function
1
Vdd_IO
2
NC
Not connected
3
NC
Not connected
4
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
5
GND
0 V supply
6
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
7
SDO
SPI serial data output
I2C less significant bit of the device address
8
CS
9
Reserved
Leave unconnected
10
Reserved
Connect to Gnd
11
INT
Inertial interrupt
12
GND
0 V supply
13
GND
0 V supply
14
Vdd
Power supply
15
Reserved
16
GND
Power supply for I/O pins
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
Connect to Vdd
0V supply
Doc ID 15596 Rev 1
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Mechanical and electrical specifications
LIS33DE
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
T = 25°C unless otherwise noted
Table 3.
Symbol
FS
Dres
So
Mechanical characteristics @ Vdd=2.5V (1)
Parameter
Measurement range
Device resolution
Sensitivity
TCSO
Sensitivity change vs
temperature
TyOff
Typical zero-g level offset
accuracy(4)
TCOff
Zero-g level change vs
temperature
Vst
Self test output
change(5),(6),(7)
BW
System bandwidth(8)
Top
Operating temperature range
Wh
Product weight
Test conditions
Min.
Typ.(2)
(3)
±2.0
±2.3
FS bit set to 0
FS bit set to 1
±9.2
FS bit set to 0
72
Max.
Unit
g
mg
FS bit set to 0
15
18
21
FS bit set to 1
61
72
83
mg/digit
FS bit set to 0
±0.01
%/°C
FS bit set to 0
±60
mg
FS bit set to 1
±80
mg
Max delta from 25°C
±0.5
mg/°C
FS bit set to 0
STP bit used
X axis
-3
-19
-32
LSb
FS bit set to 0
STP bit used
Y axis
3
19
32
LSb
FS bit set to 0
STP bit used
Z axis
-3
-19
-32
LSb
ODR/2
-40
Hz
+85
20
°C
mgram
1. The product is factory calibrated at 2.5 V. The device can be used from 2.16 V to 3.6 V.
2. Typical specifications are not guaranteed.
3. Verified by wafer level test and measurement of initial offset and sensitivity.
4. Typical zero-g level offset value after MSL3 preconditioning.
5. If STM bit is used, values change in sign for all axes.
6. Self Test output changes with the power supply. “Self Test Output Change” is defined as OUTPUT[LSb](Self-test bit on ctrl_reg1=1)
-OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=4.6g/256 at 8bit representation, ±2.3g full-scale.
7. Output data reach 99% of final value after 3/ODR when enabling self-test mode due to device filtering.
8. ODR is Output Data Rate. Refer to Table 4 for specifications.
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LIS33DE
2.2
Mechanical and electrical specifications
Electrical characteristics
T = 25°C unless otherwise noted
Table 4.
Symbol
Vdd
Vdd_IO
Idd
IddPdn
Electrical characteristics @ Vdd=2.5V (1)
Parameter
Test conditions
Supply voltage
(3)
I/O pins supply voltage
T = 25°C, ODR=100 Hz
Current consumption in
power-down mode
T = 25°C
Digital high level Input
voltage
VIL
Digital low level input voltage
VOH
High level output voltage
VOL
Low level output voltage
ODR
Output data rate
BW
Typ.(2)
Max.
Unit
2.16
2.5
3.6
V
Vdd+0.1
V
0.3
0.45
mA
1
5
µA
1.71
Supply current
VIH
Min.
0.8*Vdd
_IO
0.2*Vdd
_IO
0.9*Vdd
_IO
DR=0
100
DR=1
400
Top
Operating temperature range
V
Hz
(5)
Turn-on time
V
V
0.1*Vdd
_IO
System bandwidth(4)
Ton
V
-40
ODR/2
Hz
3/ODR
s
+85
°C
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V.
2. Typical specification are not guaranteed.
3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
4. Filter cut-off frequency.
5. Time to obtain valid data after exiting Power-Down mode.
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Mechanical and electrical specifications
LIS33DE
2.3
Communication interface characteristics
2.3.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and top.
Table 5.
SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
Max
100
ns
10
MHz
ns
50
6
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on
characterization results, not tested in production
Figure 3.
CS
SPI slave timing diagram (a)
(3)
(3)
tc(SPC)
tsu(CS)
SPC
(3)
(3)
tsu(SI)
SDI
(3)
th(SI)
LSB IN
MSB IN
tv(SO)
SDO
th(CS)
(3)
MSB OUT
tdis(SO)
th(SO)
LSB OUT
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
resistors
a. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port
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(3)
(3)
LIS33DE
2.3.2
Mechanical and electrical specifications
I2C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 6.
I2C slave timing values
I2C standard mode(1)
Symbol
I2C fast mode (1)
Parameter
f(SCL)
Unit
SCL clock frequency
Min.
Max.
Min.
Max.
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0.01
KHz
µs
ns
3.45
0.01
0.9
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb (2)
300
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb (2)
300
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
µs
ns
µs
tw(SP:SR)
Bus free time between STOP
and START condition
1. Data based on standard I2C protocol requirement, not tested in production
2. Cb = total capacitance of one bus line, in pF
Figure 4.
I2C slave timing diagram (b)
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tf(SDA)
tsu(SDA)
tr(SDA)
START
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports
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Mechanical and electrical specifications
2.4
LIS33DE
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 7.
Absolute maximum ratings
Symbol
Vdd
Vdd_IO
Vin
Ratings
Maximum value
Unit
Supply voltage
-0.3 to 6
V
I/O pins supply voltage
-0.3 to 6
V
-0.3 to Vdd_IO +0.3
V
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO)
3000g for 0.5 ms
APOW
Acceleration (any axis, powered, Vdd=2.5V)
AUNP
Acceleration (any axis, unpowered)
TOP
Operating temperature range
-40 to +85
°C
TSTG
Storage temperature range
-40 to +125
°C
ESD
Electrostatic discharge protection
0 - 2 (HBM)
KV
10000g for 0.1 ms
3000g for 0.5 ms
Note:
10000g for 0.1 ms
Supply voltage on any pin should never exceed 6.0 V
This is a Mechanical Shock sensitive device, improper handling can cause permanent
damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages to
the part
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LIS33DE
Mechanical and electrical specifications
2.5
Terminology
2.5.1
Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the earth, noting the output value, rotating
the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing
so, ±1g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also time. The Sensitivity tolerance describes
the range of sensitivities of a large population of sensors.
2.5.2
Zero-g level
Zero-g level Offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface
measure 0g in X axis and 0g in Y axis whereas the Z axis measure 1g. The output is ideally
in the middle of the dynamic range of the sensor (content of OUT registers 00h, data
expressed as 2’s complement number). A deviation from ideal value in this case is called
Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the
offset can slightly change after mounting the sensor onto a printed circuit board or exposing
it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level
change vs. temperature”. The Zero-g level tolerance (TyOff) describes the Standard
Deviation of the range of Zero-g levels of a population of sensors.
2.5.3
Self test
Self Test allows to check the sensor functionality without moving it. The Self Test function is
off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the
self-test bit of CTRL_REG1 is programmed to ‘1‘ an actuation force is applied to the sensor,
simulating a definite input acceleration. In this case the sensor outputs exhibit a change in
their DC levels which are related to the selected full scale through the device sensitivity.
When self test is activated, the device output level is given by the algebraic sum of the
signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
If the output signals change within the amplitude specified inside Table 3, then the sensor is
working properly and the parameters of the interface chip are within the defined
specifications.
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Functionality
3
LIS33DE
Functionality
The LIS33DE is an ultracompact, low-power, digital output 3-axis linear accelerometer
packaged in a LGA package. The complete device includes a sensing element and an IC
interface able to take the information from the sensing element and to provide a signal to the
external world through an I2C/SPI serial interface.
3.1
Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is in fF range.
3.2
IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is
finally available to the user by analog-to-digital converters.
The acceleration data may be accessed through an I2C/SPI interface thus making the
device particularly suitable for direct interfacing with a microcontroller.
The LIS33DE features a data-ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in the digital
system that uses the device.
The LIS33DE may also be configured to generate an inertial Wake-Up and Free-Fall
interrupt signal accordingly to a programmed acceleration event along the enabled axes.
3.3
Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).
The trimming values are stored inside the device in a non volatile memory. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be used
during the normal operation. This allows to use the device without further calibration.
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4
Application hints
Application hints
Figure 5.
LIS33DE electrical connection
Vdd
16
10uF
14
1
Vdd_IO
13
TOP VIEW
INT
100nF
9
5
SDO
SDA/SDI/SDO
SCL/SPC
CS
8
6
GND
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be
placed as near as possible to the pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2C/SPI interface.When using the I2C, CS must be tied high.
The functions, the threshold and the timing of the interrupt pin (INT) can be completely
programmed by the user through the I2C/SPI interface.
4.1
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems.
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Digital interfaces
5
LIS33DE
Digital interfaces
The registers embedded inside the LIS33DE may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS
line must be tied high (i.e connected to Vdd_IO).
Table 8.
Serial interface pin description
Pin name
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
CS
SCL/SPC
SDA/SDI/SDO
SDO
5.1
Pin description
I2C serial clock (SCL)
SPI serial port clock (SPC)
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
I2C serial interface
The LIS33DE I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 9.
Serial interface pin description
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS33DE. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 KHz) I2C standards as well as with the
normal mode.
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5.1.1
Digital interfaces
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS33DE is 001110xb. SDO pad can be used to
modify less significant bit of the device address. If SDO pad is connected to voltage supply
LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’
(address 0011100b). This solution permits to connect and address two different
accelerometers to the same I2C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
The I2C embedded inside the LIS33DE behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb
represent the actual register address while the MSB enables address auto increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition is issued after the two sub-address bytes; if the bit is ‘0’ (Write) the
Master will transmit to the slave with direction unchanged.
Table 10.
Transfer when Master is writing one byte to slave
Master
ST
SAD + W
SUB
Slave
SAK
Table 11.
Master
ST
SAD + W
SAK
DATA
SAK
DATA
SAK
SP
SAK
Transfer when Master is receiving (reading) one byte of data from slave:
ST
SAD + W
Slave
SUB
SAK
Table 13.
Slave
SUB
SAK
Table 12.
Master
SAK
SP
Transfer when Master is writing multiple bytes to slave:
Slave
Master
DATA
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Transfer when Master is receiving (reading) one byte of data from slave
ST
SAD + W
SUB
SAK
SR
SAK
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SAD + R
NMAK
SAK
SP
DATA
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Digital interfaces
Table 14.
Master
LIS33DE
Transfer when Master is receiving (reading) multiple bytes of data from slave
ST SAD+W
Slave
SUB
SAK
SR SAD+R
SAK
MAK
SAK
DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is master acknowledge and NMAK is No
master acknowledge.
5.2
SPI bus interface
The LIS33DE SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Figure 6.
Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
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Digital interfaces
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drives SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remains unchanged in multiple read/write
commands. When 1, the address is auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When MS bit is
0 the address used to read/write data remains the same for every block. When MS bit is 1
the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
5.2.1
SPI read
Figure 7.
SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
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Digital interfaces
LIS33DE
Figure 8.
Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8
5.2.2
SPI write
Figure 9.
SPI write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 10. Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
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5.2.3
Digital interfaces
SPI read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in
CTRL_REG2.
Figure 11. SPI read protocol in 3-wires mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Multiple read command is also available in 3-wires mode.
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Register mapping
6
LIS33DE
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and
the related address:
Table 15.
Register address map
Register address
Name
Type
Default
Hex
Reserved (do not modify)
00-1F
Reserved
Ctrl_Reg1
rw
20
010 0000 00000111
Ctrl_Reg2
rw
21
010 0001 00000000
Ctrl_Reg3
rw
22
010 0010 00000000
Reserved (do not modify)
23-26
Reserved
Status_Reg
r
27
010 0111 00000000
--
r
28
010 1000
OutX
r
29
010 1001
--
r
2A
010 1010
OutY
r
2B
010 1011
--
r
2C
010 1100
OutZ
r
2D
010 1101
Reserved (do not modify)
Not used
output
Not used
output
Not used
output
2E-2F
Reserved
FF_WU_CFG
rw
30
011 0000 00000000
FF_WU_SRC(ack)
r
31
011 0001 00000000
FF_WU_THS
rw
32
011 0010 00000010
FF_WU_DURATION
rw
33
011 0011 00000000
Reserved (do not modify)
34-3F
Comment
Binary
Reserved
Registers marked as Reserved must not be changed. The writing to those registers may
cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered-up.
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7
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The registers address, made of 7 bits, is used to identify them and to
write the data through serial interface.
7.1
CTRL_REG1 (20h)
Table 16.
DR
Table 17.
CTRL_REG1 (20h) register
PD
FS
STP
STM
Zen
Yen
Xen
CTRL_REG1 (20h) register description
DR
Data rate selection. Default value: 0
(0: 100 Hz output data rate; 1: 400 Hz output data rate)
PD
Power down control. Default value: 0
(0: power down mode; 1: active mode)
FS
Full scale selection. Default value: 0
(refer to table 2 for typical full scale value)
STP, STM
Self test enable. Default value: 0
(0: normal mode; 1: self test P, M enabled)
Zen
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Yen
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
Xen
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
DR bit allows to select the data rate at which acceleration samples are produced. The
default value is ‘0’ which corresponds to a data-rate of 100 Hz. By changing the content of
DR to ‘1’ the selected data-rate will be set equal to 400 Hz.
PD bit allows to turn the device out of power-down mode. The device is in power-down
mode when PD= ‘0’ (default value after boot). The device is in normal mode when PD is set
to ‘1’.
STP, STM bits are used to activate the self-test function. When the bit is set to one, an
output change will occur to the device outputs (refer to Table 2 and 3 for specification) thus
allowing to check the functionality of the whole measurement chain.
Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when
set to ‘1’. The default value is ‘1’.
Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when
set to ’1’. The default value is ’1’.
Xen bit enables the generation of Data Ready signal for X-axis measurement channel when
set to ’1’. The default value is ’1’.
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Register description
7.2
LIS33DE
CTRL_REG2 (21h)
Table 18.
SIM
CTRL_REG2 (21h) register
BOOT
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. Bit to be kept to “0” for correct device functionality.
Table 19.
CTRL_REG2 (21h) register description
SIM
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
SIM bit selects the SPI serial interface mode. When SIM is ‘0’ (default value) the 4-wire
interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire
interface mode output data are sent to SDA_SDI pad.
BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At the device power up the content of the flash memory block is transferred to the
internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers is changed it is sufficient to use this bit to
restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied
inside corresponding internal registers and it is used to calibrate the device. These values
are factory trimmed and they are different for every accelerometer. They permit a good
behavior of the device and normally they have not to be changed. At the end of the boot
process the BOOT bit is set again to ‘0’.
7.3
CTRL_REG3 [Interrupt CTRL register] (22h)
Table 20.
IHL
CTRL_REG3 (22h) register
0(1)
0(2)
0(2)
0(2)
ICFG2
1. Bit to be kept to “0” for correct push-pull on Interrupt pad (INT).
2. Bit to be kept to “0” for correct device functionality.
Table 21.
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CTRL_REG3 (22h) register description
IHL
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
ICFG2ICFG0
Data signal on INT pad control bits. Default value 000.
(see table below)
Doc ID 15596 Rev 1
ICFG1
ICFG0
LIS33DE
Register description
Table 22.
Data signal on INT pad control bits
(1)
ICFG1(1)
ICFG0(1)
INT pad
0
0
0
GND
0
0
1
FF_WU
1
0
0
Data ready
ICFG2
1. These are the allowed bit configurations. Each other configuration may cause incorrect device functionality.
7.4
STATUS_REG (27h)
Table 23.
ZXYOR
Table 24.
STATUS_REG (27h) register
ZOR
YOR
XOR
ZYXDA
ZDA
YDA
XDA
STATUS_REG (27h) register description
ZYXOR
X, Y and Z axis data overrun. Default value: 0
(0: no overrun has occurred;
1: new data has overwritten the previous one before it is read)
ZOR
Z axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Z-axis has overwritten the previous one)
YOR
Y axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Y-axis has overwritten the previous one)
XOR
X axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the X-axis has overwritten the previous one)
ZYXDA
X, Y and Z axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
ZDA
Z axis new data available. Default value: 0
(0: a new data for the Z-axis is not yet available;
1: a new data for the Z-axis is available)
YDA
Y axis new data available. Default value: 0
(0: a new data for the Y-axis is not yet available;
1: a new data for the Y-axis is available)
XDA
X axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available;
1: a new data for the X-axis is available)
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Register description
7.5
LIS33DE
OUT_X (29h)
Table 25.
XD7
OUT_X (29h) register
XD6
XD5
XD4
XD3
XD2
XD1
XD0
YD2
YD1
YD0
ZD2
ZD1
ZD0
YLIE
XHIE
XLIE
X axis output data expressed as 2’s complement number.
7.6
OUT_Y (2Bh)
Table 26.
YD7
OUT_Y (2Bh) register
YD6
YD5
YD4
YD3
Y axis output data expressed as 2’s complement number.
7.7
OUT_Z (2Dh)
Table 27.
ZD7
OUT_Z (2Dh) register
ZD6
ZD5
ZD4
ZD3
Z axis output data expressed as 2’s complement number.
7.8
FF_WU_CFG (30h)
Table 28.
AOI
Table 29.
26/31
FF_WU_CFG (30h) register
LIR
ZHIE
ZLIE
YHIE
FF_WU_CFG (30h) register description
AOI
And/or combination of interrupt events. Default value: 0
(0: OR combination of interrupt events; 1: AND combination of interrupt events)
LIR
Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by
reading FF_WU_SRC reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
ZHIE
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
ZLIE
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Doc ID 15596 Rev 1
LIS33DE
Register description
Table 29.
7.9
FF_WU_CFG (30h) register description (continued)
YHIE
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
YLIE
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
FF_WU_SRC (31h)
Table 30.
--
Table 31.
FF_WU_SRC (31h) register
IA
ZH
ZL
YH
YL
XH
XL
FF_WU_SRC (31h) register description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: ZH event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: ZL event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: YH event has occurred)
YL
Y Low. Default value: 0
(0: no interrupt, 1: YL event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: XH event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: XL event has occurred)
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC register and the FF, WU interrupt and allows
the refreshment of data in the FF_WU_SRC register if the latched option is chosen.
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Register description
7.10
LIS33DE
FF_WU_THS (32h)
Table 32.
FF_WU_THS (32h) register
DCRM
Table 33.
THS6
THS5
THS4
THS3
THS2
THS1
THS0
FF_WU_THS (32h) register description
Resetting mode selection. Default value: 0
(0: counter reset; 1: counter decremented)
DCRM
THS6, THS0
Free-fall / wake-up Threshold: default value: 000 0010
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
7.11
FF_WU_DURATION (33h)
Table 34.
D7
Table 35.
D7-D0
FF_WU_DURATION (33h) register
D6
D5
D4
D3
D2
D1
D0
FF_WU_DURATION (33h) register description
Duration value. Default value: 0000 0000
Duration register for free-fall/wake-up interrupt. Duration step and maximum value depend
on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400 Hz, else step 10
msec, from 0 to 2.55 sec when ODR=100 Hz. The counter used to implement duration
function is blocked when LIR=1 in configuration register and the interrupt event is verified.
28/31
Doc ID 15596 Rev 1
LIS33DE
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 12. LGA 16: mechanical data and package dimensions
Dimensions
Ref.
mm
Min.
inch
Typ. Max.
A1
Min.
Typ.
1.000
A2
0.785
A3
Max.
0.0394
0.0309
0.200
0.0079
D1
2.850
3.000
3.150 0.1122 0.1181 0.1240
E1
2.850
3.000
3.150 0.1122 0.1181 0.1240
L1
1.000
1.060
L2
2.000
2.060
N1
0.500
N2
M
1.000
0.040
0.100
0.0394 0.0417
0.0787 0.0811
0.0197
0.0394
0.160 0.0016 0.0039 0.0063
P1
0.875
0.0344
P2
1.275
0.0502
T1
0.290
T2
0.190
Outline and
mechanical data
0.350
0.410 0.0114 0.0138 0.0161
0.250
0.310 0.0075 0.0098 0.0122
d
0.150
0.0059
k
0.050
0.0020
LGA16 (3x3x1.0mm)
Land Grid Array Package
7983231
Doc ID 15596 Rev 1
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Revision history
9
LIS33DE
Revision history
Table 36.
30/31
Document revision history
Date
Revision
17-Apr-2009
1
Changes
Initial release
Doc ID 15596 Rev 1
LIS33DE
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