M24M01-RMW6G

M24M01-R 1 Mbit serial I²C bus EEPROM Features ■ ■ Compatible with I2C extended addressing Two-wire I2C serial interface supports 1 MHz protocol Single supply voltage: – 1.8 V to 5.5 V Hardware write control Byte and Page Write (up to 256 bytes) Random and Sequential Read modes Self-timed programming cycle Automatic address incrementing Enhanced ESD/Latch-Up protection More than 1 million Write cycles More than 40-year data retention Packages – ECOPACK® (RoHS compliant) SO8 (MW) 208 mils width ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SO8 (MN) 150 mils width November 2007 Rev 3 1/30 www.st.com 1 Contents M24M01-R Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 2.5 2.6 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 2.6.2 2.6.3 2.6.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . . . 16 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/30 M24M01-R Contents 5 6 7 8 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3/30 List of tables M24M01-R List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC characteristics at 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC characteristics at 1 MHz (preliminary data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/30 M24M01-R List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 26 SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 27 5/30 Description M24M01-R 1 Description The M24M01-R is an I2C-compatible electrically erasable programmable memory (EEPROM) device organized as 128 Kb × 8 bits. The I2C bus is a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The M24M01-R behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are generated by the bus master and initiated by a Start condition, followed by the device select code, address bytes and data bytes. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. In order to meet environmental requirements, ST offers the M24M01-R in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram VCC 2 E1-E2 SCL WC M24M01-R SDA VSS AI13415b Table 1. Signal names Signal name Function Chip Enable Serial Data Serial Clock Write Control Supply voltage Ground Input I/O Input Input Direction E1, E2 SDA SCL WC VCC VSS 6/30 M24M01-R Figure 2. SO connections Description M24M01-R NC E1 E2 VSS 1 2 3 4 8 7 6 5 VCC WC SCL SDA AI13416b 1. See Section 7: Package mechanical for package dimensions, and how to identify pin-1. 2. NC = Not Connected internally. 7/30 Signal description M24M01-R 2 2.1 Signal description Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial Data (SDA) This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). 2.3 Chip Enable (E1, E2) These input signals are used to set the value that is to be looked for on the two bits (b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code as shown in Figure 3. When not connected (left floating), these inputs are read as low (0,0). Figure 3. Device select code VCC VCC M24xxx Ei M24xxx Ei VSS VSS Ai12806 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/30 M24M01-R Signal description 2.5 VSS ground VSS is the reference for the VCC supply voltage. 2.6 2.6.1 Supply voltage (VCC) Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1 V/µs. 2.6.3 Device reset In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 7). When VCC passes over the POR threshold, the device is reset and is in Standby Power mode. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that is there is no internal Write cycle in progress). 9/30 Signal description Figure 4. M24M01-R Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (k ) 100 fC = 400 kHz, tLOW = 1.3 µs Rbus x Cbus time constant must be less than 500 ns VCC 10 Rbus I²C bus master SCL SDA M24xxx 1 10 100 Bus line capacitor (pF) 1000 Cbus ai14796 Figure 5. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz Bus line pull-up resistor (k ) 100 fC = 1 MHz, tLOW = 500 ns, time constant Rbus x Cbus must be less than 150 ns VCC Rbus I²C bus master SCL SDA Cbus 10 fC = 1 MHz, tLOW = 700 ns, time constant Rbus x Cbus must be less than 270 ns M24xxx 1 10 Bus line capacitor (pF) ai14795 100 10/30 M24M01-R Figure 6. I2C bus protocol Signal description SCL SDA SDA Input SDA Change START Condition STOP Condition SCL 1 2 3 7 8 9 SDA MSB ACK START Condition SCL 1 2 3 7 8 9 SDA MSB ACK STOP Condition AI00792B Table 2. Device select code Device type identifier(1) b7 b6 0 b5 1 b4 0 Chip Enable address(2) b3 E2 b2 E1 A16 b1 A16 RW b0 RW Device select code 1 1. The most significant bit, b7, is sent first. 2. E1 and E2 are compared against the respective external pins on the memory device. Table 3. b15 Most significant address byte b14 b13 b12 b11 b10 b9 b8 Table 4. b7 Least significant address byte b6 b5 b4 b3 b2 b1 b0 11/30 Device operation M24M01-R 3 Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24M01-R device is always a slave in all communication. 3.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. 3.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. 3.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 3.4 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 12/30 M24M01-R Device operation 3.5 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 2-bit Chip Enable “Address” (E2, E1). To address the memory array, the 4-bit device type identifier is 1010b. Up to four memory devices can be connected on a single I2C bus. Each one is given a unique 2-bit code on the Chip Enable (E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 5. Operating modes Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write 1. X = VIH or VIL. RW bit 1 0 WC(1) X X Bytes 1 1 Initial sequence Start, device select, RW = 1 Start, device select, RW = 0, Address reStart, device select, RW = 1 X X VIL VIL ≥1 1 ≤256 1 0 0 Similar to Current or Random Address Read Start, device select, RW = 0 Start, device select, RW = 0 13/30 Device operation Figure 7. WC ACK Byte Write Start Dev sel R/W Byte addr ACK Byte addr ACK Data in Stop ACK Byte addr R/W Byte addr ACK NO ACK Data in 1 NO ACK M24M01-R Write mode sequences with WC = 1 (data write inhibited) WC ACK Page Write Start Dev sel Data in 2 WC (cont'd) NO ACK Page Write (cont'd) NO ACK Data in N Stop AI01120d 14/30 M24M01-R Device operation 3.6 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write instruction with Write Control (WC) driven high (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 7. Each data byte in the memory has a 17-bit address (the most significant bit b16 is in the device select code and the Least Significant Bits b15-b0 are defined in two address bytes). The most significant byte (Table 3) is sent first, followed by the least significant byte (Table 4). When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. 3.7 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8. 3.8 Page Write The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits, b15-b6, are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 6 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 15/30 Device operation Figure 8. Write mode sequences with WC = 0 (data write enabled) M24M01-R WC ACK Byte Write Start Dev sel R/W Byte addr ACK Byte addr ACK Data in Stop ACK Byte addr R/W Byte addr ACK Data in 1 ACK Data in 2 ACK Data in N Stop AI01106d ACK WC ACK Page Write Start WC (cont'd) ACK Page Write (cont'd) Dev sel 3.9 ECC (error correction code) and Write cycling The M24M01-R device offers an ECC (error correction code) logic which compares each 4byte word with its six associated EEPROM ECC bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC word), that is, the addressed byte is cycled together with the three other bytes making up the word. It is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of Write cycles. The M24M01-R device is qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte words. 16/30 M24M01-R Figure 9. Write cycle polling flowchart using ACK Write cycle in progress Device operation Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK returned YES NO Next Operation is addressing the memory YES ReStart Send Address and Receive ACK Stop NO StartCondition YES Data for the Write cperation Ddevice select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847d 17/30 Device operation M24M01-R 3.10 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 11, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: ● ● ● Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 10. Read mode sequences ACK Current Address Read Start Dev sel R/W Data out Stop ACK Byte addr R/W Byte addr Start NO ACK ACK Random Address Read Start Dev sel * ACK Dev sel * ACK Data out R/W NO ACK ACK Sequential Current Read Start Dev sel R/W Data out 1 ACK ACK NO ACK Data out N Stop ACK Sequention Random Read Start Dev sel * R/W Byte addr ACK Byte addr ACK Dev sel * Start ACK Data out1 R/W ACK ACK NO ACK Data out N Stop AI01105d 1. The seven most significant bits of the device select code of a Random Read (in the be identical. 1st and 4th bytes) must 18/30 Stop M24M01-R Device operation 3.11 Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 3.12 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 3.13 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte. 3.14 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. 3.15 Acknowledge in Read mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 19/30 Initial delivery state M24M01-R 4 Initial delivery state The device is delivered with all the memory array bits set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Symbol TA TSTG TLEAD VIO VCC VESD Absolute maximum ratings Parameter Ambient operating temperature Storage temperature Lead temperature during soldering Input or output range Supply voltage Electrostatic discharge voltage (Human Body model)(2) Min. –40 –65 see note –0.50 –0.50 –3000 Max. 130 150 (1) Unit °C °C °C V V V VCC + 0.6 6.5 3000 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω) 20/30 M24M01-R DC and AC parameters 6 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Symbol VCC TA Supply voltage Ambient operating temperature Operating conditions Parameter Min. 1.8 –40 Max. 5.5 85 Unit V °C Table 8. Symbol CL AC measurement conditions Parameter Load capacitance Input rise and fall times Input levels Input and output timing reference levels Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V Figure 11. AC measurement I/O waveform Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC AI00825B 0.2VCC Table 9. Symbol CIN CIN ZL ZH Input parameters Parameter(1) Input capacitance (SDA) Input capacitance (other pins) Input impedance (WC) VIN < 0.3 VCC VIN > 0.7VCC 30 400 Test condition Min. Max. 8 6 Unit pF pF kΩ kΩ 1. Sampled only, not 100% tested. 21/30 DC and AC parameters Table 10. Symbol M24M01-R DC characteristics Parameter Test condition (in addition to those in Table 7) VIN = VSS or VCC device in Standby mode VOUT = VSS or VCC, SDA in Hi-Z VCC = 1.8 V, fc= 400 kHz (rise/fall time < 50 ns) VCC = 2.5 V, fc= 400 kHz (rise/fall time < 50 ns) Min. Max. Unit ILI ILO Input leakage current (E1, E2, SCL, SDA) Output leakage current ±2 ±2 0.8 1 2 2.5 5(1) 1 2 3 –0.45 –0.45 0.75VCC 0.7VCC 0.25 VCC 0.3 VCC VCC+1 VCC+1 0.2 0.4 0.4 µA µA mA mA mA mA mA µA µA µA V ICC Supply current (Read) VCC = 5.0 V, fc= 400 kHz (rise/fall time < 50 ns) 1.8 V < VCC < 5.5 V, fc= 1 MHz (rise/fall time < 50 ns) ICC0 Supply current (Write) During tW, 1.8V < VCC < 5.5V VIN = VSS or VCC, VCC = 1.8 V ICC1 Standby supply current VIN = VSS or VCC, VCC = 2.5 V VIN = VSS or VCC, VCC = 5.5 V VIL Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA, WC) 1.8 V ≤VCC < 2.5 V 2.5 V ≤VCC ≤5.5 V 1.8 V ≤VCC < 2.5 V 2.5 V ≤VCC ≤5.5 V IOL = 0.7 mA, VCC = 1.8 V V VIH V V V VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V IOL = 3.0 mA, VCC = 5.5 V 1. Characterized value, not tested in production. 22/30 M24M01-R Table 11. AC characteristics at 400 kHz Test conditions specified in Table 7 Symbol fC tCHCL tCLCH tXH1XH2(1) tXL1XL2(1) tDL1DL2 tDXCX tCLDX tCLQX tCLQV(2)(3) tCHDX(4) tDLCL tCHDH tDHDL tW tNS(5) tWR Alt. fSCL tHIGH tLOW tR tF tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF Clock frequency Clock pulse width high Clock pulse width low Input signal rise time Input signal fall time SDA (out) fall time Data in set up time Data in hold time Data out hold time Clock low to next data valid (access time) Start condition set up time Start condition hold time Stop condition set up time Time between Stop condition and next Start condition Pulse width ignored (input filter on SCL and SDA) Write time 1.8 V < VCC < 5.5 V Parameter DC and AC parameters Min. Max. 400 Unit kHz ns ns 600 1300 20 20 20 100 0 200 200 600 600 600 1300 100 5 900 300 300 100 ns ns ns ns ns ns ns ns ns ns ns ns ms 1. Values recommended by the I²C-bus Fast-Mode specification. 2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus × Cbus time constant is less than 500 ns (as specified in Figure 4). 4. For a reStart condition, or following a Write cycle. 5. Characterized only, not tested in production. 23/30 DC and AC parameters Table 12. AC characteristics at 1 MHz (preliminary data) Test conditions specified in Table 7 Symbol fC tCHCL tCLCH tXH1XH2(1) tXL1XL2 (1) (2) M24M01-R Alt. fSCL tHIGH tLOW tR tF tF tSU:DAT Parameter Clock frequency Clock pulse width high Clock pulse width low Input signal rise time Input signal fall time SDA (out) fall time Data in setup time 0 Min. 1 - Max. Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns 300 400 20 20 20 80 0 50 50 250 250 250 500 - 300 300 100 500 5 50 tDL1DL2 tDXCX tCLDX tCLQX tHD:DAT Data in hold time tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Data out hold time Clock low to next data valid (access time) Start condition setup time Start condition hold time Stop condition setup time Time between Stop condition and next Start condition Write time Pulse width ignored (input filter on SCL and SDA) tCLQV(3)(4) tCHDX(5) tDLCL tCHDH tDHDL tW tNS(2) 1. Values recommended by the I²C-bus Fast-Mode specification. 2. Characterized only, not tested in production. 3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 4). 5. For a reStart condition, or following a Write cycle. 24/30 M24M01-R Figure 12. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDX Start condition tXH1XH2 SDA Input tCLDX SDA tDXCX Change tXL1XL2 tCHCL tCLCH DC and AC parameters tCHDH tDHDL Start Stop condition condition SCL SDA In tW tCHDH Stop condition Write cycle tCHDX Start condition tCHCL SCL tCLQV SDA Out Data valid tCLQX Data valid AI00795e tDL1DL2 25/30 Package mechanical M24M01-R 7 Package mechanical Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 b e 0.25 mm GAUGE PLANE k 8 A ccc c D E1 1 E A1 L L1 SO-A 1. Drawing is not to scale. Table 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data millimeters inches(1) Max 1.75 0.1 1.25 0.28 0.17 0.48 0.23 0.1 4.9 6 3.9 1.27 4.8 5.8 3.8 0.25 0° 0.4 1.04 5 6.2 4 0.5 8° 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0° 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8° 0.05 Typ Min Max 0.0689 0.0098 Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min 1. Values in inches are converted from mm and rounded to 4 decimal digits. 26/30 M24M01-R Package mechanical Figure 14. SO8W – 8 lead plastic small outline, 208 mils body width, package outline A2 b e D A c CP N E E1 1 A1 k L 6L_ME 1. Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows the position of pin 1 and the ‘N’ indicates the total number of pins. Table 14. SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data millimeters inches(1) Max 2.5 0 1.51 0.4 0.2 0.35 0.1 0.25 2 0.51 0.35 0.1 6.05 5.02 7.62 1.27 0° 0.5 8 6.22 8.89 10° 0.8 0.05 0.1976 0.3 0° 0.0197 8 0.0157 0.0079 0 0.0594 0.0138 0.0039 Typ Min Max 0.0984 0.0098 0.0787 0.0201 0.0138 0.0039 0.2382 0.2449 0.35 10° 0.0315 Symbol Typ A A1 A2 b c CP D E E1 e k L N Min 1. Values in inches are converted from mm and rounded to 4 decimal digits. 27/30 Part numbering M24M01-R 8 Part numbering Table 15. Example: Device type M24 = I2C serial access EEPROM Device function M01 = 1 Mbit (256 Kb × 8 bits) Clock frequency Blank: fC max = 400 kHz H: fC max = 1 MHz Operating voltage R = VCC = 1.8 V to 5.5 V Package MN = SO8 (150 mils width) MW = SO8 (208 mils width) Device grade 6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating technology P or G = ECOPACK® (RoHS compliant) Ordering information scheme M24M01 – H R MN 6 T P For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 28/30 M24M01-R Revision history 9 Revision history Table 16. Date 07-Dec-2006 Document revision history Revision 1 Initial release. Document status promoted from Preliminary Data to full Datasheet. Section 2.6: Supply voltage (VCC) updated. Note 1 updated to latest standard revision below Table 6: Absolute maximum ratings. VIL, VIH modified and, rise/fall time corrected in Test conditions in Table 10: DC characteristics. Package values in inches calculated from mm and rounded to 4 decimal digits (note added below package mechanical data tables in Section 7: Package mechanical. 1 MHz maximum clock frequency added: – Figure 5: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz – Table 12: AC characteristics at 1 MHz (preliminary data) added. tNS moved from Table 9: Input parameters to Table 11: AC characteristics at 400 kHz. Note removed below Table 9. In Table 11, tCH1CH2, tCL1CL2 and tDL1DL2 removed, tXH1XH2, tXL1XL2 added, tDL1DL2 max modified, notes modified. Figure 4: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz modified. Figure 12: AC waveforms modified. Small text changes. Changes 02-Oct-2007 2 26-Nov-2007 3 29/30 M24M01-R Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 30/30