M95M01-RMW6G

M95M01-R M95M01-W 1 Mbit serial SPI bus EEPROM with high speed clock Datasheet − production data Features ■ Compatible with SPI bus serial interface (Positive Clock SPI modes) ■ Schmitt trigger inputs for enhanced noise margin ■ Single supply voltage: 1.8 V to 5.5 V ■ High speed – 5 MHz clock rate – 5 ms Write time SO8N (MN) 150 mils width ■ Status Register ■ Hardware Protection of the Status Register ■ Byte and Page Write (up to 256 bytes) ■ Self-timed programming cycle ■ Adjustable size read-only EEPROM area ■ Enhanced ESD Protection ■ More than 1 000 000 Write cycles ■ More than 40-year data retention ■ Packages – ECOPACK® (RoHS compliant) SO8W (MW) 208 mils width TSSOP8 (DW) 169 mils width WLCSP (CS) March 2012 This is information on a product in full production. Doc ID 13264 Rev 8 1/41 www.st.com 1 Contents M95M01-R M95M01-W Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 4 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.1 4.1.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 2/41 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 13264 Rev 8 M95M01-R M95M01-W Contents 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 26 8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Doc ID 13264 Rev 8 3/41 List of tables M95M01-R M95M01-W List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. 4/41 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions (M95M01-R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating conditions (M95M01-W3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95M01-R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC characteristics (M95M01-W3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC characteristics (M95M01-R6 and M95M01-W3, VCC ≥ 2.5 V) . . . . . . . . . . . . . . . . . . . 31 AC characteristics (M95M01-R6, VCC < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 37 WLCSP – 8 bump wafer length chip scale package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Doc ID 13264 Rev 8 M95M01-R M95M01-W List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections (bottom view, bump side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 35 SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 36 TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 37 WLCSP – 8 bump wafer length chip scale package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 13264 Rev 8 5/41 Description 1 M95M01-R M95M01-W Description The M95M01-R and M95M01-W are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high speed SPI-compatible bus. The memory array is organized as 131 072 × 8 bit. It can also be seen as 512 pages of 256 bytes each. The device is accessed by a simple serial interface that is SPI-compatible. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram VCC D Q C S M95xxx W HOLD VSS AI01789C Table 1. Signal names Signal name Function Direction C Serial Clock Input D Serial Data Input Input Q Serial Data Output Output S Chip Select Input W Write Protect Input HOLD Hold Input VCC Supply voltage VSS Ground The bus signals are C, D and Q, as shown in Figure 1 and Table 1. 6/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W Figure 2. Description SO connections M95xxx S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D AI01790D 1. See Section 11: Package mechanical data for package dimensions, and how to identify pin-1. Figure 3. WLCSP connections (bottom view, bump side) VCC SCL VSS HOLD S D Q W ai16066 Doc ID 13264 Rev 8 7/41 Signal description 2 M95M01-R M95M01-W Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 12). These signals are described next. 2.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). 2.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 2.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 2.6 Signal description Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions. 2.7 VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. Doc ID 13264 Rev 8 9/41 Connecting to the SPI bus 3 M95M01-R M95M01-W Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 4. Bus master and memory devices on the SPI bus VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C Q D SPI Bus Master SPI Memory Device R CS3 VCC C Q D VSS C Q D VCC VSS SPI Memory Device R VSS SPI Memory Device R CS2 CS1 S W HOLD S W HOLD S W HOLD AI12836b 1. The Write Protect (W) and Hold (HOLD) signals should be driven high or low as appropriate. Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. The pull-up resistor R (represented in Figure 4) ensures that no device is selected if the bus master leaves the S line in the high impedance state. In applications where the bus master might enter a state where the whole input/output SPI bus is high-impedance at a given time (for example, if the bus master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ. 10/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 3.1 Connecting to the SPI bus SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Standby mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 5. SPI modes supported CPOL CPHA 0 0 C 1 1 C D MSB Q MSB AI01438B Doc ID 13264 Rev 8 11/41 Operating features M95M01-R M95M01-W 4 Operating features 4.1 Supply voltage (VCC) 4.1.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. 4.1.2 Device reset In order to prevent inadvertent write operations during power-up, a power on reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8. When VCC passes over the POR threshold, the device is reset and in the following state: ● in Standby Power mode ● deselected (note that, to be executed, an instruction must be preceded by a falling edge on Chip Select (S)) ● Status Register value: – the Write Enable Latch (WEL) is reset to 0 – Write In Progress (WIP) is reset to 0 – The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits) When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. The device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8. 4.1.3 Power-up conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 4). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edgesensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8 and the rise time must not vary faster than 1 V/µs. 12/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 4.1.4 Operating features Power-down During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 8), the device must be: 4.2 ● deselected (Chip Select S should be allowed to follow the voltage applied on VCC) ● in Standby Power mode (there should not be any internal write cycle in progress). Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 12. When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1. 4.3 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 6). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. Figure 6. Hold condition activation C HOLD Hold Condition Hold Condition AI02029D Doc ID 13264 Rev 8 13/41 Operating features 4.4 M95M01-R M95M01-W Status Register Figure 7 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status Register bits 4.5 Data protection and protocol control Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms: ● Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ● All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: – Power-up – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write (WRITE) instruction completion ● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. ● The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status Register to be protected. For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence: ● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). ● The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus. Table 2. Write-protected block size Status Register bits 14/41 Protected block Array addresses protected BP1 BP0 0 0 none none 0 1 Upper quarter 1 8000h - 1 FFFFh 1 0 Upper half 1 0000h - 1 FFFFh 1 1 Whole memory 0 0000h - 1 FFFFh Doc ID 13264 Rev 8 M95M01-R M95M01-W Memory organization The memory is organized as shown in Figure 7. Figure 7. Block diagram HOLD W High Voltage Generator Control Logic S C D I/O Shift Register Q Address Register and Counter Data Register Status Register Size of the Read only EEPROM area Y Decoder 5 Memory organization 1 Page X Decoder AI01272C Doc ID 13264 Rev 8 15/41 Instructions 6 M95M01-R M95M01-W Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set Instruction 6.1 Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. Figure 8. Write Enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI02281E 16/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 6.2 Instructions Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: ● Power-up ● WRDI instruction execution ● WRSR instruction completion ● WRITE instruction completion. Figure 9. Write Disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI03750D Doc ID 13264 Rev 8 17/41 Instructions 6.3 M95M01-R M95M01-W Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. The status and control bits of the Status Register are as follows: 6.3.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.3.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted. 6.3.3 BP1, BP0 bits The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. 6.3.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD b0 0 0 0 BP1 BP0 WEL WIP Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit 18/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W Instructions Figure 10. Read Status Register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 6 5 4 3 MSB 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI02031E Doc ID 13264 Rev 8 19/41 Instructions 6.4 M95M01-R M95M01-W Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. Figure 11. Write Status Register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 D High Impedance 6 5 4 3 2 1 0 MSB Q AI02282D 20/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W Table 5. Instructions Protection modes W SRWD Signal Bit 1 0 0 0 1 1 0 1 Mode Write Protection of the Status Register Memory content Protected area(1) Unprotected area(1) Status Register is Writable Software (if the WREN instruction Protected has set the WEL bit) Write Protected (SPM) The values in the BP1 and BP0 bits can be changed Ready to accept Write instructions Status Register is Hardware Hardware write protected Protected The values in the BP1 and Write Protected (HPM) BP0 bits cannot be changed Ready to accept Write instructions 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 4. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. The protection features of the device are summarized in Table 2. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven high or low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): ● If Write Protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. ● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Doc ID 13264 Rev 8 21/41 Instructions M95M01-R M95M01-W Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: ● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) low ● or by driving Write Protect (W) low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. 22/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 6.5 Instructions Read from Memory Array (READ) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 12. Read from Memory Array (READ) sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address 23 22 21 D 3 2 1 0 MSB Data Out 1 High Impedance 7 Q 6 5 4 3 2 Data Out 2 1 0 7 MSB AI13878 1. As shown in Table 6, the most significant address bits are Don’t Care. Table 6. Address range bits(1) M95M01-R and M95M01-W Address bits A16-A0 1. Bits A23 to A17 are Don’t Care. Doc ID 13264 Rev 8 23/41 Instructions 6.6 M95M01-R M95M01-W Write to Memory Array (WRITE) As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. In the case of Figure 13, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Table 15), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. The selftimed Write cycle starts, and continues, for a period tWC (as specified in Table 15), at the end of which the Write in Progress (WIP) bit is reset to 0. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size is 256 bytes). The instruction is not accepted, and is not executed, under the following conditions: Note: ● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) ● if a Write cycle is already in progress ● if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) ● if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. The self-timed write cycle, tW, is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. Figure 13. Byte Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address 23 14 13 D 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High Impedance Q AI13879 1. As shown in Table 6, the most significant address bits are Don’t Care. 24/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W Instructions Figure 14. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-bit address 15 14 13 D 3 2 Data byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data byte 2 D 7 6 5 4 3 2 Data byte 3 1 0 7 6 5 4 3 2 Data byte N 1 0 6 5 4 3 2 1 0 AI13880 1. As shown in Table 6, the most significant address bits are Don’t Care. Doc ID 13264 Rev 8 25/41 ECC (error correction code) and write cycling 7 M95M01-R M95M01-W ECC (error correction code) and write cycling The M95M01-R and M95M01-W devices offer an ECC (error correction code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95M01-R and M95M01-W devices are qualified at 1 million (1 000 000) write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets. 8 Power-up and delivery state 8.1 Power-up state After power-up, the device is in the following state: ● Standby Power mode ● Deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started). ● Not in the Hold condition ● Write Enable Latch (WEL) is reset to 0 ● Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 8.2 Initial delivery state The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 26/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 9 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Absolute maximum ratings Symbol TA TSTG TLEAD Parameter Min. Max. Unit Ambient operating temperature –40 130 °C Storage temperature –65 150 °C Lead temperature during soldering See note (1) °C VO Output voltage –0.50 VCC+0.6 V VI Input voltage –0.50 6.5 V VCC Supply voltage –0.50 6.5 V IOL DC output current (Q = 0) 5 mA IOH DC output current (Q = 1) –5 mA 4000 V VESD Electrostatic discharge voltage (human body model)(2) –4000 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω) Doc ID 13264 Rev 8 27/41 DC and AC parameters 10 M95M01-R M95M01-W DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M95M01-R6) Symbol VCC TA Table 9. Parameter Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 125 °C Operating conditions (M95M01-W3) Symbol VCC TA Table 10. Parameter AC measurement conditions Symbol CL Parameter Min. Load capacitance Max. Unit 100 Input rise and fall times pF 50 ns Input pulse voltages 0.2 VCC to 0.8 VCC V Input and output timing reference voltages 0.3 VCC to 0.7 VCC V Figure 15. AC measurement I/O waveform )NPUTVOLTAGELEVELS )NPUTANDOUTPUT TIMINGREFERENCELEVELS 6## 6## 6## 6## !)# Table 11. Capacitance Parameter(1) Symbol COUT CIN Max. Unit VOUT = 0 V 8 pF Input capacitance (D) VIN = 0 V 8 pF Input capacitance (other pins) VIN = 0 V 6 pF Output capacitance (Q) Test condition 1. Not 100% tested. 28/41 Doc ID 13264 Rev 8 Min. M95M01-R M95M01-W Table 12. Symbol DC and AC parameters DC characteristics (M95M01-R6) Parameter Test condition Max Unit ±2 µA ±2 µA C = 0.1 VCC/0.9 VCC at 2 MHz, VCC = 1.8 V, Q = open 1.5 mA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 1.8 V, Q = open 3(1) mA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 2.5 V, Q = open 4 mA C = 0.1 VCC/0.9 VCC at 10 MHz, VCC = 2.5 V, Q = open 3(1) C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 5 V, Q = open 5 C = 0.1 VCC/0.9 VCC at 10 MHz, VCC = 5.5 V, Q = open 5(1) ILI Input leakage current ILO Output leakage current S = VCC, VOUT = VSS or VCC ICC ICC0(2) ICC1 Min VIN = VSS or VCC Supply current (Read) Supply current (Write) Supply current (Standby Power mode) During tW, S = VCC, 5 mA S = VCC, VIN = VSS or VCC, VCC = 1.8 V 3 µA S = VCC, VIN = VSS or VCC, VCC = 1.8 V, temp = 25 °C (or less) 1 µA S = VCC, VIN = VSS or VCC, VCC = 2.5 V 3 µA S = VCC, VIN = VSS or VCC, VCC = 2.5 V, temp = 25 °C (or less) 1 µA S = VCC, VIN = VSS or VCC, VCC = 5.5 V 5 µA 1.5 µA S = VCC, VIN = VSS or VCC, VCC = 5.5 V, temp = 25 °C (or less) VIL Input low voltage VIH Input high voltage VOL Output low voltage VOH Output high voltage mA 1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC 2.5 V ≤ VCC ≤ 5.5 V –0.45 0.3 VCC 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 2.5 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC+1 V V IOL = 0.15 mA, VCC = 1.8 V 0.3 V VCC = 2.5 V, IOL = 1.5 mA or VCC = 5 V, IOL = 2 mA 0.4 V IOH = –0.1 mA, VCC = 1.8 V VCC = 2.5 V, IOH = –0.4 mA or VCC = 5 V, IOH = –2 mA 0.8 VCC V 1. For devices identified by process letter K. 2. Characterized value, not tested in production. Doc ID 13264 Rev 8 29/41 DC and AC parameters Table 13. Symbol M95M01-R M95M01-W DC characteristics (M95M01-W3) Parameter Test conditions (in addition to conditions defined in Table 9) Max.(1) Unit ±2 µA ±2 µA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 2.5 V, Q = open 4 mA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 5 V, Q = open 5 mA During tW, S = VCC, 2.5 V < VCC < 5.5 V 6 mA 5 µA ILI Input leakage current ILO Output leakage current S = VCC, VOUT = VSS or VCC ICC ICC0(2) Supply current (Read) Supply current (Write) VIN = VSS or VCC ICC1 Supply current S = VCC, VIN = VSS or VCC, (Standby Power mode) 2.5 V < VCC < 5.5 V VIL Input low voltage –0.45 0.3 VCC V VIH Input high voltage 0.7 VCC VCC+1 V VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA 0.4 V VOH Output high voltage VCC = 2.5 V and IOH = –0.4 mA or VCC = 5 V and IOH = –2 mA 1. Preliminary data. 2. Characterized value, not tested in production. 30/41 Min.(1) Doc ID 13264 Rev 8 0.8 VCC V M95M01-R M95M01-W Table 14. DC and AC parameters AC characteristics (M95M01-R6 and M95M01-W3, VCC ≥ 2.5 V) Test conditions specified in Table 8, Table 9 and Table 10 Symbol Alt. fC fSCK Parameter(1) Clock frequency Min. Max. Min.(2) Max.(2) Unit D.C. 5 D.C. 10 MHz tSLCH tCSS1 S active setup time 60 30 ns tSHCH tCSS2 S not active setup time 60 30 ns tSHSL tCS S Deselect time 60 40 ns tCHSH tCSH S active hold time 60 30 ns S not active hold time 60 30 ns tCHSL tCH (3) tCLH Clock high time 90 40 ns (3) 90 40 ns tCLL Clock low time tCLCH (4) tRC Clock rise time 2 µs tCHCL (4) tFC Clock fall time 2 µs tCL tDVCH tDSU Data in setup time 20 10 ns tCHDX tDH Data in hold time 20 10 ns tHHCH Clock low hold time after HOLD not active 60 30 ns tHLCH Clock low hold time after HOLD active 60 30 ns tCLHL Clock low set-up time before HOLD active 0 0 ns tCLHH Clock low set-up time before HOLD not active 0 0 ns tSHQZ (4) tDIS tCLQV tV tCLQX Output disable time 80 40 ns Clock low to output valid 80 40 ns tHO Output hold time tQLQH (4) 0 0 ns tRO Output rise time 80 40 ns tQHQL (4) tFO Output fall time 80 40 ns tHHQV tLZ HOLD high to output valid 80 40 ns tHLQZ (4) tHZ HOLD low to output high-Z 80 40 ns tW tWC Write time 5 5 ms 1. Data concerning the M95M01-W3 are preliminary. 2. For devices identified with process letter K. 3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 4. Value guaranteed by characterization, not 100% tested in production. Doc ID 13264 Rev 8 31/41 DC and AC parameters Table 15. M95M01-R M95M01-W AC characteristics (M95M01-R6, VCC < 2.5 V) Test conditions specified in Table 8 and Table 10 Symbol Alt. fC fSCK tSLCH Min.(1) Max.(1) Min. Max. Clock frequency D.C. 2 tCSS1 S active setup time 150 60 ns tSHCH tCSS2 S not active setup time 150 60 ns tSHSL tCS S deselect time 200 90 ns tCHSH tCSH S active hold time 150 60 ns S not active hold time 150 60 ns tCHSL Parameter D.C. 5 Unit MHz tCH (2) tCLH Clock high time 200 80 ns (2) 200 80 ns tCLL Clock low time tCLCH (3) tRC Clock rise time 2 µs tCHCL (3) tFC Clock fall time 2 µs tCL tDVCH tDSU Data in setup time 50 20 ns tCHDX tDH Data in hold time 50 20 ns tHHCH Clock low hold time after HOLD not active 150 60 ns tHLCH Clock low hold time after HOLD active 150 60 ns tCLHL Clock low setup time before HOLD active 0 0 ns tCLHH Clock low setup time before HOLD not active 0 0 ns tSHQZ (3) tDIS tCLQV(4) tV tCLQX Output Disable time 200 80 ns Clock low to output valid 200 80 ns tHO Output hold time tQLQH (3) 0 0 ns tRO Output rise time 200 80 ns tQHQL (3) tFO Output fall time 200 80 ns tHHQV tLZ HOLD high to output valid 200 80 ns tHLQZ (3) tHZ HOLD low to output high-Z 200 80 ns tW tWC Write time 5 5 ms 1. For devices identified with process letter K. 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 3. Value guaranteed by characterization, not 100% tested in production. 4. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a read setup time tSU = 0 ns, tCL can be equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV + tSU. 32/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W DC and AC parameters Figure 16. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCHCL tCL tCLCH tCHDX D Q LSB IN MSB IN High impedance AI01447d Figure 17. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q HOLD AI01448c Doc ID 13264 Rev 8 33/41 DC and AC parameters M95M01-R M95M01-W Figure 18. Serial output timing S tCH tSHSL C tCLQV tCLCH tCHCL tCL tSHQZ tCLQX Q tQLQH tQHQL ADDR D LSB IN AI01449f 34/41 Doc ID 13264 Rev 8 M95M01-R M95M01-W 11 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 19. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 SO-A 1. Drawing is not to scale. Table 16. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.750 Max 0.0689 A1 0.100 A2 1.250 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 ccc 0.250 0.0039 0.0098 0.0492 0.100 0.0039 D 4.900 4.800 5.000 0.1929 0.1890 0.1969 E 6.000 5.800 6.200 0.2362 0.2283 0.2441 E1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 – – 0.0500 - - h 0.250 0.500 0.0098 0.0197 k 0° 8° 0° 8° L 0.400 1.270 0.0157 0.0500 L1 1.040 0.0409 1. Values in inches are converted from mm and rounded to four decimal digits. Doc ID 13264 Rev 8 35/41 Package mechanical data M95M01-R M95M01-W Figure 20. SO8W – 8 lead plastic small outline, 208 mils body width, package outline A A2 c b CP e D N E E1 1 A1 k L 6L_ME 1. Drawing is not to scale. Table 17. SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ 2.50 Max 0.0984 A1 0.00 0.25 0.0000 0.0098 A2 1.51 2.00 0.0594 0.0787 b 0.40 0.35 0.51 0.0157 0.0138 0.0201 c 0.20 0.10 0.35 0.0079 0.0039 0.0138 CP 0.10 0.0039 D 6.05 0.2382 E 5.02 6.22 0.1976 0.2449 E1 7.62 8.89 0.3000 0.3500 – – - - k 0 10 0° 10° L 0.50 0.80 0.0197 0.0315 e N 1.27 0.0500 8 8 1. Values in inches are converted from mm and rounded to four decimal digits. 36/41 Min Doc ID 13264 Rev 8 M95M01-R M95M01-W Package mechanical data Figure 21. TSSOP8 – 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min A Max Min 1.200 A1 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0° 8° 0.0394 α 0° N 8 8° 8 1. Values in inches are converted from mm and rounded to four decimal digits. Doc ID 13264 Rev 8 37/41 Package mechanical data M95M01-R M95M01-W Figure 22. WLCSP – 8 bump wafer length chip scale package e1 D e2 e E e2 Detail A Orientation reference A2 F A Orientation reference Wafer back side Side view G Bump side Bump A1 b(8x) Øccc M Z X Y Øddd M Z Seating plane(2) Note (3) Detail A rotated by 90° ai16079 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 3. Bump position designation as per JESD 95-1, SPP-010. Table 19. WLCSP – 8 bump wafer length chip scale package inches(1) millimeters Symbol Typ Min 0.555 Max Typ 0.605 0.580 A1 0.230 0.0091 A2 0.350 0.0138 b 0.322 0.0127 D 3.570 3.685 0.1406 0.1451 E 2.050 2.165 0.0807 0.0852 e 0.600 0.0236 e1 2.400 0.0945 e2 1.200 0.0472 F 0.585 0.0230 G 0.425 0.0167 8 aaa 0.110 0.0043 bbb 0.110 0.0043 ccc 0.110 0.0043 ddd 0.060 0.0024 eee 0.060 0.0024 1. Values in inches are converted from mm and rounded to four decimal digits. 38/41 Doc ID 13264 Rev 8 0.0219 Max A N (number of bumps) 0.0228 Min 0.0238 M95M01-R M95M01-W 12 Part numbering Part numbering Table 20. Ordering information scheme Example: M95M01 – R MN 6 T P /K Device type M95 = SPI serial access EEPROM Device function M01 = 1024 Kbits (131 072 × 8) Operating voltage R = VCC = 1.8 V to 5.5 V W = VCC = 2.5 V to 5.5 V Package MN = SO8N (150 mils width) MW = SO8W (208 mils width) CS = WLCSP DW = TSSOP8 (169 mils width) Device grade 6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow 3 = Automotive temperature range, –40 to 125 °C. Device tested with high reliability certified flow(1) Option blank = standard packing T = tape and reel packing Plating technology P or G = ECOPACK® (RoHS compliant) Process(2) /A or /K= Manufacturing technology code 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. The process letter only concerns WLCSP devices and device grade 3 products. For all other packages, the process letters do not appear in the Ordering Information but only appear on the device package (marking) and on the shipment box. Please contact your nearest ST sales office. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 13264 Rev 8 39/41 Revision history 13 Revision history Table 21. Document revision history Date Revision 13-Mar-2007 1 Initial release. 15-May-2007 2 VCC conditions modified in Table 15: AC characteristics (M95M01-R6, VCC < 2.5 V). Small text changes. 21-Jun-2007 3 The device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1). 4 Schmitt trigger inputs for enhanced noise margin added to Features on page 1. VIL and VIH values modified according to voltage range in Table 12: DC characteristics (M95M01-R6). 5 Document status promoted from preliminary data to full datasheet. ICC0 modified in Table 12: DC characteristics (M95M01-R6). In Section 11: Package mechanical data, values in inches are converted from mm and rounded to 4 decimal digits. Table 20: Available products (package, voltage range, temperature grade) added. Small text changes. 6 WLCSP package added (see Figure 3: WLCSP connections (bottom view, bump side) and Section 11: Package mechanical data). Section 3: Connecting to the SPI bus updated. Section 4.1: Supply voltage (VCC) updated. Note added to Section 6.6: Write to Memory Array (WRITE). Note added to Table 15: AC characteristics (M95M01-R6, VCC < 2.5 V). Figure 16: Serial input timing, Figure 17: Hold timing and Figure 18: Serial output timing updated. ECOPACK text updated under Section 11: Package mechanical data. 7 M95M01-W device grade 3 devices added (see Table 9: Operating conditions (M95M01-W3), Table 13: DC characteristics (M95M01-W3), Table 14: AC characteristics (M95M01-R6 and M95M01-W3, VCC ≥ 2.5 V) and Table 20: Ordering information scheme). 8 Added TSSOP package. Updated – Table 12: DC characteristics (M95M01-R6) – Table 13: DC characteristics (M95M01-W3) – Table 14: AC characteristics (M95M01-R6 and M95M01-W3, VCC ≥ 2.5 V) – Table 15: AC characteristics (M95M01-R6, VCC < 2.5 V) – Figure 15: AC measurement I/O waveform – “Process” in Section 12: Part numbering Deleted: – Table 20: Available products (package, voltage range, temperature grade) 17-Jul-2007 24-Jan-2008 07-May-2009 30-Jul-2009 26-Mar-2012 40/41 M95M01-R M95M01-W Changes Doc ID 13264 Rev 8 M95M01-R M95M01-W Please Read Carefully: Information in this document is provided solely in connection with ST products. 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