SPC564B70L7C9E0X

SPC564Bxx SPC56ECxx 32-bit MCU family built on the Power Architecture® for automotive body electronics applications Datasheet - production data LBGA256 (17 x 17 x 1.7 mm) LQFP176 LQFP208 (28 x 28 x 1.4 mm) (24 x 24 x 1.4 mm) Features  e200z4d, 32-bit Power – Up to 120 MHz and 200 MIPs operation Architecture®  e200z0h, 32-bit Power Architecture – Up to 80 MHz and 75 MIPs operation  Memory – Up to 3 MByte on-chip Flash with ECC – Up to 256 KByte on-chip SRAM with ECC – 64KByte on-chip Data Flash with ECC – 16-entry memory protection unit (MPU) – User selectable Memory BIST  Interrupts – 255 interrupt sources with 16 priority levels – Up to 54 ext. IRQ including 30 wake-up  GPIOs: from 147 (LQFP176) to 199 (LBGA256)  System timer units – 8-ch. 32-bit periodic interrupt timer (PIT) – 4-channel 32-bit system timer (STM) – Safety System Watchdog Timer (SWT) – Real-time clock timer (RTC/API)  eMIOS, 16-bit counter timed I/O units – Up to 64 channels with PWM/MC/IC/OC – – – – – – Up to 6 FlexCAN with 64 buffers each Up to 10 LINFlex/UART channels Up to 8 buffered DSPI channels I2C interface One FleyRay (dual-ch.) with 128 buffers Fast Ethernet Controller  Cryptographic Services Engine (CSE) – AES-128 en/decryption, CMAC auth. – Secured device boot mode  32-ch. eDMA with multiple request sources  Clock generation – 4 to 40 MHz main oscillator – 16 MHz internal RC oscillator – Software-controlled FMPLL – 128 kHz internal RC oscillator – 32 kHz auxiliary oscillator – Clock Monitoring Unit (CMU)  Low power capabilities – Ultra low power STANDBY – CAN Sampler to store CAN ID in STBY – Fast wake-up and exectute from RAM  Exhaustive debugging capability – Nexus 3+ interface on LBGA256 only – Nexus 1 on all devices  Voltage supply – Single 5 V or 3.3 V supply – On-chip Vreg with external ballast transitor  Operating temperature range -40 to 125 °C  Two ADC (10-bit and 12-bit) – Up to 62 channels extendable to 90 ch. – Multiple Analog Watchdog  Dedicated diagnostic features for lighting – Advanced shiffted PWM generation – ADC conversion synchronized on PWM  Communication interfaces March 2016 This is information on a product in full production. DocID17478 Rev 9 1/123 www.st.com SPC564Bxx-SPC56ECxx Table 1. Device summary Part number Package 1.5 MByte 2 MByte 3 MByte LQFP176 SPC564B64L7 SPC56EC64L7 SPC564B70L7 SPC56EC70L7 SPC564B74L7 SPC56EC74L7 LQFP208 SPC564B64L8 SPC56EC64L8 SPC564B70L8 SPC56EC70L8 SPC564B74L8 SPC56EC74L8 LBGA256 SPC56EC64B3 SPC56EC70B3 SPC56EC74B3 2/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Contents Contents 1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.1 NVUSRO [PAD3V5V(0)] field description . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.2 NVUSRO [PAD3V5V(1)] field description . . . . . . . . . . . . . . . . . . . . . . . 52 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.6 3.5.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.6.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 67 3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 67 3.8.2 VDD_BV options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.8.3 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69 3.9 Low voltage domain power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID17478 Rev 9 3/123 5 Contents SPC564Bxx-SPC56ECxx 3.11 3.10.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.10.2 Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 74 3.10.3 Flash memory start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . 75 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 75 3.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 75 3.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 76 3.12 Fast external crystal oscillator (4–40 MHz) electrical characteristics . . . . 77 3.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 80 3.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 83 3.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 85 3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.17.1 3.18 3.19 4 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Fast Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) . 96 3.18.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) . . . . 97 3.18.3 MII Async Inputs Signal Timing (CRS and COL) . . . . . . . . . . . . . . . . . . 97 3.18.4 MII Serial Management Channel Timing (MDIO and MDC) . . . . . . . . . . 98 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.19.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.19.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 4.2.1 LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.2 LQFP208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.3 LBGA256 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 114 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 DocID17478 Rev 9 5/123 5 List of tables SPC564Bxx-SPC56ECxx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 6/123 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SPC564Bxx and SPC56ECxx family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPC564Bxx and SPC56ECxx series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PAD3V5V(0) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PAD3V5V(1) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LBGA256 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 61 FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 62 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I/O supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Low voltage power domain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Code flash memory—Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Data flash memory—Program and erase specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 74 Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 79 Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 82 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 83 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 85 ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ADC conversion characteristics (10-bit ADC_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Conversion characteristics (12-bit ADC_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 MII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 MII Async Inputs Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 MII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. List of tables On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQFP208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LBGA256 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 DocID17478 Rev 9 7/123 7 List of figures SPC564Bxx-SPC56ECxx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. 8/123 SPC564Bxx and SPC56ECxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 176-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 208-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 256-pin BGA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Low voltage monitor vs. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 79 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 82 ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MII receive signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 MII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 MII async inputs timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 MII serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DSPI classic SPI timing–master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DSPI classic SPI timing–master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DSPI classic SPI timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DSPI classic SPI timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DSPI modified transfer format timing–master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 104 DSPI modified transfer format timing–master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 104 DSPI modified transfer format timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DSPI modified transfer format timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Timing diagram - JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LQFP208 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LBGA256 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx 1 Introduction 1.1 Document Overview Introduction This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the SPC564Bxx and SPC56ECxx device. To ensure a complete understanding of the device functionality, refer also to the SPC564Bxx and SPC56ECxx Reference Manual. 1.2 Description The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. The SPC564Bxx and SPC56ECxx family expands the range of the SPC560B microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. It also capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. DocID17478 Rev 9 9/123 122 Feature Package CPU Execution speed(2) SPC564B64 LQFP 176 LQFP 208 SPC56EC64 LQFP 176 LQFP 208 SPC564B70 LBGA LQFP 256 176 SPC56EC70 LQFP 208 LQFP 208 LBGA 256 LQFP 176 LQFP 208 SPC56EC74 LQFP 176 LQFP 208 LBGA 256 e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h Up to 120 MHz (e200z4d) Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h)(3) Up to 120 MHz (e200z4d) Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h)(3) Up to 120 MHz (e200z4d) Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h)(3) Code flash memory 1.5 MB 2 MB Data flash memory SRAM LQFP 176 SPC564B74 Introduction 10/123 Table 2. SPC564Bxx and SPC56ECxx family comparison(1) 3 MB 4 x16 KB 128 KB 192 KB 160 KB 256 KB DocID17478 Rev 9 MPU 192 KB 256 KB 16-entry eDMA(4) 32 ch 10-bit ADC dedicated(5), (6) 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch shared with 12-bit ADC(7) 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 10 ch 5 ch 10 ch 5 ch 10 ch 19 ch 12-bit ADC dedicated(8) CTU Total timer 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 19 ch 64 ch I/O(9) eMIOS 64 ch, 16-bit SCI (LINFlexD) 10 SPI (DSPI) 8 CAN (FlexCAN)(10) 6 SPC564Bxx-SPC56ECxx shared with 10-bit ADC(7) 5 ch Feature Package SPC564B64 LQFP 176 LQFP 208 SPC56EC64 LQFP 176 LQFP 208 SPC564B70 LBGA LQFP 256 176 LQFP 208 SPC56EC70 LQFP 176 FlexRay Yes STCU(11) Yes Ethernet I No Yes No LQFP 176 LQFP 208 SPC56EC74 LQFP 176 No LQFP 208 LBGA 256 Yes 1 32 kHz oscillator (SXOSC) Debug LBGA 256 Yes 2C GPIO(12) LQFP 208 SPC564B74 SPC564Bxx-SPC56ECxx Table 2. SPC564Bxx and SPC56ECxx family comparison(1) (continued) Yes 147 177 147 JTAG 177 199 147 177 Nexus 3+ DocID17478 Rev 9 Cryptographic Services Engine (CSE) 147 JTAG 177 199 Nexus 3+ 147 177 147 177 JTAG 199 Nexus 3+ Optional 1. Feature set dependent on selected peripheral multiplexing; table shows example. 2. Based on 125 C ambient operating temperature and subject to full device characterization. 3. The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs to run at 1/2 system frequency. There is a configurable e200z0 system clock divider for this purpose. 4. DMAMUX also included that allows for software selection of 32 out of a possible 57 sources. 5. Not shared with 12-bit ADC, but possibly shared with other alternate functions. 6. There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4 dedicated ANX channels. 7. 16x precision channels (ANP) and 3x standard (ANS). 8. Not shared with 10-bit ADC, but possibly shared with other alternate functions. 9. As a minimum, all timer channels can function as PWM or Input Capture and Output Control. Refer to the eMIOS section of the device reference manual for information on the channel configuration and functions. 10. CAN Sampler also included that allows ID of CAN message to be captured when in low power mode. 11. STCU controls MBIST activation and reporting. 12. Estimated I/O count for proposed packages based on multiplexing with peripherals. Introduction 11/123 Introduction 1.3 SPC564Bxx-SPC56ECxx Block diagram Figure 1 shows the detailed block diagram of the SPC564Bxx and SPC56ECxx. Figure 1. SPC564Bxx and SPC56ECxx block diagram FEC CSE Nexus Port FlexRay Nexus 3+ Nexus Voltage regulator NMI0 e200z0h NMI1 e200z4d Instructions (Master) Data (Master) Instructions (Master) Data (Master) MPU JTAG Port 64-bit 8 x 5 crossbar switch JTAGC SRAM 2  128 KB Code Flash Data Flash 2  1.5 MB 64 KB 2  SRAM controller Flash memory controller (Slave) Nexus 3+ NMI0 (Slave) (Slave) Interrupt requests from peripheral blocks NMI1 Clocks DMAMUX MPU registers INTC eDMA CMU 16 x Semaphores CAN Sampler ( Master) FMPLL STCU 8 RTC/API 4  STM SWT ECSM MC_RGM MC_CGM MC_ME MC_PCU PIT RTI BAM SSCM WKP Peripheral Bridge Interrupt Request 10 ch(1) 1  12-bit ADC SIUL Reset Control External Interrupt Request 27 ch or 33 ch(2) 1  10-bit ADC CTU 2  32 ch eMIOS 10  LINFlexD 8 DSPI I2C 6 FlexCAN IMUX GPIO & Pad Control (3) (3) I/O Legend: ADC BAM CSE CAN CMU CTU DMAMUX DSPI eDMA FlexCAN FEC eMIOS ECSM FMPLL FlexRay I2C IMUX INTC Notes: 12/123 Analog-to-Digital Converter Boot Assist Module Cryptographic Services Engine Controller Area Network (FlexCAN) Clock Monitor Unit Cross Triggering Unit DMA Channel Multiplexer Deserial Serial Peripheral Interface enhanced Direct Memory Access Controller Area Network controller modules Fast Ethernet Controller Enhanced Modular Input Output System Error Correction Status Module Frequency-Modulated Phase-Locked Loop FlexRay Communication Controller Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAGC LINFlexD MC_ME MC_CGM MC_PCU MC_RGM MPU Nexus NMI PIT_RTI RTC/API SIUL SRAM SSCM STM SWT STCU WKPU JTAG controller Local Interconnect Network Flexible with DMA sup Mode Entry Module Clock Generation Module Power Control Unit Reset Generation Module Memory Protection Unit Nexus Development Interface Non-Maskable Interrupt Periodic Interrupt Timer with Real-Time Interrupt Real-Time Clock/ Autonomous Periodic Interrupt System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Self Test Control Unit Wakeup Unit 1) 10 dedicated channels plus up to 19 shared channels. See the device-comparison table. 2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table. 3) 16 x precision channels (ANP) are mapped on input only I/O cells. DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Introduction Table 3 summarizes the functions of the blocks present on the SPC564Bxx and SPC56ECxx. Table 3. SPC564Bxx and SPC56ECxx series block summary Block Function Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Cryptographic Security Engine (CSE) Supports the encoding and decoding of any kind of data Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width DMA Channel Multiplexer (DMAMUX) Allows to route DMA sources (called slots) to DMA channels Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host (eDMA) processor via “n” programmable channels. Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Generates high-speed system clocks and supports programmable frequency modulation FlexRay (FlexRay communication Provides high-speed distributed control for advanced automotive applications controller) Fast Ethernet Controller (FEC) Ethernet Media Access Controller (MAC) designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks Internal multiplexer (IMUX) SIUL subblock Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests for both e200z0h and e200z4d cores JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode DocID17478 Rev 9 13/123 122 Introduction SPC564Bxx-SPC56ECxx Table 3. SPC564Bxx and SPC56ECxx series block summary (continued) Block Function LinFlexD (Local Interconnect Network Flexible with DMA support) Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Non-Maskable Interrupt (NMI) Handles external events that must produce an immediate response, such as power down detection Nexus Development Interface (NDI) Provides real-time development capabilities for e200z0h and e200z4d core processor Periodic interrupt timer/ Real Time Interrupt Timer (PIT_RTI) Produces periodic interrupts and triggers Real-time counter (RTC/API) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode). Supports autonomous periodic interrupt (API) function to generate a periodic wakeup request to exit a low power mode or an interrupt request Static random-access memory (SRAM) Provides storage for program code, constants, and variables Provides control over all the electrical pad controls and up 32 ports with 16 bits System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration System status and configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AutoSAR and operating system tasks Semaphores Provides the hardware support needed in multi-core systems for sharing resources and provides a simple mechanism to achieve lock/unlock operations via a single write access. Wake Unit (WKPU) Supports external sources that can generate interrupts or wakeup events, of which can cause non-maskable interrupt requests or wakeup events. 14/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions The available LQFP pinouts and the LBGA ballmaps are provided in the following figures. For functional port pin description, see Table 6. 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PB[2] PC[8] PC[13] PC[12] PI[0] PI[1] PI[2] PI[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV_A VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PI[4] PI[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 2. 176-pin LQFP configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 Top view 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV_B VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PI[13] PI[12] PI[11] VDD_LV VSS_LV PI[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] VDD_HV_ADC1 VSS_HV_ADC1 PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PB[3] PC[9] PC[14] PC[15] PJ[4] VDD_HV_A VSS_HV PH[15] PH[13] PH[14] PI[6] PI[7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV_A VSS_HV RESET VSS_LV VDD_LV VRC_CTRL PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] NOTE 1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV_A PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] PI[15] PI[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV_A VSS_HV PD[8] PB[4] 2 Package pinouts and signal descriptions 2)Availability of port pin alternate functions depends on product selection. DocID17478 Rev 9 15/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 PB[2] PC[8] PC[13] PC[12] PL[0] PK[15] PK[14] PK[13] PK[12] PK[11] PK[10] PK[9] PI[0] PI[1] PI[2] PI[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV_A VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PI[4] PI[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 3. 208-pin LQFP configuration LQFP208 Top view 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PJ[12] PJ[11] PA[4] PK[0] PJ[15] PJ[14] PJ[13] PA[13] PJ[10] PJ[9] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV_A PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] PI[15] PI[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV_A VSS_HV PD[8] PB[4] PB[3] PC[9] PC[14] PC[15] PJ[4] VDD_HV_A VSS_HV PH[15] PH[13] PH[14] P[I6] P[I7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV_A VSS_HV RESET VSS_LV VDD_LV VRC_CTRL PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PK[1] PK[2] PK[3] PK[4] PK[5] PK[6] PK[7] PK[8] PF[9] PF[8] PF[12] PC[6] NOTE 1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2) Availability of port pin alternate functions depends on product selection. 16/123 DocID17478 Rev 9 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV_B VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PI[13] PI[12] PI[11] PI[10] VDD_LV VSS_LV PI[9] PI[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_A VSS_HV PD[12] VDD_HV_ADC1 VSS_HV_ADC1 PB[11] PD[11] PD[10] PD[9] PJ[5] PJ[6] PJ[7] PJ[8] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0 SPC564Bxx-SPC56ECxx A B C D E F G H J K L M N P R T Package pinouts and signal descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC[15] PB[2] PC[13] PI[1] PE[7] PH[8] PE[2] PE[4] PC[4] PE[3] PH[9] PI[4] PH[11] PE[14] PA[10] PG[11] PH[13] PC[14] PC[8] PC[12] PI[3] PE[6] PH[5] PE[5] PC[5] PC[0] PC[2] PH[12] PG[10] PA[11] PA[9] PA[8] PH[14] VDD_HV _A PC[9] PL[0] PI[0] PH[7] PH[6] VSS_LV VDD_HV _A PA[5] PC[3] PE[15] PG[14] PE[12] PA[7] PE[13] PG[5] PI[6] PJ[4] PB[3] PK[15] PI[2] PH[4] VDD_LV PC[1] PH[10] PA[6] PI[5] PG[15] PF[14] PF[15] PH[2] PG[3] PI[7] PH[15] PG[2] VDD_LV VSS_LV PK[10] PK[9] PM[1] PM[0] PL[15] PL[14] PG[0] PG[1] PH[0] VDD_HV _A PA[2] PG[4] PA[1] PE[1] PL[2] PM[6] PL[1] PK[11] PM[5] PL[13] PL[12] PM[2] PH[1] PH[3] PG[12] PG[13] PE[8] PE[0] PE[10] PA[0] PL[3] VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV PK[12] VDD_HV _B PI[13] PI[12] PA[3] PE[9] VDD_HV _A PE[11] PK[1] PL[4] VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV VSS_HV PK[13] VDD_HV _A VDD_LV VSS_LV PI[11] VSS_HV VRC_CT RL VDD_LV PG[9] PL[5] VSS_LV VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV PK[14] PD[15] PI[8] PI[9] PI[10] RESET VSS_LV PG[8] PC[11] PL[6] VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[3] PD[14] PD[13] PB[14] PB[15] PC[10] PG[7] PB[0] PK[2] PL[7] VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[4] PD[12] PB[12] PB[13] VDD_HV _ADC1 L PG[6] PB[1] PK[4] PF[9] PK[5] PK[6] PK[7] PK[8] PL[8] PL[9] PL[10] PL[11] PB[11] PD[10] PD[11] VSS_HV _ADC1 M PK[3] PF[8] PC[6] PC[7] PJ[13] VDD_HV _A PB[10] PF[6] VDD_HV _A PJ[1] PD[2] PJ[5] PB[5] PB[6] PJ[6] PD[9] PF[12] PF[10] PF[13] PA[14] PJ[9] PA[12] PF[0] PF[5] PF[7] PJ[3] PI[15] PD[4] PD[7] PD[8] PJ[8] PJ[7] PF[11] PA[15] PJ[11] PJ[15] PA[13] PF[2] PF[3] PF[4] VDD_LV PJ[2] PJ[0] PD[0] PD[3] PD[6] VDD_HV _ADC0 PB[7] PJ[12] PA[4] PK[0] PJ[14] PJ[10] PF[1] XTAL EXTAL VSS_LV PB[9] PB[8] PI[14] PD[1] PD[5] VSS_HV _ADC0 PB[4] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K N P R T Notes: 1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], PA[3], PM[3], and PM[4]. 2)Availability of port pin alternate functions depends on product selection. Figure 4. 256-pin BGA configuration DocID17478 Rev 9 17/123 122 Package pinouts and signal descriptions 2.1 SPC564Bxx-SPC56ECxx Pad types In the device the following types of pads are available for system pins and functional port pins: S = Slow(a) M = Medium(a),(b) F = Fast(a),(b) I = Input only with analog feature(a) A = Analog 2.2 System pins The system pins are listed in Table 4. Table 4. System pin descriptions Pad type RESET config. LQFP 208 LBGA 256 Port pin LQFP 176 Pin number I/O M Input, weak pull-up only after PHASE2 29 29 K1 I/O direction Function RESET Bidirectional reset with Schmitt-Trigger characteristics and noise filter. EXTAL Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator bypass mode is used. I A(1) — 58 74 T8 XTAL Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode.  Analog input for the clock generator when the oscillator is in bypass mode. I/O A(1) — 56 72 T7 1. For analog pads, it is not recommended to enable IBE if APC is enabled to avoid extra current in middle range voltage. a. See the I/O pad electrical characteristics in the device datasheet for details. b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. For example, Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by default. Only exception is PC[1] which is in medium configuration by default (refer to PCR.SRC in the reference manual, Pad Configuration Registers (PCR0—PCR198)). 18/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx 2.3 Package pinouts and signal descriptions Functional ports The functional port pins are listed in Table 5. Table 5. Functional port pin descriptions LQFP 208 LBGA256 PA[4] LQFP 176 PA[3] RESET config. PA[2] Pad type PA[1] I/O direction(2) PA[0] Function Peripheral Port pin Alternate function(1) Pin number PCR[0] AF0 AF1 AF2 AF3 — — GPIO[0] E0UC[0] CLKOUT E0UC[13] WKPU[19] CAN1RX SIUL eMIOS_0 MC_CGM eMIOS_0 WKPU FlexCAN_1 I/O I/O O I/O I I M/S Tristate 24 24 G4 PCR[1] AF0 AF1 AF2 AF3 — — — GPIO[1] E0UC[1] — — WKPU[2] CAN3RX NMI[0](3) SIUL eMIOS_0 — — WKPU FlexCAN_3 WKPU I/O I/O — — I I I S Tristate 19 19 F3 PCR[2] AF0 AF1 AF2 AF3 — — GPIO[2] E0UC[2] — MA[2] WKPU[3] NMI[1](3) SIUL eMIOS_0 — ADC_0 WKPU WKPU I/O I/O — O I I S Tristate 17 17 F1 PCR[3] AF0 AF1 AF2 AF3 — — — GPIO[3] E0UC[3] LIN5TX CS4_1 RX_ER_CLK EIRQ[0] ADC1_S[0] SIUL eMIOS_0 LINFlexD_5 DSPI_1 FEC SIUL ADC_1 I/O I/O O O I I I M/S Tristate 114 138 G16 PCR[4] AF0 AF1 AF2 AF3 — — GPIO[4] E0UC[4] — CS0_1 LIN5RX WKPU[9] SIUL eMIOS_0 — DSPI_1 LINFlexD_5 WKPU I/O I/O — I/O I I S Tristate 51 61 T2 PCR DocID17478 Rev 9 19/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) Alternate function(1) Function Peripheral I/O direction(2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 Pin number AF0 AF1 AF2 GPIO[5] E0UC[5] LIN4TX SIUL eMIOS_0 LINFlexD_4 I/O I/O O M/S Tristate 146 170 C10 PCR[6] AF0 AF1 AF2 AF3 — — GPIO[6] E0UC[6] — CS1_1 LIN4RX EIRQ[1] SIUL eMIOS_0 — DSPI_1 LINFlexD_4 SIUL I/O I/O — O I I S Tristate 147 171 D11 PCR[7] AF0 AF1 AF2 AF3 — — — GPIO[7] E0UC[7] LIN3TX — RXD[2] EIRQ[2] ADC1_S[1] SIUL eMIOS_0 LINFlexD_3 — FEC SIUL ADC_1 I/O I/O O — I I I M/S Tristate 128 152 C15 PCR[8] AF0 AF1 AF2 AF3 — — — — GPIO[8] E0UC[8] E0UC[14] — RXD[1] EIRQ[3] ABS[0] LIN3RX SIUL eMIOS_0 eMIOS_0 — FEC SIUL MC_RGM LINFlexD_3 I/O I/O I/O — I I I I M/S Input, weak pull-up 129 153 B16 PCR[9] AF0 AF1 AF2 AF3 — — GPIO[9] E0UC[9] — CS2_1 RXD[0] FAB SIUL eMIOS_0 — DSPI1 FEC MC_RGM I/O I/O — O I I M/S Pulldown 130 154 B15 Port pin PCR PA[5] PCR[5] PA[6] PA[7] PA[8] PA[9] 20/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LBGA256 PA[15] LQFP 208 PA[14] LQFP 176 PA[13] RESET config. PA[12] Pad type PA[11] I/O direction(2) PA[10] Function Peripheral Port pin Alternate function(1) Pin number PCR[10] AF0 AF1 AF2 AF3 — — — GPIO[10] E0UC[10] SDA LIN2TX COL ADC1_S[2] SIN_1 SIUL eMIOS_0 I2C LINFlexD_2 FEC ADC_1 DSPI_1 I/O I/O I/O O I I I M/S Tristate 131 155 A15 PCR[11] AF0 AF1 AF2 AF3 — — — — GPIO[11] E0UC[11] SCL — RX_ER EIRQ[16] LIN2RX ADC1_S[3] SIUL eMIOS_0 I2C — FEC SIUL LINFlexD_2 ADC_1 I/O I/O I/O — I I I I M/S Tristate 132 156 B14 PCR[12] AF0 AF1 AF2 AF3 — — GPIO[12] — E0UC[28] CS3_1 EIRQ[17] SIN_0 SIUL — eMIOS_0 DSPI1 SIUL DSPI_0 I/O — I/O O I I S Tristate 53 69 P6 PCR[13] AF0 AF1 AF2 AF3 GPIO[13] SOUT_0 E0UC[29] — SIUL DSPI_0 eMIOS_0 — I/O O I/O — M/S Tristate 52 66 R5 PCR[14] AF0 AF1 AF2 AF3 — GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4] SIUL DSPI_0 DSPI_0 eMIOS_0 SIUL I/O I/O I/O I/O I M/S Tristate 50 58 P4 PCR[15] AF0 AF1 AF2 AF3 — GPIO[15] CS0_0 SCK_0 E0UC[1] WKPU[10] SIUL DSPI_0 DSPI_0 eMIOS_0 WKPU I/O I/O I/O I/O I M/S Tristate 48 56 R2 PCR DocID17478 Rev 9 21/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 22/123 LBGA256 PB[5] LQFP 208 PB[4] LQFP 176 PB[3] RESET config. PB[2] Pad type PB[1] I/O direction(2) PB[0] Function Peripheral Port pin Alternate function(1) Pin number PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX E0UC[30] LIN0TX SIUL FlexCAN_0 eMIOS_0 LINFlexD_0 I/O O I/O I M/S Tristate 39 39 L3 PCR[17] AF0 AF1 AF2 — — — GPIO[17] — E0UC[31] LIN0RX WKPU[4] CAN0RX SIUL — eMIOS_0 LINFlexD_0 WKPU FlexCAN_0 I/O — I/O I I I S Tristate 40 40 M2 PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX SDA E0UC[30] SIUL LINFlexD_0 I2C eMIOS_0 I/O O I/O I/O M/S Tristate 176 208 A2 PCR[19] AF0 AF1 AF2 AF3 — — GPIO[19] E0UC[31] SCL — WKPU[11] LIN0RX SIUL eMIOS_0 I2C — WKPU LINFlexD_0 I/O I/O I/O — I I S Tristate 1 1 D4 PCR[20] AF0 AF1 AF2 AF3 — — GPI[20] — — — ADC0_P[0] ADC1_P[0] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 88 104 T16 PCR[21] AF0 AF1 AF2 AF3 — — GPI[21] — — — ADC0_P[1] ADC1_P[1] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 91 107 N13 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LQFP 208 LBGA256 PB[10] LQFP 176 PB[9](5) RESET config. PB[8] Pad type PB[7] I/O direction(2) PB[6] Function Peripheral Port pin Alternate function(1) Pin number PCR[22] AF0 AF1 AF2 AF3 — — GPI[22] — — — ADC0_P[2] ADC1_P[2] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 92 108 N14 PCR[23] AF0 AF1 AF2 AF3 — — GPI[23] — — — ADC0_P[3] ADC1_P[3] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 93 109 R16 PCR[24] AF0 AF1 AF2 AF3 — — — — GPI[24] — — — ADC0_S[0] ADC1_S[4] WKPU[25] OSC32k_XTAL(4) SIUL — — — ADC_0 ADC_1 WKPU SXOSC I — — — I I I I I — 61 77 T11 PCR[25] AF0 AF1 AF2 AF3 — — — — I — — — I I I I I — 60 76 T10 4) SIUL — — — ADC_0 ADC_1 WKPU SXOSC GPIO[26] SOUT_1 CAN3TX — ADC0_S[2] ADC1_S[6] WKPU[8] SIUL DSPI_1 FlexCAN_3 — ADC_0 ADC_1 WKPU I/O O — — I I I S Tristate 62 78 N7 PCR PCR[26] AF0 AF1 AF2 AF3 — — — GPI[25] — — — ADC0_S[1] ADC1_S[5] WKPU[26] OSC32k_EXTAL( DocID17478 Rev 9 23/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) PC[1](6) 24/123 LBGA256 PC[0](6) LQFP 208 PB[15] LQFP 176 PB[14] RESET config. PB[13] Pad type PB[12] I/O direction(2) PB[11] Function Peripheral Port pin Alternate function(1) Pin number PCR[27] AF0 AF1 AF2 AF3 — GPIO[27] E0UC[3] — CS0_0 ADC0_S[3] SIUL eMIOS_0 — DSPI_0 ADC_0 I/O I/O — I/O I S Tristate 97 117 M13 PCR[28] AF0 AF1 AF2 AF3 — GPIO[28] E0UC[4] — CS1_0 ADC0_X[0] SIUL eMIOS_0 — DSPI_0 ADC_0 I/O I/O — O I S Tristate 101 123 L14 PCR[29] AF0 AF1 AF2 AF3 — GPIO[29] E0UC[5] — CS2_0 ADC0_X[1] SIUL eMIOS_0 — DSPI_0 ADC_0 I/O I/O — O I S Tristate 103 125 L15 PCR[30] AF0 AF1 AF2 AF3 — GPIO[30] E0UC[6] — CS3_0 ADC0_X[2] SIUL eMIOS_0 — DSPI_0 ADC_0 I/O I/O — O I S Tristate 105 127 K15 PCR[31] AF0 AF1 AF2 AF3 — GPIO[31] E0UC[7] — CS4_0 ADC0_X[3] SIUL eMIOS_0 — DSPI_0 ADC_0 I/O I/O — O I S Tristate 107 129 K16 PCR[32] AF0 AF1 AF2 AF3 GPIO[32] — TDI — SIUL — JTAGC — I/O — I — M/S Input, weak pull-up 154 178 B10 PCR[33] AF0 AF1 AF2 AF3 GPIO[33] — TDO — SIUL — JTAGC — I/O — O — F/M Tristate 149 173 D9 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LBGA256 PC[7] LQFP 208 PC[6] LQFP 176 PC[5] RESET config. PC[4] Pad type PC[3] M/S Tristate 145 169 B11 S Tristate 144 168 C11 M/S Tristate 159 183 A9 I/O O O — O I M/S Tristate 158 182 B9 SIUL LINFlexD_1 eMIOS_1 — I/O O I/O — S Tristate 44 52 N3 SIUL — eMIOS_1 — LINFlexD_1 WKPU I/O — I/O — I I S Tristate 45 53 N4 Function Peripheral PC[2] I/O I/O O — I Alternate function(1) Port pin I/O direction(2) Pin number PCR[34] AF0 AF1 AF2 AF3 — GPIO[34] SCK_1 CAN4TX — EIRQ[5] SIUL DSPI_1 FlexCAN_4 — SIUL GPIO[35] CS0_1 MA[0] — CAN1RX CAN4RX EIRQ[6] SIUL DSPI_1 ADC_0 — FlexCAN_1 FlexCAN_4 SIUL I/O I/O O PCR[35] AF0 AF1 AF2 AF3 — — — GPIO[36] E1UC[31] — SIUL eMIOS_1 — I/O I/O — PCR[36] AF0 AF1 AF2 AF3 ALT4 — — — FR_B_TX_EN SIN_1 CAN3RX EIRQ[18] Flexray DSPI_1 FlexCAN_3 SIUL O I I I PCR[37] AF0 AF1 AF2 AF3 ALT4 — GPIO[37] SOUT_1 CAN3TX — FR_A_TX EIRQ[7] SIUL DSPI_1 FlexCAN_3 — Flexray SIUL PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX E1UC[28] — PCR[39] AF0 AF1 AF2 AF3 — — GPIO[39] — E1UC[29] — LIN1RX WKPU[12] PCR DocID17478 Rev 9 I I I 25/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 26/123 LBGA256 PC[13] LQFP 208 PC[12] LQFP 176 PC[11] RESET config. PC[10] Pad type PC[9] I/O direction(2) PC[8] Function Peripheral Port pin Alternate function(1) Pin number PCR[40] AF0 AF1 AF2 AF3 GPIO[40] LIN2TX E0UC[3] — SIUL LINFlexD_2 eMIOS_0 — I/O O I/O — S Tristate 175 207 B3 PCR[41] AF0 AF1 AF2 AF3 — — GPIO[41] — E0UC[7] — LIN2RX WKPU[13] SIUL — eMIOS_0 — LINFlexD_2 WKPU I/O — I/O — I I S Tristate 2 2 C3 PCR[42] AF0 AF1 AF2 AF3 GPIO[42] CAN1TX CAN4TX MA[1] SIUL FlexCAN_1 FlexCAN_4 ADC_0 I/O O O O M/S Tristate 36 36 L1 PCR[43] AF0 AF1 AF2 AF3 — — — GPIO[43] — — MA[2] CAN1RX CAN4RX WKPU[5] SIUL — — ADC_0 FlexCAN_1 FlexCAN_4 WKPU I/O — — O I I I S Tristate 35 35 K4 PCR[44] AF0 AF1 AF2 AF3 ALT4 — — GPIO[44] E0UC[12] — — FR_DBG[0] SIN_2 EIRQ[19] SIUL eMIOS_0 — — Flexray DSPI_2 SIUL I/O I/O — — O I I M/S Tristate 173 205 B4 PCR[45] AF0 AF1 AF2 AF3 ALT4 GPIO[45] E0UC[13] SOUT_2 — FR_DBG[1] SIUL eMIOS_0 DSPI_2 — Flexray I/O I/O O — O M/S Tristate 174 206 A3 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LQFP 208 LBGA256 PD[2] LQFP 176 PD[1] RESET config. PD[0] Pad type PC[15] I/O direction(2) PC[14] Function Peripheral Port pin Alternate function(1) Pin number PCR[46] AF0 AF1 AF2 AF3 ALT4 — GPIO[46] E0UC[14] SCK_2 — FR_DBG[2] EIRQ[8] SIUL eMIOS_0 DSPI_2 — Flexray SIUL I/O I/O I/O — O I M/S Tristate 3 3 B2 PCR[47] AF0 AF1 AF2 AF3 ALT4 GPIO[47] E0UC[15] CS0_2 — FR_DBG[3] EIRQ[20] SIUL eMIOS_0 DSPI_2 — Flexray SIUL I/O I/O I/O — O I M/S Tristate 4 4 A1 PCR[48] AF0 AF1 AF2 AF3 — — — GPI[48] — — — ADC0_P[4] ADC1_P[4] WKPU[27] SIUL — — — ADC_0 ADC_1 WKPU I — — — I I I I Tristate 77 93 R12 PCR[49] AF0 AF1 AF2 AF3 — — — GPI[49] — — — ADC0_P[5] ADC1_P[5] WKPU[28] SIUL — — — ADC_0 ADC_1 WKPU I — — — I I I I Tristate 78 94 T13 PCR[50] AF0 AF1 AF2 AF3 — — GPI[50] — — — ADC0_P[6] ADC1_P[6] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 79 95 N11 PCR DocID17478 Rev 9 27/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 28/123 LBGA256 PD[8] LQFP 208 PD[7] LQFP 176 PD[6] RESET config. PD[5] Pad type PD[4] I/O direction(2) PD[3] Function Peripheral Port pin Alternate function(1) Pin number PCR[51] AF0 AF1 AF2 AF3 — — GPI[51] — — — ADC0_P[7] ADC1_P[7] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 80 96 R13 PCR[52] AF0 AF1 AF2 AF3 — — GPI[52] — — — ADC0_P[8] ADC1_P[8] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 81 97 P12 PCR[53] AF0 AF1 AF2 AF3 — — GPI[53] — — — ADC0_P[9] ADC1_P[9] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 82 98 T14 PCR[54] AF0 AF1 AF2 AF3 — — GPI[54] — — — ADC0_P[10] ADC1_P[10] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 83 99 R14 PCR[55] AF0 AF1 AF2 AF3 — — GPI[55] — — — ADC0_P[11] ADC1_P[11] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 84 100 P13 PCR[56] AF0 AF1 AF2 AF3 — — GPI[56] — — — ADC0_P[12] ADC1_P[12] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 87 103 P14 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LBGA256 PD[14] LQFP 208 PD[13] LQFP 176 PD[12] RESET config. PD[11] Pad type PD[10] I/O direction(2) PD[9] Function Peripheral Port pin Alternate function(1) Pin number PCR[57] AF0 AF1 AF2 AF3 — — GPI[57] — — — ADC0_P[13] ADC1_P[13] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 94 114 N16 PCR[58] AF0 AF1 AF2 AF3 — — GPI[58] — — — ADC0_P[14] ADC1_P[14] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 95 115 M14 PCR[59] AF0 AF1 AF2 AF3 — — GPI[59] — — — ADC0_P[15] ADC1_P[15] SIUL — — — ADC_0 ADC_1 I — — — I I I Tristate 96 116 M15 PCR[60] AF0 AF1 AF2 AF3 — GPIO[60] CS5_0 E0UC[24] — ADC0_S[4] SIUL DSPI_0 eMIOS_0 — ADC_0 I/O O I/O — I S Tristate 100 120 L13 PCR[61] AF0 AF1 AF2 AF3 — GPIO[61] CS0_1 E0UC[25] — ADC0_S[5] SIUL DSPI_1 eMIOS_0 — ADC_0 I/O I/O I/O — I S Tristate 102 124 K14 PCR[62] AF0 AF1 AF2 AF3 ALT4 — GPIO[62] CS1_1 E0UC[26] — FR_DBG[0] ADC0_S[6] SIUL DSPI_1 eMIOS_0 — Flexray ADC_0 I/O O I/O — O I S Tristate 104 126 K13 PCR DocID17478 Rev 9 29/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 30/123 LBGA256 PE[4] LQFP 208 PE[3] LQFP 176 PE[2] RESET config. PE[1] Pad type PE[0] I/O direction(2) PD[15] Function Peripheral Port pin Alternate function(1) Pin number PCR[63] AF0 AF1 AF2 AF3 ALT4 — GPIO[63] CS2_1 E0UC[27] — FR_DBG[1] ADC0_S[7] SIUL DSPI_1 eMIOS_0 — Flexray ADC_0 I/O O I/O — O I S Tristate 106 128 J13 PCR[64] AF0 AF1 AF2 AF3 — — GPIO[64] E0UC[16] — — CAN5RX WKPU[6] SIUL eMIOS_0 — — FlexCAN_5 WKPU I/O I/O — — I I S Tristate 18 18 G2 PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] CAN5TX — SIUL eMIOS_0 FlexCAN_5 — I/O I/O O — M/S Tristate 20 20 F4 PCR[66] AF0 AF1 AF2 AF3 ALT4 — — GPIO[66] E0UC[18] — — FR_A_TX_EN SIN_1 EIRQ[21] SIUL eMIOS_0 — — Flexray DSPI_1 SIUL I/O I/O — — O I I M/S Tristate 156 180 A7 PCR[67] AF0 AF1 AF2 AF3 — — GPIO[67] E0UC[19] SOUT_1 — FR_A_RX WKPU[29] SIUL eMIOS_0 DSPI_1 — Flexray WKPU I/O I/O O — I I M/S Tristate 157 181 A10 PCR[68] AF0 AF1 AF2 AF3 ALT4 — GPIO[68] E0UC[20] SCK_1 — FR_B_TX EIRQ[9] SIUL eMIOS_0 DSPI_1 — Flexray SIUL I/O I/O I/O — O I M/S Tristate 160 184 A8 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LBGA256 PE[10] LQFP 208 PE[9] LQFP 176 PE[8] RESET config. PE[7] Pad type PE[6] I/O direction(2) PE[5] Function Peripheral Port pin Alternate function(1) Pin number PCR[69] AF0 AF1 AF2 AF3 — — GPIO[69] E0UC[21] CS0_1 MA[2] FR_B_RX WKPU[30] SIUL eMIOS_0 DSPI_1 ADC_0 Flexray WKPU I/O I/O I/O O I I M/S Tristate 161 185 B8 PCR[70] AF0 AF1 AF2 AF3 — GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[22] SIUL eMIOS_0 DSPI_0 ADC_0 SIUL I/O I/O O O I M/S Tristate 167 191 B6 PCR[71] AF0 AF1 AF2 AF3 — GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[23] SIUL eMIOS_0 DSPI_0 ADC_0 SIUL I/O I/O O O I M/S Tristate 168 192 A5 PCR[72] AF0 AF1 AF2 AF3 GPIO[72] CAN2TX E0UC[22] CAN3TX SIUL FlexCAN_2 eMIOS_0 FlexCAN_3 I/O O I/O O M/S Tristate 21 21 G1 PCR[73] AF0 AF1 AF2 AF3 — — — GPIO[73] — E0UC[23] — WKPU[7] CAN2RX CAN3RX SIUL — eMIOS_0 — WKPU FlexCAN_2 FlexCAN_3 I/O — I/O — I I I S Tristate 22 22 H1 PCR[74] AF0 AF1 AF2 AF3 — GPIO[74] LIN3TX CS3_1 E1UC[30] EIRQ[10] SIUL LINFlexD_3 DSPI_1 eMIOS_1 SIUL I/O O O I/O I S Tristate 23 23 G3 PCR DocID17478 Rev 9 31/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 32/123 LBGA256 PF[0] LQFP 208 PE[15] LQFP 176 PE[14] RESET config. PE[13] Pad type PE[12] I/O direction(2) PE[11] Function Peripheral Port pin Alternate function(1) Pin number PCR[75] AF0 AF1 AF2 AF3 — — GPIO[75] E0UC[24] CS4_1 — LIN3RX WKPU[14] SIUL eMIOS_0 DSPI_1 — LINFlexD_3 WKPU I/O I/O O — I I S Tristate 25 25 H3 PCR[76] AF0 AF1 AF2 AF3 — — — — GPIO[76] — E1UC[19] — CRS SIN_2 EIRQ[11] ADC1_S[7] SIUL — eMIOS_1 — FEC DSPI_2 SIUL ADC_1 I/O — I/O — I I I I M/S Tristate 133 157 C14 PCR[77] AF0 AF1 AF2 AF3 — GPIO[77] SOUT_2 E1UC[20] — RXD[3] SIUL DSPI_2 eMIOS_1 — FEC I/O O I/O — I M/S Tristate 127 151 C16 PCR[78] AF0 AF1 AF2 AF3 — GPIO[78] SCK_2 E1UC[21] — EIRQ[12] SIUL DSPI_2 eMIOS_1 — SIUL I/O I/O I/O — I M/S Tristate 136 160 A14 PCR[79] AF0 AF1 AF2 AF3 GPIO[79] CS0_2 E1UC[22] SCK_6 SIUL DSPI_2 eMIOS_1 DSPI_6 I/O I/O I/O I/O M/S Tristate 137 161 C12 PCR[80] AF0 AF1 AF2 AF3 — GPIO[80] E0UC[10] CS3_1 — ADC0_S[8] SIUL eMIOS_0 DSPI_1 — ADC_0 I/O I/O O — I S Tristate 63 79 P7 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) PF[7] LBGA256 PF[6] LQFP 208 PF[5] LQFP 176 PF[4] RESET config. PF[3] Pad type PF[2] I/O direction(2) PF[1] Function Peripheral Port pin Alternate function(1) Pin number PCR[81] AF0 AF1 AF2 AF3 — GPIO[81] E0UC[11] CS4_1 — ADC0_S[9] SIUL eMIOS_0 DSPI_1 — ADC_0 I/O I/O O — I S Tristate 64 80 T6 PCR[82] AF0 AF1 AF2 AF3 — GPIO[82] E0UC[12] CS0_2 — ADC0_S[10] SIUL eMIOS_0 DSPI_2 — ADC_0 I/O I/O I/O — I S Tristate 65 81 R6 PCR[83] AF0 AF1 AF2 AF3 — GPIO[83] E0UC[13] CS1_2 — ADC0_S[11] SIUL eMIOS_0 DSPI_2 — ADC_0 I/O I/O O — I S Tristate 66 82 R7 PCR[84] AF0 AF1 AF2 AF3 — GPIO[84] E0UC[14] CS2_2 — ADC0_S[12] SIUL eMIOS_0 DSPI_2 — ADC_0 I/O I/O O — I S Tristate 67 83 R8 PCR[85] AF0 AF1 AF2 AF3 — GPIO[85] E0UC[22] CS3_2 — ADC0_S[13] SIUL eMIOS_0 DSPI_2 — ADC_0 I/O I/O O — I S Tristate 68 84 P8 PCR[86] AF0 AF1 AF2 AF3 — GPIO[86] E0UC[23] CS1_1 — ADC0_S[14] SIUL eMIOS_0 DSPI_1 — ADC_0 I/O I/O O — I S Tristate 69 85 N8 PCR[87] AF0 AF1 AF2 AF3 — GPIO[87] — CS2_1 — ADC0_S[15] SIUL — DSPI_1 — ADC_0 I/O — O — I S Tristate 70 86 P9 PCR DocID17478 Rev 9 33/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 34/123 LBGA256 PF[13] LQFP 208 PF[12] LQFP 176 PF[11] RESET config. PF[10] Pad type PF[9] I/O direction(2) PF[8] Function Peripheral Port pin Alternate function(1) Pin number PCR[88] AF0 AF1 AF2 AF3 GPIO[88] CAN3TX CS4_0 CAN2TX SIUL FlexCAN_3 DSPI_0 FlexCAN_2 I/O O O O M/S Tristate 42 50 N2 PCR[89] AF0 AF1 AF2 AF3 — — — GPIO[89] E1UC[1] CS5_0 — CAN2RX CAN3RX WKPU[22] SIUL eMIOS_1 DSPI_0 — FlexCAN_2 FlexCAN_3 WKPU I/O I/O O — I I I S Tristate 41 49 M4 PCR[90] AF0 AF1 AF2 AF3 GPIO[90] CS1_0 LIN4TX E1UC[2] SIUL DSPI_0 LINFlexD_4 eMIOS_1 I/O O O I/O M/S Tristate 46 54 P2 PCR[91] AF0 AF1 AF2 AF3 — — GPIO[91] CS2_0 E1UC[3] — LIN4RX WKPU[15] SIUL DSPI_0 eMIOS_1 — LINFlexD_4 WKPU I/O O I/O — I I S Tristate 47 55 R1 PCR[92] AF0 AF1 AF2 AF3 GPIO[92] E1UC[25] LIN5TX — SIUL eMIOS_1 LINFlexD_5 — I/O I/O O — M/S Tristate 43 51 P1 PCR[93] AF0 AF1 AF2 AF3 — — GPIO[93] E1UC[26] — — LIN5RX WKPU[16] SIUL eMIOS_1 — — LINFlexD_5 WKPU I/O I/O — — I I S Tristate 49 57 P3 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LBGA256 PG[3] LQFP 208 PG[2] LQFP 176 PG[1] RESET config. PG[0] Pad type PF[15] I/O direction(2) PF[14] Function Peripheral Port pin Alternate function(1) Pin number PCR[94] AF0 AF1 AF2 AF3 ALT4 GPIO[94] CAN4TX E1UC[27] CAN1TX MDIO SIUL FlexCAN_4 eMIOS_1 FlexCAN_1 FEC I/O O I/O O I/O M/S Tristate 126 150 D14 PCR[95] AF0 AF1 AF2 AF3 — — — — GPIO[95] E1UC[4] — — RX_DV CAN1RX CAN4RX EIRQ[13] SIUL eMIOS_1 — — FEC FlexCAN_1 FlexCAN_4 SIUL I/O I/O — — I I I I M/S Tristate 125 149 D15 PCR[96] AF0 AF1 AF2 AF3 ALT4 GPIO[96] CAN5TX E1UC[23] — MDC SIUL FlexCAN_5 eMIOS_1 — FEC I/O O I/O — O F Tristate 122 146 E13 PCR[97] AF0 AF1 AF2 AF3 — — — GPIO[97] — E1UC[24] — TX_CLK CAN5RX EIRQ[14] SIUL — eMIOS_1 — FEC FlexCAN_5 SIUL I/O — I/O — I I I M Tristate 121 145 E14 PCR[98] AF0 AF1 AF2 AF3 GPIO[98] E1UC[11] SOUT_3 — SIUL eMIOS_1 DSPI_3 — I/O I/O O — M/S Tristate 16 16 E4 PCR[99] AF0 AF1 AF2 AF3 — GPIO[99] E1UC[12] CS0_3 — WKPU[17] SIUL eMIOS_1 DSPI_3 — WKPU I/O I/O I/O — I S Tristate 15 15 E1 PCR DocID17478 Rev 9 35/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 36/123 LBGA256 PG[9] LQFP 208 PG[8] LQFP 176 PG[7] RESET config. PG[6] Pad type PG[5] I/O direction(2) PG[4] Function Peripheral Port pin Alternate function(1) Pin number PCR[100] AF0 AF1 AF2 AF3 GPIO[100] E1UC[13] SCK_3 — SIUL eMIOS_1 DSPI_3 — I/O I/O I/O — M/S Tristate 14 14 F2 PCR[101] AF0 AF1 AF2 AF3 — — GPIO[101] E1UC[14] — — WKPU[18] SIN_3 SIUL eMIOS_1 — — WKPU DSPI_3 I/O I/O — — I I S Tristate 13 13 D1 PCR[102] AF0 AF1 AF2 AF3 GPIO[102] E1UC[15] LIN6TX — SIUL eMIOS_1 LINFlexD_6 — I/O I/O O — M/S Tristate 38 38 M1 PCR[103] AF0 AF1 AF2 AF3 — — GPIO[103] E1UC[16] E1UC[30] — LIN6RX WKPU[20] SIUL eMIOS_1 eMIOS_1 — LINFlexD_6 WKPU I/O I/O I/O — I I S Tristate 37 37 L2 PCR[104] AF0 AF1 AF2 AF3 — GPIO[104] E1UC[17] LIN7TX CS0_2 EIRQ[15] SIUL eMIOS_1 LINFlexD_7 DSPI_2 SIUL I/O I/O O I/O I S Tristate 34 34 K3 PCR[105] AF0 AF1 AF2 AF3 — — GPIO[105] E1UC[18] — SCK_2 LIN7RX WKPU[21] SIUL eMIOS_1 — DSPI_2 LINFlexD_7 WKPU I/O I/O — I/O I I S Tristate 33 33 J4 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) PH[0] LBGA256 PG[15] LQFP 208 PG[14] LQFP 176 PG[13] RESET config. PG[12] Pad type PG[11] I/O direction(2) PG[10] Function Peripheral Port pin Alternate function(1) Pin number PCR[106] AF0 AF1 AF2 AF3 — GPIO[106] E0UC[24] E1UC[31] — SIN_4 SIUL eMIOS_0 eMIOS_1 — DSPI_4 I/O I/O I/O — I S Tristate 138 162 B13 PCR[107] AF0 AF1 AF2 AF3 GPIO[107] E0UC[25] CS0_4 CS0_6 SIUL eMIOS_0 DSPI_4 DSPI_6 I/O I/O I/O I/O M/S Tristate 139 163 A16 PCR[108] AF0 AF1 AF2 AF3 ALT4 GPIO[108] E0UC[26] SOUT_4 — TXD[2] SIUL eMIOS_0 DSPI_4 — FEC I/O I/O O — O M/S Tristate 116 140 F15 PCR[109] AF0 AF1 AF2 AF3 ALT4 GPIO[109] E0UC[27] SCK_4 — TXD[3] SIUL eMIOS_0 DSPI_4 — FEC I/O I/O I/O — O M/S Tristate 115 139 F16 PCR[110] AF0 AF1 AF2 AF3 — GPIO[110] E1UC[0] LIN8TX — SIN_6 SIUL eMIOS_1 LINFlexD_8 — DSPI_6 I/O I/O O — I S Tristate 134 158 C13 PCR[111] AF0 AF1 AF2 AF3 — GPIO[111] E1UC[1] SOUT_6 — LIN8RX SIUL eMIOS_1 DSPI_6 — LINFlexD_8 I/O I/O O — I M/S Tristate 135 159 D13 PCR[112] AF0 AF1 AF2 AF3 ALT4 — GPIO[112] E1UC[2] — — TXD[1] SIN_1 SIUL eMIOS_1 — — FEC DSPI_1 I/O I/O — — O I M/S Tristate 117 141 E15 PCR DocID17478 Rev 9 37/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) PH[7] 38/123 LBGA256 PH[6] LQFP 208 PH[5] LQFP 176 PH[4] RESET config. PH[3] Pad type PH[2] I/O direction(2) PH[1] Function Peripheral Port pin Alternate function(1) Pin number PCR[113] AF0 AF1 AF2 AF3 ALT4 GPIO[113] E1UC[3] SOUT_1 — TXD[0] SIUL eMIOS_1 DSPI_1 — FEC I/O I/O O — O M/S Tristate 118 142 F13 PCR[114] AF0 AF1 AF2 AF3 ALT4 GPIO[114] E1UC[4] SCK_1 — TX_EN SIUL eMIOS_1 DSPI_1 — FEC I/O I/O I/O — O M/S Tristate 119 143 D16 PCR[115] AF0 AF1 AF2 AF3 ALT4 GPIO[115] E1UC[5] CS0_1 — TX_ER SIUL eMIOS_1 DSPI_1 — FEC I/O I/O I/O — O M/S Tristate 120 144 F14 PCR[116] AF0 AF1 AF2 AF3 GPIO[116] E1UC[6] SOUT_7 — SIUL eMIOS_1 DSPI_7 — I/O I/O O — M/S Tristate 162 186 D7 PCR[117] AF0 AF1 AF2 AF3 — GPIO[117] E1UC[7] — — SIN_7 SIUL eMIOS_1 — — DSPI_7 I/O I/O — — I S Tristate 163 187 B7 PCR[118] AF0 AF1 AF2 AF3 GPIO[118] E1UC[8] SCK_7 MA[2] SIUL eMIOS_1 DSPI_7 ADC_0 I/O I/O I/O O M/S Tristate 164 188 C7 PCR[119] AF0 AF1 AF2 AF3 ALT4 GPIO[119] E1UC[9] CS3_2 MA[1] CS0_7 SIUL eMIOS_1 DSPI_2 ADC_0 DSPI_7 I/O I/O O O I/O M/S Tristate 165 189 C6 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Alternate function(1) Function Peripheral I/O direction(2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 Pin number PCR[120] AF0 AF1 AF2 AF3 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL eMIOS_1 DSPI_2 ADC_0 I/O I/O O O M/S Tristate 166 190 A6 PCR[121] AF0 AF1 AF2 AF3 — GPIO[121] — — — TCK SIUL — — — JTAGC I/O — — — I S Input, weak pull-up 155 179 A11 PH[10](6) PCR[122] AF0 AF1 AF2 AF3 — GPIO[122] — — — TMS SIUL — — — JTAGC I/O — — — I M/S Input, weak pull-up 148 172 D10 PCR[123] AF0 AF1 AF2 AF3 GPIO[123] SOUT_3 CS0_4 E1UC[5] SIUL DSPI_3 DSPI_4 eMIOS_1 I/O O I/O I/O M/S Tristate 140 164 A13 PCR[124] AF0 AF1 AF2 AF3 GPIO[124] SCK_3 CS1_4 E1UC[25] SIUL DSPI_3 DSPI_4 eMIOS_1 I/O I/O O I/O M/S Tristate 141 165 B12 PCR[125] AF0 AF1 AF2 AF3 GPIO[125] SOUT_4 CS0_3 E1UC[26] SIUL DSPI_4 DSPI_3 eMIOS_1 I/O O I/O I/O M/S Tristate 9 9 B1 PCR[126] AF0 AF1 AF2 AF3 GPIO[126] SCK_4 CS1_3 E1UC[27] SIUL DSPI_4 DSPI_3 eMIOS_1 I/O I/O O I/O M/S Tristate 10 10 C1 PCR[127] AF0 AF1 AF2 AF3 GPIO[127] SOUT_5 — E1UC[17] SIUL DSPI_5 — eMIOS_1 I/O O — I/O M/S Tristate 8 8 E3 Port pin PH[8] PH[9](6) PH[11] PH[12] PH[13] PH[14] PH[15] PCR DocID17478 Rev 9 39/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) PI[6] 40/123 LBGA256 PI[5] LQFP 208 PI[4] LQFP 176 PI[3] RESET config. PI[2] Pad type PI[1] I/O direction(2) PI[0] Function Peripheral Port pin Alternate function(1) Pin number PCR[128] AF0 AF1 AF2 AF3 GPIO[128] E0UC[28] LIN8TX — SIUL eMIOS_0 LINFlexD_8 — I/O I/O O — S Tristate 172 196 C5 PCR[129] AF0 AF1 AF2 AF3 — — GPIO[129] E0UC[29] — — WKPU[24] LIN8RX SIUL eMIOS_0 — — WKPU LINFlexD_8 I/O I/O — — I I S Tristate 171 195 A4 PCR[130] AF0 AF1 AF2 AF3 GPIO[130] E0UC[30] LIN9TX — SIUL eMIOS_0 LINFlexD_9 — I/O I/O O — S Tristate 170 194 D6 PCR[131] AF0 AF1 AF2 AF3 — — GPIO[131] E0UC[31] — — WKPU[23] LIN9RX SIUL eMIOS_0 — — WKPU LINFlexD_9 I/O I/O — — I I S Tristate 169 193 B5 PCR[132] AF0 AF1 AF2 AF3 GPIO[132] E1UC[28] SOUT_4 — SIUL eMIOS_1 DSPI_4 — I/O I/O O — M/S Tristate 143 167 A12 PCR[133] AF0 AF1 AF2 AF3 ALT4 GPIO[133] E1UC[29] SCK_4 CS2_5 CS2_6 SIUL eMIOS_1 DSPI_4 DSPI_5 DSPI_6 I/O I/O I/O O O M/S Tristate 142 166 D12 PCR[134] AF0 AF1 AF2 AF3 ALT4 GPIO[134] E1UC[30] CS0_4 CS0_5 CS0_6 SIUL eMIOS_1 DSPI_4 DSPI_5 DSPI_6 I/O I/O I/O I/O I/O S Tristate 11 11 D2 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) LBGA256 PI[12] LQFP 208 PI[11] LQFP 176 PI[10] RESET config. PI[9] Pad type PI[8] I/O direction(2) PI[7] Function Peripheral Port pin Alternate function(1) Pin number PCR[135] AF0 AF1 AF2 AF3 ALT4 GPIO[135] E1UC[31] CS1_4 CS1_5 CS1_6 SIUL eMIOS_1 DSPI_4 DSPI_5 DSPI_6 I/O I/O O O O S Tristate 12 12 E2 PCR[136] AF0 AF1 AF2 AF3 — GPIO[136] — — — ADC0_S[16] SIUL — — — ADC_0 I/O — — — I S Tristate 108 130 J14 PCR[137] AF0 AF1 AF2 AF3 — GPIO[137] — — — ADC0_S[17] SIUL — — — ADC_0 I/O — — — I S Tristate — 131 J15 PCR[138] AF0 AF1 AF2 AF3 — GPIO[138] — — — ADC0_S[18] SIUL — — — ADC_0 I/O — — — I S Tristate — 134 J16 PCR[139] AF0 AF1 AF2 AF3 — — GPIO[139] — — — ADC0_S[19] SIN_3 SIUL — — — ADC_0 DSPI_3 I/O — — — I I S Tristate 111 135 H16 PCR[140] AF0 AF1 AF2 AF3 — GPIO[140] CS0_3 CS0_2 — ADC0_S[20] SIUL DSPI_3 DSPI_2 — ADC_0 I/O I/O I/O — I S Tristate 112 136 G15 PCR DocID17478 Rev 9 41/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 42/123 LBGA256 PJ[2] LQFP 208 PJ[1] LQFP 176 PJ[0] RESET config. PI[15] Pad type PI[14] I/O direction(2) PI[13] Function Peripheral Port pin Alternate function(1) Pin number PCR[141] AF0 AF1 AF2 AF3 — GPIO[141] CS1_3 CS1_2 — ADC0_S[21] SIUL DSPI_3 DSPI_2 — ADC_0 I/O O O — I S Tristate 113 137 G14 PCR[142] AF0 AF1 AF2 AF3 — — GPIO[142] — — — ADC0_S[22] SIN_4 SIUL — — — ADC_0 DSPI_4 I/O — — — I I S Tristate 76 92 T12 PCR[143] AF0 AF1 AF2 AF3 — GPIO[143] CS0_4 CS2_2 — ADC0_S[23] SIUL DSPI_4 DSPI_2 — ADC_0 I/O I/O O — I S Tristate 75 91 P11 PCR[144] AF0 AF1 AF2 AF3 — GPIO[144] CS1_4 CS3_2 — ADC0_S[24] SIUL DSPI_4 DSPI_2 — ADC_0 I/O O O — I S Tristate 74 90 R11 PCR[145] AF0 AF1 AF2 AF3 — — GPIO[145] — — — ADC0_S[25] SIN_5 SIUL — — —— ADC_0 DSPI_5 I/O — — — I I S Tristate 73 89 N10 PCR[146] AF0 AF1 AF2 AF3 — GPIO[146] CS0_5 CS0_6 CS0_7 ADC0_S[26] SIUL DSPI_5 DSPI_6 DSPI_7 ADC_0 I/O I/O I/O I/O I S Tristate 72 88 R10 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) PJ[9] LBGA256 PJ[8] LQFP 208 PJ[7] LQFP 176 PJ[6] RESET config. PJ[5] Pad type PJ[4] I/O direction(2) PJ[3] Function Peripheral Port pin Alternate function(1) Pin number PCR[147] AF0 AF1 AF2 AF3 — GPIO[147] CS1_5 CS1_6 CS1_7 ADC0_S[27] SIUL DSPI_5 DSPI_6 DSPI_7 ADC_0 I/O O O O I S Tristate 71 87 P10 PCR[148] AF0 AF1 AF2 AF3 GPIO[148] SCK_5 E1UC[18] — SIUL DSPI_5 eMIOS_1 — I/O I/O I/O — M/S Tristate 5 5 D3 PCR[149] AF0 AF1 AF2 AF3 — GPIO[149] — — — ADC0_S[28] SIUL — — — ADC_0 I/O — — — I S Tristate — 113 N12 PCR[150] AF0 AF1 AF2 AF3 — GPIO[150] — — — ADC0_S[29] SIUL — — — ADC_0 I/O — — — I S Tristate — 112 N15 PCR[151] AF0 AF1 AF2 AF3 — GPIO[151] — — — ADC0_S[30] SIUL — — — ADC_0 I/O — — — I S Tristate — 111 P16 PCR[152] AF0 AF1 AF2 AF3 — GPIO[152] — — — ADC0_S[31] SIUL — — — ADC_0 I/O — — — I S Tristate — 110 P15 PCR[153] AF0 AF1 AF2 AF3 — GPIO[153] — — — ADC1_S[8] SIUL — — — ADC_1 I/O — — — I S Tristate — 68 P5 PCR DocID17478 Rev 9 43/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) 44/123 LBGA256 PJ[15] LQFP 208 PJ[14] LQFP 176 PJ[13] RESET config. PJ[12] Pad type PJ[11] I/O direction(2) PJ[10] Function Peripheral Port pin Alternate function(1) Pin number PCR[154] AF0 AF1 AF2 AF3 — GPIO[154] — — — ADC1_S[9] SIUL — — — ADC_1 I/O — — — I S Tristate — 67 T5 PCR[155] AF0 AF1 AF2 AF3 — GPIO[155] — — — ADC1_S[10] SIUL — — — ADC_1 I/O — — — I S Tristate — 60 R3 PCR[156] AF0 AF1 AF2 AF3 — GPIO[156] — — — ADC1_S[11] SIUL — — — ADC_1 I/O — — — I S Tristate — 59 T1 PCR[157] AF0 AF1 AF2 AF3 — — — — GPIO[157] — CS1_7 — CAN4RX ADC1_S[12] CAN1RX WKPU[31] SIUL — DSPI_7 — FlexCAN_4 ADC_1 FlexCAN_1 WKPU I/O — O — I I I I S Tristate — 65 N5 PCR[158] AF0 AF1 AF2 AF3 GPIO[158] CAN1TX CAN4TX CS2_7 SIUL FlexCAN_1 FlexCAN_4 DSPI_7 I/O O O O M/S Tristate — 64 T4 PCR[159] AF0 AF1 AF2 AF3 — GPIO[159] — CS1_6 — CAN1RX SIUL — DSPI_6 — FlexCAN_1 I/O — O — I M/S Tristate — 63 R4 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) PK[6] LBGA256 PK[5] LQFP 208 PK[4] LQFP 176 PK[3] RESET config. PK[2] Pad type PK[1] I/O direction(2) PK[0] Function Peripheral Port pin Alternate function(1) Pin number PCR[160] AF0 AF1 AF2 AF3 GPIO[160] CAN1TX CS2_6 — SIUL FlexCAN_1 DSPI_6 — I/O O O — M/S Tristate — 62 T3 PCR[161] AF0 AF1 AF2 AF3 — GPIO[161] CS3_6 — — CAN4RX SIUL DSPI_6 — — FlexCAN_4 I/O O — — I M/S Tristate — 41 H4 PCR[162] AF0 AF1 AF2 AF3 GPIO[162] CAN4TX — — SIUL FlexCAN_4 — — I/O O — — M/S Tristate — 42 L4 PCR[163] AF0 AF1 AF2 AF3 — — GPIO[163] E1UC[0] — — CAN5RX LIN8RX SIUL eMIOS_1 — — FlexCAN_5 LINFlexD_8 I/O I/O — — I I M/S Tristate — 43 N1 PCR[164] AF0 AF1 AF2 AF3 GPIO[164] LIN8TX CAN5TX E1UC[1] SIUL LINFlexD_8 FlexCAN_5 eMIOS_1 I/O O O I/O M/S Tristate — 44 M3 PCR[165] AF0 AF1 AF2 AF3 — — GPIO[165] — — — CAN2RX LIN2RX SIUL — — — FlexCAN_2 LINFlexD_2 I/O — — — I I M/S Tristate — 45 M5 PCR[166] AF0 AF1 AF2 AF3 GPIO[166] CAN2TX LIN2TX — SIUL FlexCAN_2 LINFlexD_2 — I/O O O — M/S Tristate — 46 M6 PCR DocID17478 Rev 9 45/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) PK[13] 46/123 LBGA256 PK[12] LQFP 208 PK[11] LQFP 176 PK[10] RESET config. PK[9] Pad type PK[8] I/O direction(2) PK[7] Function Peripheral Port pin Alternate function(1) Pin number PCR[167] AF0 AF1 AF2 AF3 — — GPIO[167] — — — CAN3RX LIN3RX SIUL — — — FlexCAN_3 LINFlexD_3 I/O — — — I I M/S Tristate — 47 M7 PCR[168] AF0 AF1 AF2 AF3 GPIO[168] CAN3TX LIN3TX — SIUL FlexCAN_3 LINFlexD_3 — I/O O O — M/S Tristate — 48 M8 PCR[169] AF0 AF1 AF2 AF3 — GPIO[169] — — — SIN_4 SIUL — — — DSPI_4 I/O — — — I M/S Tristate — 197 E8 PCR[170] AF0 AF1 AF2 AF3 GPIO[170] SOUT_4 — — SIUL DSPI_4 — — I/O O — — M/S Tristate — 198 E7 PCR[171] AF0 AF1 AF2 AF3 GPIO[171] SCK_4 — — SIUL DSPI_4 — — I/O I/O — — M/S Tristate — 199 F8 PCR[172] AF0 AF1 AF2 AF3 GPIO[172] CS0_4 — — SIUL DSPI_4 — — I/O I/O — — M/S Tristate — 200 G12 PCR[173] AF0 AF1 AF2 AF3 — GPIO[173] CS3_6 CS2_7 SCK_1 CAN3RX SIUL DSPI_6 DSPI_7 DSPI_1 FlexCAN_3 I/O O O I/O I M/S Tristate — 201 H12 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) PL[4] PL[5] LBGA256 PL[3] LQFP 208 PL[2] LQFP 176 PL[1] RESET config. PL[0] Pad type PK[15] I/O direction(2) PK[14] Function Peripheral Port pin Alternate function(1) Pin number PCR[174] AF0 AF1 AF2 AF3 GPIO[174] CAN3TX CS3_7 CS0_1 SIUL FlexCAN_3 DSPI_7 DSPI_1 I/O O O I/O M/S Tristate — 202 J12 PCR[175] AF0 AF1 AF2 AF3 — — GPIO[175] — — — SIN_1 SIN_7 SIUL — — — DSPI_1 DSPI_7 I/O — — — I I M/S Tristate — 203 D5 PCR[176] AF0 AF1 AF2 AF3 GPIO[176] SOUT_1 SOUT_7 — SIUL DSPI_1 DSPI_7 — I/O O O — M/S Tristate — 204 C4 PCR[177] AF0 AF1 AF2 AF3 GPIO[177] — — — SIUL — — — I/O — — — M/S Tristate — — F7 (7) AF0 AF1 AF2 AF3 GPIO[178] — MDO0(8) — SIUL — Nexus — I/O — O — M/S Tristate — — F5 PCR[179] AF0 AF1 AF2 AF3 GPIO[179] — MDO1 — SIUL — Nexus — I/O — O — M/S Tristate — — G5 PCR[180] AF0 AF1 AF2 AF3 GPIO[180] — MDO2 — SIUL — Nexus — I/O — O — M/S Tristate — — H5 PCR[181] AF0 AF1 AF2 AF3 GPIO[181] — MDO3 — SIUL — Nexus — I/O — O — M/S Tristate — — J5 PCR PCR[178] DocID17478 Rev 9 47/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) PL[12] PL[13] 48/123 LBGA256 PL[11] LQFP 208 PL[10] LQFP 176 PL[9] RESET config. PL[8] Pad type PL[7] I/O direction(2) PL[6] Function Peripheral Port pin Alternate function(1) Pin number PCR[182] AF0 AF1 AF2 AF3 GPIO[182] — MDO4 — SIUL — Nexus — I/O — O — M/S Tristate — — K5 PCR[183] AF0 AF1 AF2 AF3 GPIO[183] — MDO5 — SIUL — Nexus — I/O — O — M/S Tristate — — L5 PCR[184] AF0 AF1 AF2 AF3 — GPIO[184] — — — EVTI SIUL — — — Nexus I/O — — — I S Pull-up — — M9 PCR[185] AF0 AF1 AF2 AF3 GPIO[185] — MSEO — SIUL — Nexus — I/O — O — M/S Tristate — — M10 PCR[186] AF0 AF1 AF2 AF3 GPIO[186] — MCKO — SIUL — Nexus — I/O — O — F/S Tristate — — M11 PCR[187] AF0 AF1 AF2 AF3 GPIO[187] — — — SIUL — — — I/O — — — M/S Tristate — — M12 PCR[188] AF0 AF1 AF2 AF3 GPIO[188] — EVTO — SIUL — Nexus — I/O — O — M/S Tristate — — F11 PCR[189] AF0 AF1 AF2 AF3 GPIO[189] — MDO6 — SIUL — Nexus — I/O — O — M/S Tristate — — F10 PCR DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) PM[4] LBGA256 PM[3] LQFP 208 PM[2] LQFP 176 PM[1] RESET config. PM[0] Pad type PL[15] I/O direction(2) PL[14] Function Peripheral Port pin Alternate function(1) Pin number PCR[190] AF0 AF1 AF2 AF3 GPIO[190] — MDO7 — SIUL — Nexus — I/O — O — M/S Tristate — — E12 PCR[191] AF0 AF1 AF2 AF3 GPIO[191] — MDO8 — SIUL — Nexus — I/O — O — M/S Tristate — — E11 PCR[192] AF0 AF1 AF2 AF3 GPIO[192] — MDO9 — SIUL — Nexus — I/O — O — M/S Tristate — — E10 PCR[193] AF0 AF1 AF2 AF3 GPIO[193] — MDO10 — SIUL — Nexus — I/O — O — M/S Tristate — — E9 PCR[194] AF0 AF1 AF2 AF3 GPIO[194] — MDO11 — SIUL — Nexus — I/O — O — M/S Tristate — — F12 PCR[195] AF0 AF1 AF2 AF3 GPIO[195] — — — SIUL — — — I/O — — — M/S Tristate — — K12 PCR[196] AF0 AF1 AF2 AF3 GPIO[196] — — — SIUL — — — I/O — — — M/S Tristate — — L12 PCR DocID17478 Rev 9 49/123 122 Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx Table 5. Functional port pin descriptions (continued) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PM[6] I/O direction(2) PM[5] Function Peripheral Port pin Alternate function(1) Pin number PCR[197] AF0 AF1 AF2 AF3 GPIO[197] — — — SIUL — — — I/O — — — M/S Tristate — — F9 PCR[198] AF0 AF1 AF2 AF3 GPIO[198] — — — SIUL — — — I/O — — — M/S Tristate — — F6 PCR 1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 000  AF0; PCR.PA = 001 AF1; PCR.PA = 010 AF2; PCR.PA = 011  AF3; PCR.PA = 100  ALT4. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. 2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 3. NMI[0] and NMI[1] have a higher priority than alternate functions. When NMI is selected, the PCR.PA field is ignored. 4. SXOSC’s OSC32k_XTAL and OSC32k_EXTAL pins are shared with GPIO functionality. When used as crystal pins, other functionality of the pin cannot be used and it should be ensured that application never programs OBE and PUE bit of the corresponding PCR to "1". 5. If you want to use OSC32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature as PB[10] can induce coupling on PB[9] and disturb oscillator frequency. 6. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed. 7. When MBIST is enabled to run (STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0]) to 0 V before the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBIST operation. When MBIST is not enabled (STCU Enable = 0), there are no restriction as the device does not internally drive the pad. 8. These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development Interface "Port Control Register" rather than the SIUL. Specifically, the debugger can enable the MDO[7:0], MSEO, and MCKO ports by programming NDI (PCR[MCKO_EN] or PCR[PSTAT_EN]). MDO[8:11] ports can be enabled by programming NDI ((PCR[MCKO_EN] and PCR[FPM]) or PCR[PSTAT_EN]). 50/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx 3 Electrical Characteristics Electrical Characteristics This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS_HV). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. 3.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 6 are used and the parameters are tagged accordingly in the tables where appropriate. Table 6. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. Note: The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.2 NVUSRO register Portions of the device configuration, such as high voltage supply is controlled via bit values in the Non-Volatile User Options Register (NVUSRO). For a detailed description of the NVUSRO register, see SPC564Bxx and SPC56ECxx Reference Manual. DocID17478 Rev 9 51/123 122 Electrical Characteristics 3.2.1 SPC564Bxx-SPC56ECxx NVUSRO [PAD3V5V(0)] field description Table 7 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for VDD_HV_A domain. Table 7. PAD3V5V(0) field description (1) Value Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value. 3.2.2 NVUSRO [PAD3V5V(1)] field description Table 8 shows how NVUSRO [PAD3V5V(1)] controls the device configuration the device configuration for VDD_HV_B domain. Table 8. PAD3V5V(1) field description Value(1) Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value. 3.3 Absolute maximum ratings Table 9. Absolute maximum ratings Value Symbol Parameter Conditions Unit Min Max S Digital ground on VSS_HV R pins — 0 0 V VDD_HV_A Voltage on VDD_HV_A pins S with respect to ground R (VSS_HV) — –0.3 6.0 V VDD_HV_B(1) Voltage on VDD_HV_B pins S with respect to common R ground (VSS_HV) — –0.3 6.0 V Voltage on VSS_LV (low S voltage digital supply) pins R with respect to ground (VSS_HV) — VSS_HV 0.1 VSS_HV 0.1 V VSS_HV VSS_LV 52/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Table 9. Absolute maximum ratings (continued) Value Symbol Parameter Conditions Base control voltage for external BCP68 NPN device VRC_CTRL(2) VSS_ADC Voltage on VSS_HV_ADC0, S VSS_HV_ADC1 (ADC R reference) pin with respect to ground (VSS_HV) VDD_HV_ADC0 Voltage on VDD_HV_ADC0 S with respect to ground R (VSS_HV) (4) Voltage on VDD_HV_ADC1 S with respect to ground R (VSS_HV) VIN Voltage on any GPIO pin S with respect to ground R (VSS_HV) VDD_HV_ADC1 Unit Min Max Relative to VDD_LV 0 VDD_LV + 1 V — VSS_HV 0.1 VSS_HV + 0.1 V — –0.3 6.0 VDD_HV_A 0.3 VDD_HV_A+0.3 –0.3 6.0 Relative to VDD_HV_A(3) — V V Relative to VDD_HV_A2 VDD_HV_A0.3 Relative to VDD_HV_A/HV_B VDD_HV_A/HV_B VDD_HV_A/HV_B+ 0.3 0.3 VDD_HV_A+0.3 IINJPAD S Injected input current on any R pin during overload condition — –10 10 IINJSUM Absolute sum of all injected S input currents during R overload condition — –50 50 IAVGSEG (5) TSTORAGE Sum of all the static I/O S current within a supply R segment (VDD_HV_A or VDD_HV_B) V mA VDD = 5.0 V ± 10%, PAD3V5V = 0 70 VDD = 3.3 V ± 10%, PAD3V5V = 1 64 mA S Storage temperature R — –55(6) 150 °C 1. VDD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design is robust against any supply order. 2. This voltage is internally generated by the device and no external voltage should be supplied. 3. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V. 4. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within ±300 mV of VDD_HV_B when these channels are used for ADC_1. 5. Any temperature beyond 125 °C should limit the current to 50 mA (max). 6. This is the storage temperature for the flash memory. Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD_HV_A/HV_B or VIN < VSS_HV), the voltage on pins with respect to ground (VSS_HV) must not exceed the recommended values. DocID17478 Rev 9 53/123 122 Electrical Characteristics 3.4 SPC564Bxx-SPC56ECxx Recommended operating conditions Table 10. Recommended operating conditions (3.3 V) Value Symbol VSS_HV Parameter SR Digital ground on VSS_HV pins Conditions Unit Min Max — 0 0 V VDD_HV_A(1) Voltage on VDD_HV_A pins SR with respect to ground (VSS_HV) — 3.0 3.6 V VDD_HV_B(1) Voltage on VDD_HV_B pins SR with respect to ground (VSS_HV) — 3.0 3.6 V VSS_LV(2) Voltage on VSS_LV (low voltage digital supply) SR pins with respect to ground (VSS_HV) — VSS_HV 0.1 VSS_HV + 0.1 V Relative to VDD_LV 0 VDD_LV + 1 V — VSS_HV 0.1 VSS_HV + 0.1 V — 3.0(5) 3.6 Base control voltage for external BCP68 NPN device VRC_CTRL(3) VSS_ADC Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC SR reference) pin with respect to ground (VSS_HV) Voltage on VDD_HV_ADC0 VDD_HV_ADC0 with SR (4) respect to ground (VSS_HV) VDD_HV_ADC1 (7) Voltage on VDD_HV_ADC1 with SR respect to ground (VSS_HV) VIN Voltage on any GPIO pin SR with respect to ground (VSS_HV) IINJPAD Injected input current on SR any pin during overload condition IINJSUM Absolute sum of all SR injected input currents during overload condition Relative to VDD_HV_A(6) — Relative to VDD_HV_A(6) VDD_HV_A 0.1 VDD_HV_A + 0.1 3.0 V 3.6 VDD_HV_A 0.1 VDD_HV_A + 0.1 — VSS_HV 0.1 — Relative to VDD_HV_A/HV_B — VDD_HV_A/HV_B + 0.1 — 5 5 V V mA TVDD 54/123 SR VDD_HV_A slope to ensure correct power up(8) — 50 50 — — 0.5 V/µs — 0.5 — V/min DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Table 10. Recommended operating conditions (3.3 V) (continued) Value Symbol Parameter Ambient temperature under bias TA SR TJ Junction temperature SR under bias Conditions fCPU up to 120 MHz  2% Unit Min Max –40 125 °C 40 — 150 1. 100 nF EMI capacitance need to be provided between each VDD/VSS_HV pair. 2. 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance needs to be provided as CREG on each VDD_LV pin. For details refer to the Power Management chapter of the MPC5646C Reference Manual. 3. This voltage is internally generated by the device and no external voltage should be supplied. 4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. 6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V. 7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1. 8. Guaranteed by the device validation. Table 11. Recommended operating conditions (5.0 V) Value Symbol Parameter Conditions Max — 0 0 — 4.5 5.5 Voltage drop(2) 3.0 5.5 — 3.0 5.5 V Ethernet/3.3 V functionality S (See the notes in all figures in R Section 2: Package pinouts and signal descriptions for the list of channels operating in VDD_HV_B domain) — 3.0 3.6 V Voltage on VSS_LV (Low voltage S digital supply) pins with respect to R ground (VSS_HV) — VSS_HV – 0.1 VSS_HV + 0.1 V Relative to VDD_LV 0 VDD_LV + 1 V — VSS_HV – 0.1 VSS_HV + 0.1 V VSS_HV S Digital ground on VSS_HV pins R VDD_HV_A(1) S Voltage on VDD_HV_A pins with R respect to ground (VSS_HV) Generic GPIO functionality VDD_HV_B VSS_LV(3) VRC_CTRL(4) VSS_ADC Unit Min Base control voltage for external BCP68 NPN device Voltage on VSS_HV_ADC0, S VSS_HV_ADC1 (ADC reference) R pin with respect to ground (VSS_HV) DocID17478 Rev 9 V V 55/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Table 11. Recommended operating conditions (5.0 V) (continued) Value Symbol Parameter Conditions Unit Min Max 4.5 5.5 3.0 5.5 Relative to VDD_HV_A(6) VDD_HV_A – 0.1 VDD_HV_A + 0.1 — 4.5 5.5 3.0 5.5 VDD_HV_A 0.1 VDD_HV_A + 0.1 — VSS_HV –0.1 — Relative to VDD_HV_A/HV_B — VDD_HV_A/HV_B + 0.1 — –5 5 — VDD_HV_ADC0 (5) VDD_HV_ADC1 (7) VIN S Voltage on VDD_HV_ADC0 with R respect to ground (VSS_HV) S Voltage on VDD_HV_ADC1 with R respect to ground (VSS_HV) S Voltage on any GPIO pin with R respect to ground (VSS_HV) IINJPAD S Injected input current on any pin R during overload condition IINJSUM Absolute sum of all injected input S currents during overload R condition TVDD S VDD_HV_A slope to ensure correct R power up(8) TA C-Grade Part (2) Voltage drop Voltage drop(2) Relative to VDD_HV_A(6) V V V mA — –50 50 — — 0.5 V/µs — 0.5 — V/min S Ambient temperature under bias R — 40 85 TJ C-Grade Part S Junction temperature under bias R — 40 110 TA V-Grade Part S Ambient temperature under bias R — 40 105 TJ V-Grade Part S Junction temperature under bias R — 40 130 TA M-Grade Part S Ambient temperature under bias R — 40 125 TJ M-Grade Part S Junction temperature under bias R — 40 150 °C 1. 100 nF EMI capacitance need to be provided between each VDD/VSS_HV pair. 2. Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC functionality is guaranteed from the entire range 3.0V–5.5 V, the parametrics measured are at 3.0V and 5.5V (extreme voltage ranges to cover the range of operation). The parametrics might have some variation in the intermediate voltage range, but there is no impact to functionality. 3. 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance needs to be provided as CREG on each VDD_LV pin. 4. This voltage is internally generated by the device and no external voltage should be supplied. 5. 100 nF capacitance needs to be provided between VDD_HV_(ADC0/ADC1)/VSS_HV_(ADC0/ADC1) pair. 6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V. 7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1. 56/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics 8. Guaranteed by device validation. Note: SRAM retention guaranteed to LVD levels. 3.5 Thermal characteristics 3.5.1 Package thermal characteristics Table 12. LQFP thermal characteristics(1) Symbol C RJA CC RJA CC D D Parameter Pin count (2) Conditions Thermal resistance, junction-to-ambient natural convection Single-layer board—1s Thermal resistance, junction-to-ambient natural convection Four-layer board—2s2p(5) Value(3) Unit Min Typ Max 176 — — 44.4(4) °C/W 208 — — 43 °C/W 176 — — 36.1 °C/W 208 — — 33.9 °C/W 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C. 3. All values need to be confirmed during device validation. 4. 1s board as per standard JEDEC (JESD51-7) in natural convection. 5. 2s2p board as per standard JEDEC (JESD51-7) in natural convection. Table 13. LBGA256 thermal characteristics(1) Symbol RJA CC C — Parameter Conditions Thermal resistance, junction-to-ambient natural convection Value Single-layer board—1s 44.3 Four-layer board—2s2p 31 Unit °C/W 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. DocID17478 Rev 9 57/123 122 Electrical Characteristics 3.5.2 SPC564Bxx-SPC56ECxx Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: Equation 1 TJ = TA + (PD  RJA) Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: Equation 2 PD = K / (TJ + 273 °C) Therefore, solving equations Equation 1 and Equation 2: Equation 3 K = PD  (TA + 273 °C) + RJA  PD2 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations Equation 1 and Equation 2 iteratively for any value of TA. 3.6 I/O pad electrical characteristics 3.6.1 I/O pad types The device provides four main I/O pad types depending on the associated alternate functions:  Slow pads—These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission.  Medium pads—These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission.  Fast pads—These pads provide maximum speed. These are used for improved Nexus debugging capability.  Input only pads—These pads are associated to ADC channels and 32 kHz low power external crystal oscillator providing low input leakage.  Low power pads—These pads are active in standby mode for wakeup source. Also, medium/slow and fast/medium pads are available in design which can be configured to behave like a slow/medium and medium/fast pads depending upon the slew-rate control. 58/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 3.6.2 I/O input DC characteristics Table 14 provides input DC electrical characteristics as described in Figure 5. Figure 5. I/O input DC electrical characteristics definition VIN VDD VIH VHYS VIL PDIx = ‘1 (GPDI register of SIUL) PDIx = ‘0’ Table 14. I/O input DC electrical characteristics Symbol C Value(2) Conditions(1) Parameter Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) — 0.65 VDD — VDD + 0.4 VIL SR P Input low level CMOS (Schmitt Trigger) — 0.3 — 0.35VDD Input hysteresis CMOS (Schmitt Trigger) — 0.1VDD — — VHYS CC C ILKG WFI P TA = 40 °C — 2 — P — 2 — D No injection T = 25 °C A on adjacent T A = 105 °C pin — 12 500 P TA = 125 °C — 70 1000 CC Digital input leakage SR P WNFI SR P V nA Width of input pulse rejected by analog filter(3) — — — 40(4) ns Width of input pulse accepted by analog filter(3) — 1000(4) — — ns 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation. 3. Analog filters are available on all wakeup lines. DocID17478 Rev 9 59/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx 4. The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending on silicon sample to sample variation. 3.6.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads:  Table 15 provides weak pull figures. Both pull-up and pull-down resistances are supported.  Table 16 provides output driver characteristics for I/O pads when in SLOW configuration.  Table 17 provides output driver characteristics for I/O pads when in MEDIUM configuration.  Table 18 provides output driver characteristics for I/O pads when in FAST configuration. Table 15. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter P |IWPU| CC C P P |IWPD| CC C P Weak pull-up current absolute value Value Conditions(1),(2) Unit Min Typ Max 10 — 150 10 — 250 10 — 150 10 — 150 10 — 250 10 — 150 VIN = VIL, VDD = PAD3V5V = 0 5.0 V ± 10% PAD3V5V = 1(3) VIN = VIL, VDD = PAD3V5V = 1 3.3 V ± 10% VIN = VIH, VDD = PAD3V5V = 0 Weak pull-down 5.0 V ± 10% PAD3V5V = 1 current absolute value VIN = VIH, VDD = PAD3V5V = 1 3.3 V ± 10% µA µA 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 16. SLOW configuration output buffer electrical characteristics Symbol VOH CC C Value Conditions(1),(2) Unit Min Typ Max P IOH = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — Output high level Push C SLOW Pull configuration IOH = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(3) 0.8VDD — — VDD 0.8 — — P 60/123 Parameter IOH = 1.5 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 DocID17478 Rev 9 V SPC564Bxx-SPC56ECxx Electrical Characteristics Table 16. SLOW configuration output buffer electrical characteristics (continued) Symbol C P VOL CC Output low level C SLOW configuration Value Conditions(1),(2) Parameter Push Pull P Unit Min Typ Max IOL = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD IOL = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(3) — — 0.1VDD IOL = 1.5 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5 V 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 17. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter VOL CC CC C Output high level MEDIUM configuration Unit Min Typ Max IOH = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — IOH = 1.5 mA, Push Pull VDD = 5.0 V ± 10%, PAD3V5V = 1(3) 0.8VDD — — C VOH Value Conditions(1),(2) C IOH = 2 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD 0.8 — — C IOL = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.2VDD IOL = 1.5 mA, Push Pull VDD = 5.0 V ± 10%, PAD3V5V = 1(3) — — 0.1VDD IOL = 2 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5 C Output low level MEDIUM configuration C V V 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. DocID17478 Rev 9 61/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Table 18. FAST configuration output buffer electrical characteristics Symbol C Parameter CC VOH CC VOL C Unit Min Typ Max IOH = 14 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — IOH = 7 mA, Push Pull VDD = 5.0 V ± 10%, PAD3V5V = 1(3) 0.8VDD — — P Output high level FAST configuration Value Conditions(1),(2) C IOH = 11 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD 0.8 — — P IOL = 14 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD C Output low level IOL = 7 mA, FAST Push Pull VDD = 5.0 V ± 10%, configuration PAD3V5V = 1(3) — — 0.1VDD C IOL = 11 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5 V V 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus outputs (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 3.6.4 Output pin transition times Table 19. Output pin transition times Symbol C Parameter T CC D D CC — — 50 — — 100 CL = 100 pF — — 125 CL = 25 pF — — 40 — — 50 — — 75 — — 10 — — 20 — — 40 — — 12 — — 25 — — 40 CL = 50 pF D CL = 100 pF D CL = 25 pF D D T D 62/123 Max T T Ttr Typ CL = 50 pF Output transition time output pin(4) SLOW configuration Output transition time output pin(4) MEDIUM configuration Unit Min CL = 25 pF D Ttr Conditions Value(3) (1),(2) CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF VDD = 5.0 V ± 10 %, PAD3V5V = 0 VDD = 3.3 V ± 10 %, PAD3V5V = 1 VDD = 5.0 V ± 10 %, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V ± 10 %, PAD3V5V = 1 SIUL.PCRx.SRC = 1 DocID17478 Rev 9 ns ns SPC564Bxx-SPC56ECxx Electrical Characteristics Table 19. Output pin transition times (continued) Symbol C Parameter Conditions Value(3) (1),(2) Unit Min Typ Max — — 4 — — 6 CL = 100 pF — — 12 CL = 25 pF — — 4 — — 7 — — 12 CL = 25 pF CL = 50 pF Ttr CC D Output transition time output pin(4) FAST configuration CL = 50 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF ns 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3. All values need to be confirmed during device validation. 4. CL includes device and package capacitances (CPKG < 5 pF). 3.6.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply is associated to a VDD/VSS_HV supply pair as described in Table 20. Table 21 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 20. I/O supplies Package I/O Supplies LBGA256(1) Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11 LQFP208 pin6 pin27 (VDD_HV_A) (VDD_HV_A)pi pin7 n28 (VSS_HV) (VSS_HV) pin73 (VSS_HV) pin75 (VDD_HV_A) pin101 (VDD_HV_A) pin102 (VSS_HV) pin132 (VSS_HV) pin133 (VDD_HV_A) pin147 (VSS_HV) pin148 (VDD_HV_B) LQFP176 pin6 (VDD_HV_A) pin7 (VSS_HV) pin57 (VSS_HV) pin59 (VDD_HV_A) pin85 (VDD_HV_A) pin86 (VSS_HV) pin123 (VSS_HV) pin124 (VDD_HV_B) pin150 (VSS_HV) pin151 (VDD_HV_A) pin27 (VDD_HV_A)pi n28 (VSS_HV) pin174 (VSS_HV) — pin175 (VDD_HV_A) — — 1. VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. DocID17478 Rev 9 63/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Table 21. I/O consumption Symbol ISWTSLW(4) ISWTMED (4) ISWTFST(4) C Parameter Conditions C Peak I/O current for D C FAST configuration Typ Max VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 19.9 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 15.5 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 28.8 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 16.3 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 113.5 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 52.1 — — 2.22 — — 3.13 — — 6.54 — — 1.51 — — 2.14 — — 4.33 — — 6.5 — — 13.32 CL = 100 pF, 13 MHz — — 18.26 CL = 25 pF, 13 MHz — — 4.91 — — 8.47 — — 10.94 — — 21.05 — — 33 — — 55.77 — — 14 — — 20 CL = 100 pF, 40 MHz — — 34.89 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65(4) CL = 25 pF CL = 25 pF mA mA mA CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz IRMSSLW VDD = 5.0 V ± 10%, PAD3V5V = 0 Root mean square CL = 100 pF, 2 MHz C D I/O current for C SLOW configuration CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz mA VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz CL = 25 pF, 13 MHz IRMSMED Root mean square C I/O current for D C MEDIUM configuration CL = 25 pF, 40 MHz CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 mA VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 13 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz IRMSFST VDD = 5.0 V ± 10%, PAD3V5V = 0 Root mean square CL = 100 pF, 40 MHz C D I/O current for FAST C CL = 25 pF, 40 MHz configuration CL = 25 pF, 64 MHz IAVGSEG Sum of all the static S D I/O current within a R supply segment Unit Min C Peak I/O current for D CL = 25 pF C SLOW configuration Peak I/O current for C D MEDIUM C configuration Value(3) (1),(2) mA VDD = 3.3 V ± 10%, PAD3V5V = 1 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3. All values need to be confirmed during device validation. 4. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. 64/123 DocID17478 Rev 9 mA SPC564Bxx-SPC56ECxx 3.7 Electrical Characteristics RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. Figure 6. Start-up reset requirements VDD_HV_A VDDMIN RESET VIH VIL device reset forced by RESET device start-up phase Figure 7. Noise filtering on reset signal VRESET hw_rst VDD ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST DocID17478 Rev 9 65/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Table 22. Reset electrical characteristics Symbol C Parameter Conditions Value(2) (1) Unit Min Typ Max VIH S Input High Level CMOS P R (Schmitt Trigger) — 0.65VDD — VDD + 0.4 V VIL S Input low Level CMOS P R (Schmitt Trigger) — 0.3 — 0.35VDD V VHYS C Input hysteresis CMOS C C (Schmitt Trigger) — 0.1VDD — — V Push Pull, IOL = 2 mA, VDD = 5.0 V ± 10 %, PAD3V5V = 0 (recommended) — — 0.1VDD Push Pull, IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(3) — — 0.1VDD Push Pull, IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — 0.5 CL = 25 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 10 CL = 50 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 20 CL = 100 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 40 CL = 25 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 12 CL = 50 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 25 CL = 100 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 40 VOL Ttr WFRST WNFRS T |IWPU| C P Output low level C Output transition time C D output pin(4) C MEDIUM configuration ns S Reset input filtered P R pulse — — — 40 ns S Reset input not filtered P R pulse — 1000 — — ns VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150 VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150 10 — 250 C Weak pull-up current P C absolute value VDD = 5.0 V ± 10%, PAD3V5V = 1(5) 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation. 3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section of the device Reference Manual). 4. CL includes device and package capacitance (CPKG < 5 pF). 5. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 66/123 V DocID17478 Rev 9 µA SPC564Bxx-SPC56ECxx Electrical Characteristics 3.8 Power management electrical characteristics 3.8.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage supply VDD_HV_A. The following supplies are involved:  HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD_HV_A power pin.  LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the on-chip VREG with an external ballast (BCP68 NPN device). It is further split into four main domains to ensure noise isolation between critical LV modules within the device: – LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. – LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is shorted with LV_COR through double bonding. – LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR through double bonding. – LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Figure 8. Voltage regulator capacitance connection 100 nf VDD_LV 100 nf VSS_LV VDD_LV 100 nf VSS_LV VDD_LV VSS_LV 40 f (4  10 f) PD0 (always on domain) PD0 Logic PD1 Switchable Domain (FMPLL, Flash) (CREGn) 32 KB Split 56 KB Split 8 KB Split CTRL CTRL CTRL VDD_LV HPVDD VSS_LV Off chip BCP68 NPN driver VRC_CTRL sw1 ( 2.6 V for correct functionality. The device is not monitoring this supply hence the external component must meet the 2.6 V criteria through external monitoring if required. Table 23. Voltage regulator electrical characteristics Symbol C Value(2) Conditions(1) Parameter Unit Min Typ Max CREGn S External ballast stability — R capacitance — 40 — 60 F RREG S Stability capacitor equivalent — R serial resistance — — — 0.2 W VDD_HV_A/HV_B/VSS_HV S Decoupling capacitance (Close to pair — R the pin) VDD_LV/VSS_LV pair 100 — nF CREGP 100 — nF 10 — 40 F 1.20 1.28 1.32 V CDEC2 Stability capacitance regulator S — supply (Close to the ballast R collector) VDD_BV/VSS_HV VMREG C P Main regulator output voltage C After trimming TA = 25 °C 68/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Table 23. Voltage regulator electrical characteristics (continued) Symbol C S Main regulator current provided to — R VDD_LV domain IMREG Value(2) Conditions(1) Parameter — Unit Min Typ Max — — 350 mA C Main regulator module current D C consumption IMREG = 200 mA — — 2 IMREGINT IMREG = 0 mA — — 1 VLPREG C Low power regulator output P C voltage After trimming TA = 25 °C 1.17 1.27 1.32 V ILPREG S Low power regulator current — R provided to VDD_LV domain — — 50 mA ILPREG = 15 mA; TA = 55 °C — — 600 ILPREG = 0 mA; TA = 55 °C — 20 — Main LVDs and reference current C D consumption (low power and main TA = 55 °C C regulator switched off) — 2 — A C Main LVD current consumption D C (switch-off during standby) — 1 — A — — D C C ILPREGINT Low power regulator module current consumption — IVREGREF IVREDLVD12 — TA = 55 °C C In-rush current on VDD_BV during D C power-up IDD_HV_A — mA A 600 mA (3) 1. VDD_HV_A = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Inrush current is seen more like steps of 600 mA peak. The startup of the regulator happens in steps of 50 mV in ~25 steps to reach ~1.2 V VDD_LV. Each step peak current is within 600 mA 3.8.3 Voltage monitor electrical characteristics The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the VDD_HV_A and the VDD_LV voltage while device is supplied: Note:  POR monitors VDD_HV_A during the power-up phase to ensure device is maintained in a safe reset state  LVDHV3 monitors VDD_HV_A to ensure device is reset below minimum functional supply  LVDHV5 monitors VDD_HV_A when application uses device in the 5.0 V±10 % range  LVDLVCOR monitors power domain No. 1 (PD1)  LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply. When enabled, PD2 (RAM retention) is monitored through LVD_DIGBKP. DocID17478 Rev 9 69/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Figure 9. Low voltage monitor vs. Reset VDDHV/LV VLVDHVxH/LVxH VLVDHVxL/LVxL RESET Table 24. Low voltage monitor electrical characteristics Symbol C Parameter Value(2) Conditions(1) Unit Min Typ Max VPORUP S P Supply for functional POR module R — 1.0 — 5.5 VPORH C P Power-on reset threshold C — 1.5 — 2.6 VLVDHV3H C T LVDHV3 low voltage detector high threshold C — 2.7 — 2.85 VLVDHV3L C T LVDHV3 low voltage detector low threshold C — 2.6 — 2.74 VLVDHV5H C T LVDHV5 low voltage detector high threshold C — 4.3 — 4.5 VLVDHV5L C T LVDHV5 low voltage detector low threshold C — 4.2 — 4.4 1.08 — 1.17 1.08 — 1.17 V VLVDLVCORL C P LVDLVCOR low voltage detector low threshold C VLVDLVBKPL C P LVDLVBKP low voltage detector low threshold C TA = 25 °C, after trimming 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3.9 Low voltage domain power consumption Table 25 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. 70/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Table 25. Low voltage power domain electrical characteristics(1) Symbol IDDMAX(5) C C RUN mode maximum D C average current — at 120 MHz P IDDRUN C RUN mode typical D C average current(8) C IDDHALT C P HALT mode current(11) C C IDDSTOP C P STOP mode current(12) C C TA = 25 °C Min Typ(3) — 210 — 150 (8) Unit Max(4) 300(6), (7) mA 208(9) mA (10) mA at 80 MHz TA = 25 °C — at 120 MHz TA = 125 °C — 180 280 mA at 120 MHz TA = 25 °C — 20 27 mA at 120 MHz TA = 125 °C — 35 100 mA TA = 25 °C — 0.4 5 mA TA = 125 °C — 16 72 mA TA = 25 °C — 50 96 µA TA = 125 °C — 630 2400 µA TA = 25 °C — 40 92 µA TA = 125 °C — 500 2000 µA TA = 25 °C — 25 85 µA TA = 125 °C — 230 1100 µA — TA = 25 °C — — 5 µA — TA = 25 °C — — 3 mA — TA = 25 °C — — 500 µA — TA = 25 °C — — 5 µA No clocks active IDDSTDBY3 (96 KB RAM retained) P C STANDBY3 mode C C current(13) IDDSTDBY2 (64 KB RAM retained) C C STANDBY2 mode C C current(14) No clocks active IDDSTDBY1 (8 KB RAM retained) C C STANDBY1 mode C C current(15) No clocks active 110 150 No clocks active 32 KHz OSC Adders in LP mode Value Conditions(2) Parameter 4–40 MHz OSC C T C 16 MHz IRC 128 KHz IRC 1. Except for IDDMAX, all the current values are total current drawn from VDD_HV_A. 2. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified All temperatures are based on an ambient temperature. 3. Target typical current consumption for the following typical operating conditions and configuration. Process = typical, Voltage = 1.2 V. 4. Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage = 1.32 V. 5. Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 6. Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 23. 7. Maximum “allowed” current is package dependent. 8. Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. RUN current measured with typical application with accesses on both code flash and RAM. DocID17478 Rev 9 71/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx 9. Subject to change, Configuration: 1 e200z4d + 4 kbit/s Cache, 1 e200z0h (1/2 system frequency), CSE, 1 eDMA (10 ch.), 6 FlexCAN (4 500 kbit/s, 2 125 kbit/s), 4 LINFlexD (20 kbit/s), 6 DSPI (2 2 Mbit/s, 3 4 Mbit/s, 1 10 Mbit/s), 16 Timed I/O, 16 ADC Input, 1 FlexRay (2 ch., 10 Mbit/s), 1 FEC (100 Mbit/s), 1 RTC, 4PIT channels, 1 SWT, 1 STM. For lower pin count packages reduce the amount of timed I/O’s and ADC channels. RUN current measured with typical application with accesses on both code flash and RAM. 10. This value is obtained from limited sample set. 11. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication, instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs. 12. Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON. All possible peripherals off and clock gated. Flash in power down mode. 13. Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum consumption, all possible modules switched-off. Measurement condition assumes Tj = Ta. 14. LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum consumption, all possible modules switched-off. Measurement condition assumes Tj = Ta. 15. LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules switched OFF. Measurement condition assumes Tj = Ta. 3.10 Flash memory electrical characteristics 3.10.1 Program/Erase characteristics Table 26 shows the code flash memory program and erase characteristics. Table 26. Code flash memory—Program and erase specifications Value Symbol C Parameter Unit Min Typ(1) Initial max(2) Max(3) Double word (64 bits) program time(4) — 18 50 500 µs 16 KB block pre-program and erase time — 200 500 5000 ms 32 KB block pre-program and erase time — 300 600 5000 ms — 600 1300 5000 ms — — 30 30 µs C Erase Suspend Request Rate 20 — — — ms tPABT D Program Abort Latency — — 10 10 µs tEAPT D Erase Abort Latency — — 30 30 µs Tdwprogram T16Kpperase T32Kpperase C T128Kpperase C 128 KB block pre-program and erase time C D Erase Suspend Latency Teslat tESRT(5) 1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. 5. It is Time between erase suspend resume and the next erase suspend request. Table 27 shows the data flash memory program and erase characteristics. 72/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Table 27. Data flash memory—Program and erase specifications Value Symbol C Word (32 bits) program time(4) Twprogram C 16 KB block pre-program and erase time T16Kpperase Teslat tESRT(5) Parameter C D Erase Suspend Latency C C Erase Suspend Request Rate Unit Min Typ(1) Initial max(2) Max(3) — 30 70 500 µs — 700 800 5000 ms — — 30 30 µs 10 — — — ms tPABT D Program Abort Latency — — 12 12 µs tEAPT D Erase Abort Latency — — 30 30 µs 1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. 5. It is time between erase suspend resume and next erase suspend. Table 28. Flash memory module life Value Symbol P/E C CC Parameter Conditions Typ Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (TJ) — 100000 100000 cycles Number of program/erase cycles per block for 32 Kbyte blocks over C the operating temperature range (TJ) — 10000 100000 cycles — 1000 100000 cycles Blocks with 0–1000 P/E cycles 20 — years Blocks with 10000 P/E cycles 10 — years Blocks with 100000 P/E cycles 5 — years Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) Retention CC Unit Min C Minimum data retention at 85 °C average ambient temperature(1) 1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. DocID17478 Rev 9 73/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 29. Flash memory read access timing(1) Conditions(2) Symbol fREAD C CC Frequency Parameter Code flash memory Data flash memory range P 5 wait states 13 wait states 120 —100 C 4 wait states 11 wait states 100—80 D Maximum frequency for Flash C reading 3 wait states 9 wait states 80—64 2 wait states 7 wait states 64—40 C 1 wait states 4 wait states 40—20 C 0 wait states 2 wait states 20—0 Unit MHz 1. Max speed is the maximum speed allowed including PLL frequency modulation (FM). 2. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 3.10.2 Flash memory power supply DC characteristics Table 30 shows the flash memory power supply DC characteristics on external supply. Table 30. Flash memory power supply DC electrical characteristics Symbol Value(2) Conditions(1) Parameter Unit Min Typ Max ICFREAD(3) Code flash memory IDFREAD Data flash memory 13 Code flash memory 52 Flash memory module C Sum of the current consumption read C on VDD_HV_A on read access (3) fCPU = 120 MHz  2%(4) ICFMOD(3) IDFMOD(3) ICFLPW(3) ICFPWD(3) IDFPWD(3) Program/Erase on-going C Sum of the current consumption while reading flash C on VDD_HV_A (program/erase) memory registers fCPU = 120 MHz  2% (4) Sum of the current consumption C on VDD_HV_A during flash C memory low power mode Sum of the current consumption C on VDD_HV_A during flash C memory power down mode mA mA Data flash memory 13 Code flash memory 1.1 Code flash memory 150 Data flash memory 150 mA µA 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = –40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Data based on characterization results, not tested in production. 4. fCPU 120 MHz  2 % can be achieved over full temperature 125 °C ambient, 150 °C junction temperature. 74/123 33 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx 3.10.3 Electrical Characteristics Flash memory start-up/switch-off timings Table 31. Start-up time/Switch-off time Symbol TFLARSTEXIT C C C D Delay for flash memory module to exit reset mode C C T Delay for flash memory module to exit low-power mode Unit (1) Code flash memory Code flash memory Min Typ — — — Data flash memory TFLALPEXIT Value Conditions Parameter — Max 125 — — — — 0.5 µs TFLAPDEXIT C C Delay for flash memory module to exit T power-down mode Code flash memory — — Data flash memory TFLALPENTR Y C C T Delay for flash memory module to enter low-power mode Code flash memory — — 30 — — — — 0.5 1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified. 3.11 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 3.11.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for the application.   Software recommendations The software flowchart must include the management of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical data corruption (control registers) Pre-qualification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note Software Techniques For Improving Microcontroller EMC Performance (AN1015)). DocID17478 Rev 9 75/123 122 Electrical Characteristics 3.11.2 SPC564Bxx-SPC56ECxx Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI measurements. Table 32. EMI radiated emission measurement(1)(2) Value Symbol C Parameter Conditions Unit Min — S R — Scan range fCPU S R — VDD_LV S R — SEMI C C Typ — 0.150 Operating frequency — — LV operating voltages — VDD = 5 V, TA = 25 °C, LQFP176 package Test conforming to IEC 61967-2, fOSC = 40 MHz/fCPU = 120 MHz T Peak level Max 1000 MHz 120 — MHz — 1.28 — V No PLL frequency modulation — — 18 dBµV ± 2% PLL frequency modulation — — 14(3) dBµV 1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4. 2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3. All values need to be confirmed during device validation. 3.11.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.11.3.1 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts (n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note Electrostatic Discharge Sensitivity Measurement (AN1181). Table 33. ESD absolute maximum ratings(1)(2) Class Max value(3) TA = 25 °C conforming to AEC-Q100-002 H1C 2000 Electrostatic discharge voltage (Machine Model) TA = 25 °C conforming to AEC-Q100-003 M2 200 Electrostatic discharge voltage (Charged Device Model) TA = 25 °C conforming to AEC-Q100-011 C3A Symbol Ratings VESD(HBM) Electrostatic discharge voltage (Human Body Model) VESD(MM) VESD(CDM) 76/123 Conditions DocID17478 Rev 9 500 750 (corners) Unit V SPC564Bxx-SPC56ECxx Electrical Characteristics 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3. Data based on characterization results, not tested in production. 3.11.3.2 Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance:  A supply over-voltage is applied to each power supply pin.  A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 34. Latch-up results Symbol LU 3.12 Parameter Static latch-up class Conditions TA = 125 °C conforming to JESD 78 Class II level A Fast external crystal oscillator (4–40 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 35 provides the parameter description of 4 MHz to 40 MHz crystals used for the design simulations. DocID17478 Rev 9 77/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Figure 10. Crystal oscillator and resonator connection scheme EXTAL C1 Crystal XTAL XTAL RD C2 DEVICE VDD I R EXTAL EXTAL Resonator DEVICE XTAL DEVICE Note: XTAL/EXTAL must not be directly used to drive external circuits. Table 35. Crystal description Crystal motional capacitance (Cm) fF Crystal motional inductance (Lm) mH Load on xtalin/xtalout C1 = C2 (pF)(1) Shunt capacitance between xtalout and xtalin C0(2) (pF) Nominal frequency (MHz) NDK crystal reference Crystal equivalent series resistance ESR  4 NX8045GB 300 2.68 591.0 21 2.93 8 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 120 3.11 56.5 15 2.93 120 3.90 25.3 10 3.00 50 6.18 2.56 8 3.49 12 NX5032GA 16 40 NX5032GA 1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 78/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics S_MTRANS bit (ME_GS register) 1 0 VXTAL 1/fMXOSC VFXOSC 90% VFXOSCOP 10% TMXOSCSU valid internal clock Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics Symbol fFXOSC C Parameter Fast external SR — crystal oscillator frequency Value(2) Conditions(1) — Unit Min Typ Max 4.0 — 40.0 VDD = 3.3 V ± 10% 4(3) — 20(3) gmFXOSC Fast external CC C crystal oscillator transconductance VDD = 5.0 V ± 10% 6.5(3) — 25(3) VFXOSC Oscillation CC T amplitude at EXTAL fOSC = 40 MHz For both VDD = 3.3 V ± 10%, VDD = 5.0 V ± 10% — 0.95 — — 1.8 VDD = 3.3 V ± 10%, fOSC = 40 MHz — 2 2.2 VDD = 5.0 V ± 10%, fOSC = 40 MHz — 2.3 2.5 VDD = 3.3 V ± 10%, fOSC = 16 MHz — 1.3 1.5 VDD = 5.0 V ± 10%, fOSC = 16 MHz — 1.6 1.8 fOSC = 40 MHz For both VDD = 3.3 V ± 10%, VDD = 5.0 V ± 10% — — 5 VFXOSCOP IFXOSC(4) TFXOSCSU CC P Oscillation operating point Fast external CC T crystal oscillator consumption Fast external CC T crystal oscillator start-up time — DocID17478 Rev 9 MHz mA/V V V mA ms 79/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics (continued) Symbol C Value(2) Conditions(1) Parameter VIH Input high level SR P CMOS (Schmitt Trigger) Oscillator bypass mode VIL Input low level SR P CMOS (Schmitt Trigger) Oscillator bypass mode Unit Min Typ Max 0.65VDD_ — VDD_HV_A + 0.4 V — 0.35VDD_HV_A V HV_A 0.3 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Based on ATE Cz 4. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals). 3.13 Slow external crystal oscillator (32 kHz) electrical characteristics The device provides a low power oscillator/resonator driver. Figure 12. Crystal oscillator and resonator connection scheme OSC32K_EXTAL OSC32K_EXTAL Resonator Crystal C1 RP OSC32K_XTAL C2 DEVICE Note: OSC32K_XTAL DEVICE OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. l 80/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics Figure 13. Equivalent circuit of a quartz crystal C0 C1 Crystal Cm C2 Rm Lm C1 C2 Table 37. Crystal motional characteristics(1) Value Symbol Parameter Conditions Unit Min Typ Max Lm Motional inductance — — 11.796 — KH Cm Motional capacitance — — 2 — fF Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground(2) — 18 — 28 pF C1/C2 AC coupled @ C0 = 2.85 pF(4) Rm(3) — — 65 pF(4) — — 50 AC coupled @ C0 = 7.0 pF(4) — — 35 AC coupled @ C0 = 9.0 pF(4) — — 30 AC coupled @ C0 = 4.9 Motional resistance kW 1. The crystal used is Epson Toyocom MC306. 2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3. Maximum ESR (Rm) of the crystal is 50 k 4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins. DocID17478 Rev 9 81/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics OSCON bit (OSC_CTL register) 1 0 VOSC32K_XTAL 1/fLPXOSC32K VLPXOSC32K 90% 10% TLPXOSC32KSU valid internal clock Table 38. Slow external crystal oscillator (32 kHz) electrical characteristics Symbol C Value(2) Conditions(1) Parameter Unit Min Typ Max 32 32.76 8 40 VDD = 3.3 V ± 10%, 13(3) — 33(3) VDD = 5.0 V ± 10% 15(3) — 35(3) fSXOSC S Slow external crystal oscillator — R frequency gmSXOSC C Slow external crystal oscillator — C transconductance VSXOSC C C T Oscillation amplitude — 1.2 1.4 1.7 V ISXOSCBIAS C C T Oscillation bias current — 1.2 — 4.4 µA ISXOSC C C T Slow external crystal oscillator consumption — — — 7 µA TSXOSCSU C C T Slow external crystal oscillator start-up time — — — 2(4) s — 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Based on ATE CZ 4. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal. 82/123 DocID17478 Rev 9 kHz µA/V SPC564Bxx-SPC56ECxx 3.14 Electrical Characteristics FMPLL electrical characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 39. FMPLL electrical characteristics Symbol C Parameter Conditions Value(2) (1) Unit Min Typ Max fPLLIN S — FMPLL reference clock(3) R — 4 — 64 MHz PLLIN S FMPLL reference clock — R duty cycle(3) — 40 — 60 % fPLLOUT C FMPLL output clock P C frequency — 16 — 120 MHz fCPU S — System clock frequency R — — — fFREE C P Free-running frequency C — 20 — 150 MHz tLOCK C P FMPLL lock time C Stable oscillator (fPLLIN = 16 MHz) 40 100 µs tLTJIT C — FMPLL long term jitter C fPLLIN = 40 MHz (resonator), fPLLCLK @ 120 MHz, 4000 cycles — — 6 (for < 1ppm) ns C C FMPLL consumption C TA = 25 °C — — 3 mA IPLL 120 + 2%(4) MHz 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 4. fCPU 120 + 2% MHz can be achieved at 125 °C. 3.15 Fast internal RC oscillator (16 MHz) electrical characteristics The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device and can also be used as input to PLL. Table 40. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol fFIRC C Value(2) Conditions(1) Parameter C P C Fast internal RC oscillator high frequency S — R TA = 25 °C, trimmed DocID17478 Rev 9 Unit Min Typ Max — 16 — MHz — 12 20 83/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Table 40. Fast internal RC oscillator (16 MHz) electrical characteristics (continued) Symbol C IFIRCRUN(3) Fast internal RC oscillator high C T frequency current in running C mode IFIRCPWD D Fast internal RC oscillator high C D frequency current in power C down mode D IFIRCSTOP Typ Max TA = 25 °C, trimmed — — 200 µA TA = 25 °C — — 100 nA TA = 55 °C — — 200 nA TA = 125 °C — — 1 µA sysclk = off — 500 — sysclk = 2 MHz — 600 — sysclk = 4 MHz — 700 — sysclk = 8 MHz — 900 — sysclk = 16 MHz — 1250 — VDD = 5.0 V ± 10% — — 2.0 VDD = 3.3 V ± 10% — — 5 Fast internal RC oscillator high C T frequency and system clock TA = 25 °C C current in stop mode TA = 55 °C — C C Unit Min C TFIRCSU Value(2) Conditions(1) Parameter Fast internal RC oscillator start-up time µs — TA = 125 °C — VDD = 5.0 V ± 10% — — 2.0 VDD = 3.3 V ± 10% — — 5 +1 FIRCPRE Fast internal RC oscillator C C precision after software C trimming of fFIRC TA = 25 °C 1 — FIRCTRIM C Fast internal RC oscillator C C trimming step TA = 25 °C — 1.6 FIRCVAR Fast internal RC oscillator variation over temperature and C C supply with respect to fFIRC at C TA = 25 °C in high-frequency configuration — 5 — +5 2. All values need to be confirmed during device validation. 3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. DocID17478 Rev 9 % % 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 84/123 µA % SPC564Bxx-SPC56ECxx 3.16 Electrical Characteristics Slow internal RC oscillator (128 kHz) electrical characteristics The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module. Table 41. Slow internal RC oscillator (128 kHz) electrical characteristics Symbol fSIRC C Parameter Conditions C P C Slow internal RC oscillator low frequency S — R Value(2) (1) TA = 25 °C, trimmed Unit Min Typ Max — 128 — kHz untrimmed, across temperatures 84 — 205 TA = 25 °C, trimmed — — 5 µA µs ISIRC(3) C Slow internal RC oscillator low C C frequency current TSIRCSU C Slow internal RC oscillator startP C up time TA = 25 °C, VDD = 5.0 V ± 10% — 8 12 SIRCPRE Slow internal RC oscillator C C precision after software trimming C of fSIRC TA = 25 °C 2 — +2 SIRCTRIM C Slow internal RC oscillator C C trimming step — — 2.7 — SIRCVAR Variation in fSIRC across C C temperature and fluctuation in C supply voltage, post trimming — 10 — +10 % % 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 3.17 ADC electrical characteristics 3.17.1 Introduction The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit). Note: Due to ADC limitations, the two ADCs cannot sample a shared channel at the same time i.e., their sampling windows cannot overlap if a shared channel is selected. If this is done, neither of the ADCs can guarantee their conversion accuracies. DocID17478 Rev 9 85/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Figure 15. ADC_0 characteristic and error definitions Offset Error OSE Gain Error GE 1023 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 (1) Example of an actual transfer curve 5 (2) The ideal transfer curve (5) (3) Differential non-linearity error (DNL) 4 (4) Integral non-linearity error (INL) (4) (5) Center of a step of the actual transfer curve 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE 3.17.1.1 Input impedance and ADC accuracy To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device, can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. 86/123 DocID17478 Rev 9 SPC564Bxx-SPC56ECxx Electrical Characteristics In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being CS and Cp2 substantially two switched capacitances, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1MHz, with CS+Cp2 equal to 3pF, a resistance of 330K is obtained (Reqiv = 1 / (fc*(CS+Cp2)), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF, the external circuit must be designed to respect the following relation Equation 4 RS + RF 1 V A  ---------------------  --- LSB R EQ 2 The formula above provides a constraint for external network design, in particular on resistive path. Figure 16. Input equivalent circuit (precise channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF VA Current Limiter RL CF CP1 Channel Selection Sampling RSW RAD CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW Channel Selection Switch Impedance RADSampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance DocID17478 Rev 9 87/123 122 Electrical Characteristics SPC564Bxx-SPC56ECxx Figure 17. Input equivalent circuit (extended channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source Filter RS Current Limiter RF RL CF VA CP1 Channel Selection Extended Switch Sampling RSW1 RSW2 RAD CP3 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2) RADSampling Switch Impedance CP Pin Capacitance (three contributions, CP1, CP2 and CP3) CS Sampling Capacitance A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed. Figure 18. Transient behavior during sampling phase Voltage Transient on CS VCS VA V