SPC584Bx
32-bit Power Architecture microcontroller for automotive ASIL-B
applications
Datasheet - production data
eTQFP64 (10 x 10 x 1.0 mm)
eTQFP144 (20 x 20 x 1.0 mm)
eTQFP100 (14 x 14 x 1.0 mm)
eTQFP176 (24 x 24 x 1.4 mm)
Features
AEC-Q100 qualified
High performance e200z420
– 32-bit Power Architecture technology CPU
– Core frequency as high as 120 MHz
– Variable Length Encoding (VLE)
2112 KB (2048 KB code flash + 64 KB data
flash) on-chip flash memory: supports read
during program and erase operations, and
multiple blocks allowing EEPROM emulation
176 KB HSM dedicated flash memory (144 KB
code + 32 KB data)
128 KB on-chip general-purpose SRAM (in
addition to 64 KB core local data RAM
Crossbar switch architecture for concurrent
access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
Multi-channel direct memory access controller
(eDMA) with 64 channels
1 interrupt controller (INTC)
Comprehensive new generation ASIL-B safety
concept
– ASIL-B of ISO 26262
– FCCU for collection and reaction to failure
notifications
September 2019
This is information on a product in full production.
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
– Cyclic redundancy check (CRC) unit
Enhanced low power support
– Ultra low power STANDBY
– Smart Wake-up Unit
– Fast wake-up and execute from RAM
Enhanced modular IO subsystem (eMIOS): up
to 64 timed I/O channels with 16-bit counter
resolution
Body cross triggering unit (BCTU)
– Triggers ADC conversions from any eMIOS
channel
– Triggers ADC conversions from up to 2
dedicated PIT_RTIs
Enhanced analog-to-digital converter system
with:
– 2 independent fast 12-bit SAR analog
converters
– 1 supervisor 12-bit SAR analog converter
– 1 10-bit SAR analog converter with STDBY
mode support
Communication interfaces
– 1 Ethernet controller 10/100 Mbps,
compliant IEEE 802.3-2008
– 8 MCAN interfaces with advanced shared
memory scheme and ISO CAN-FD support
– 14 LINFlexD modules
– 7 Deserial Serial Peripheral Interface
(DSPI) modules
Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
domain for computational shell
Nexus Development Interface (NDI) per IEEEISTO 5001-2003 standard, with some support
for 2010 standard
DS11701 Rev 4
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www.st.com
SPC584Bx
Boot Assist Flash (BAF) supports factory programming using a serial bootload through the
asynchronous CAN or LIN/UART
Junction temperature range -40 °C to 150 °C
Table 1. Device summary
Part number
Package
2/142
1 MB
1.5 MB
2 MB
eTQFP64
SPC584B60E1
SPC584B64E1
SPC584B70E1
eTQFP100
SPC584B60E3
SPC584B64E3
SPC584B70E3
eTQFP144
SPC584B60E5
SPC584B64E5
SPC584B70E5
eLQFP176
SPC584B60E7
SPC584B64E7
SPC584B70E7
DS11701 Rev 4
SPC584Bx
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1
Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 18
4.4
Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5
Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 21
4.6
Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7
Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.8
I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8.1
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8.2
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.8.3
I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.9
Reset pad (PORST) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 37
4.10
PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.11
4.12
4.10.1
PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.10.2
PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.11.1
Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.11.2
Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.11.3
RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.11.4
Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.12.1
ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DS11701 Rev 4
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5
Contents
SPC584Bx
SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.12.3
SAR ADC 10 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.13
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.14
LFAST pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.15
5
4.12.2
4.14.1
LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.14.2
LFAST LVDS interface electrical characteristics . . . . . . . . . . . . . . . . . . 58
4.14.3
LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.15.1
Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.15.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.15.3
Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.16
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.17
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.17.1
Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.17.2
DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.17.3
Ethernet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.17.4
CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.17.5
UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.17.6
I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1
eTQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.1.1
5.2
eTQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.1
5.3
4/142
Package mechanical drawings and data information . . . . . . . . . . . . . 116
eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.4.1
5.5
Package mechanical drawings and data information . . . . . . . . . . . . . 111
eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.3.1
5.4
Package mechanical drawings and data information . . . . . . . . . . . . . 106
Package mechanical drawings and data information . . . . . . . . . . . . . 121
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.1
eTQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.2
eTQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5.3
eTQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.5.4
LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.5.5
General notes for specifications at maximum junction temperature . . 125
DS11701 Rev 4
SPC584Bx
Contents
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
DS11701 Rev 4
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5
Introduction
1
SPC584Bx
Introduction
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.
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DS11701 Rev 4
SPC584Bx
2
Description
Description
The SPC584Bx microcontroller is a member of the family of devices superseding the
SPC560Bx family. SPC584Bx is built on the legacy of the SPC560Bx family, while
introducing new features coupled with higher throughput to provide substantial reduction of
cost per feature and significant power and performance improvement (MIPS per mW). On
the SPC584Bx device, there is one processor core e200z420 and one e200z0 core
embedded in the Hardware Security Module.
2.1
Device feature summary
Table 2 lists a summary of major features for the SPC584Bx device. The feature column
represents a combination of module names and capabilities of certain modules. A detailed
description of the functionality provided by each on-chip module is given later in this
document.
Table 2. Features list
Feature
Description
SPC58 family
40 nm
Number of Cores
1
Local RAM
64 KB Data
Single Precision Floating Point
Yes
SIMD
No
VLE
Yes
8 KB Instruction
Cache
4 KB Data
Core MPU: 24 per CPU
MPU
System MPU: 24 per XBAR
Semaphores
No
CRC Channels
2x4
Software Watchdog Timer (SWT)
2
Core Nexus Class
3+
4 x SCU
Event Processor
4 x PMC
Run control Module
Yes
System SRAM
128 KB (full standby RAM)
Flash
2048 KB code / 64 KB data
Flash fetch accelerator
2 x 4 x 256-bit
DMA channels
32
DMA Nexus Class
3
DS11701 Rev 4
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12
Description
SPC584Bx
Table 2. Features list (continued)
Feature
Description
LINFlexD
14
MCAN (ISO CAN-FD compliant)
8
DSPI
7
I2C
1
Ethernet
1 MAC with Time Stamping, AVB and VLAN support
SIPI / LFAST Debugger
High Speed
8 PIT channels
System Timers
1 AUTOSAR® (STM)
RTC/API
eMIOS
2 x 32 channels
BCTU
64 channels
ADC (SAR)
4
Temp. sensor
Yes
Self Test Controller
Yes
PLL
Dual PLL with FM
Integrated linear voltage regulator
Yes
External Power Supplies
5 V, 3.3 V
HALT Mode
Low Power Modes
STOP Mode
Smart Standby with output controller, analog and digital inputs
Standby Mode
2.2
Block diagram
The figures below show the top-level block diagrams.
8/142
DS11701 Rev 4
SPC584Bx
Description
Figure 1. Block diagram
JTAGM
JTAGC
DCI
SPU
NPC
INTC
SWT IAC
e200 z420n3 – 120 MHz
dual issue
Nexus3p
Main Core
Concentrator_1
E2E ECC
PAMU
DMA CHMUX_1
DMA CHMUX_0
SIPI_1
ETHERNET_0
VLE
64 Ch
eDMA
I-Cache
Control
HSM
8 KB
2 way
32 ADD
32 DATA
SBI
(32 to 64)
EFPU2
D-MEM
Control
D-Cache
Control
64 KB
D-MEM
4 KB
2 way
Unified
Backdoor
Interface
With
E2E ECC
32 ADD
32 ADD
64 DATA
64 DATA
Core Memory Protection Unit
(CMPU)
Nexus Data
Trace
Nexus Data
Trace
BIU with E2E ECC
Decorated Storage Access
32 ADD
64 DATA
32 ADD
64 DATA
Instruction
32 ADD
64 DATA
Load / Store
32 ADD
64 DATA
AHB_M
AHB_M4
AHB_M6
AHB_M
AHB_M
AHB_M
Nexus Data
Trace
32 ADD
64 DATA
AHB_M
Cross Bar Switch (XBAR) AMBA 2.0 v6 AHB – 64 bit
System Memory Protection Unit
AHB_S
AHB_S
AHB_S
AHB_S
32 ADD
64 DATA
32 ADD
64 DATA
32 ADD
64 DATA
Periph. Bridge
AIPS_2
E2E ECC
Periph. Bridge
AIPS_1
E2E ECC
PRAMC
with E2E
ECC
32 ADD
32 DATA
32 ADD
32 DATA
32 ADD
64 DATA
Peripheral
Cluster 2
Peripheral
Cluster 1
SRAM
Array 2
128 KB
32 ADD
64 DATA
AHB_S
32 ADD
64 DATA
PFLASHC
Set-Associative
Prefetch Buffers
with E2E ECC
DS11701 Rev 4
AHB_S
256 Page Line
FLASH
2 MB
EEPROM
4x16 KB
Non Volatile Memory
Multiple RWW partitions
9/142
12
Description
SPC584Bx
Figure 2. Periphery allocation
PBRIDGE_2
BCTU_0
STDBY_CTU_0
XBAR_1
eMIOS_0
XBIC_Concentrator_0, 1
ETHERNET_0
SMPU_1
SAR_ADC_12bit_0
XBIC_1
SAR_ADC_10bit_STDBY
PCM_0
SAR_ADC_12bit_B0
PFLASH_1
I2C_0
INTC_1
DSPI_0, 2, 4, 6
SWT_2, 3
LINFlexD_0, 2, 4, 6, 8, 10, 12
STM_2
CAN_SUB_0_MESSAGE_RAM
eDMA_1
CAN_SUB_0_M_CAN_0..3
PRAM_2, 3
CCCU
TDM_0
HSM
DTS
JDC
JTAGM
MEMU
IMA
CRC_0
DMAMUX_0
PIT_0
RTC/API
WKPU
MC_PCU
PBRIDGE_2 – Peripheral Cluster 2
STCU
eMIOS_1
DSPI_1, 3, 5
LINFlexD_1, 3, 5, 7, 9, 11, 15
MC_RGM
CAN_SUB_1_MESSAGE_RAM
RCOSC_DIG
CAN_SUB_1_M_CAN_1..4
RC1024K_DIG
FCCU
OSC_DIG
CRC_1
OSC32K_DIG
DMAMUX_1
PLL_DIG
PIT_1
CMU_0_PLL0_XOSC_IRCOSC
CMU_1_CORE_XBAR
MC_CGM
CMU_2_HPBM
MC_ME
CMU_3_PBRIDGE
SIUL2
CMU_6_SARADC
FLASH_0
CMU_11_FBRIDGE
FLASH_ALT_0
CMU_12_EMIOS
PASS
CMU_14_PFBRIDGE
PBRIDGE_1 – Peripheral Cluster 1
PMC_DIG
SSCM
PBRIDGE_1
SAR_ADC_12bit_1
SIPI_1
LFAST_1
Note: In this diagram, ON-platform modules are shown in orange color and OFF-platform modules
are shown in blue color.
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DS11701 Rev 4
SPC584Bx
2.3
Description
Features overview
On-chip modules within SPC584Bx include the following features:
One main CPU, dual issue, 32-bit CPU core complexes (e200z4)
–
Power Architecture embedded specification compliance
–
Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
–
Single-precision floating point operations
–
64 KB local data RAM for Core_2
–
8 KB I-Cache and 4 KB D-Cache for Core_2
2112 KB (2048 KB code flash + 64 KB data flash) on-chip flash memory
–
Supports read during program and erase operations, and multiple blocks allowing
EEPROM emulation
176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
128 KB on-chip general-purpose SRAM (+ 64 KB local data RAM: 64 KB included in
the CPU)
Multi channel direct memory access controllers
–
32 eDMA channels
One interrupt controller (INTC)
Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
Hardware security module (HSM) with HW cryptographic co-processor
System integration unit lite (SIUL)
Boot assist Flash (BAF) supports factory programming using a serial bootload through
the asynchronous CAN or LIN/UART.
Hardware support for safety ASIL-B level related applications
Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with
16-bit counter resolution
–
Buffered updates
–
Support for shifted PWM outputs to minimize occurrence of concurrent edges
–
Supports configurable trigger outputs for ADC conversion for synchronization to
channel output waveforms
–
Shared or independent time bases
–
DMA transfer support available
Body Cross Triggering Unit (BCTU)
–
Triggers ADC conversions from any eMIOS channel
–
Triggers ADC conversions from up to 2 dedicated PIT_RTIs
–
One event configuration register dedicated to each timer event allows to define the
corresponding ADC channel
–
Synchronization with ADC to avoid collision
Enhanced analog-to-digital converter system with:
–
Two independent fast 12-bit SAR analog converters
DS11701 Rev 4
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12
Description
12/142
SPC584Bx
–
One supervisor 12-bit SAR analog converter
–
One 10-bit SAR analog converter with STDBY mode support
Seven Deserial Serial Peripheral Interface (DSPI) modules
Fourteen LIN and UART communication interface (LINFlexD) modules
–
LINFlexD_0 is a Master/Slave
–
All others are Masters
Eight modular controller area network (MCAN) modules, all supporting flexible data
rate (ISO CAN-FD compliant)
One ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008
–
IEEE 1588-2008 Time stamping (internal 64-bit time stamp)
–
IEEE 802.1AS and IEEE 802.1Qav (AVB-Feature)
–
IEEE 802.1Q VLAN tag detection
–
IPv4 and IPv6 checksum modules
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some
support for 2010 standard
Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and
IEEE 1149.7), 2-pin JTAG interface
Standby power domain with smart wake-up sequence
DS11701 Rev 4
SPC584Bx
3
Package pinouts and signal descriptions
Package pinouts and signal descriptions
Refer to the SPC584Bx IO_ Definition document.
It includes the following sections:
1.
Package pinouts
2.
Pin descriptions
a)
Power supply and reference voltage pins
b)
System pins
c)
LVDS pins
d)
Generic pins
DS11701 Rev 4
13/142
13
Electrical characteristics
SPC584Bx
4
Electrical characteristics
4.1
Introduction
The present document contains the target Electrical Specification for the 40 nm family 32-bit
MCU SPC584Bx products.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol”
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” (System Requirement) is included in the
“Symbol” column.
The electrical parameters shown in this document are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 3 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 3. Parameter classifications
Classification tag
14/142
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design validation on a small sample size from typical
devices.
D
Those parameters are derived mainly from simulations.
DS11701 Rev 4
SPC584Bx
4.2
Electrical characteristics
Absolute maximum ratings
Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Stress beyond the listed maxima, even momentarily, may affect device reliability or cause
permanent damage to the device.
Table 4. Absolute maximum ratings
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
SR
D
Core voltage
operating life
range(1)
—
–0.3
—
1.4
V
VDD_HV_IO_ETH
SR
D
I/O supply
voltage(2)
—
–0.3
—
6.0
V
VSS_HV_ADV
SR
D
ADC ground
voltage
Reference to
digital ground
–0.3
—
0.3
V
VDD_HV_ADV
SR
D
ADC Supply
voltage(2)
Reference to
VSS_HV_ADV
–0.3
—
6.0
V
VSS_HV_ADR_S
SR
D
SAR ADC
ground
reference
—
–0.3
—
0.3
V
VDD_HV_ADR_S
SR
D
SAR ADC
voltage
reference(2)
Reference to
VSS_HV_ADR_S
–0.3
—
6.0
V
VSS-VSS_HV_ADR_S
SR
D
VSS_HV_ADR_S
differential
voltage
—
–0.3
—
0.3
V
VSS-VSS_HV_ADV
SR
D
VSS_HV_ADV
differential
voltage
—
–0.3
—
0.3
V
—
–0.3
—
6.0
Relative to Vss
–0.3
—
—
Relative to
VDD_HV_IO and
VDD_HV_ADV
—
—
0.3
VDD_LV
VDD_HV_IO_MAIN
VDD_HV_OSC
VDD_HV_FLA
VIN
TTRIN
IINJ
SR
SR
SR
D
I/O input voltage
range(2)(3) (4)
V
D
Digital Input pad
transition time(5)
—
—
—
1
ms
T
Maximum DC
injection current
for each
analog/digital
PAD(6)
—
–5
—
5
mA
DS11701 Rev 4
15/142
16
Electrical characteristics
SPC584Bx
Table 4. Absolute maximum ratings (continued)
Value
Symbol
TSTG
TPAS
C
SR
SR
Parameter
Conditions
Unit
Min
Typ
Max
T
Maximum nonoperating
Storage
temperature
range
—
–55
—
125
°C
C
Maximum
nonoperating
temperature
during passive
lifetime
—
–55
—
150(7)
°C
No supply; storage
temperature in
range –40 °C to
60 °C
—
—
20
years
TSTORAGE
SR
—
Maximum
storage time,
assembled part
programmed in
ECU
TSDR
SR
T
Maximum solder
temperature Pbfree packaged(8)
—
—
—
260
°C
MSL
SR
T
Moisture
sensitivity
level(9)
—
—
—
3
—
Maximum
cumulated
XRAY dose
Typical range for
X-rays source
during
inspection:80 ÷
130 KV; 20 ÷
50 A
—
—
1
grey
TXRAY dose
SR
T
1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed
1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3:
Operating conditions.
2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative
time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating
conditions.
3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin
to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal
calculations.
4. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum
limits to the transition time.
6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
7. 175 °C are allowed for limited time. Mission profile with passive lifetime temperature >150 °C have to be evaluated by ST to
confirm that are granted by product qualification.
8. Solder profile per IPC/JEDEC J-STD-020D.
9. Moisture sensitivity per JDEC test method A112.
16/142
DS11701 Rev 4
SPC584Bx
4.3
Electrical characteristics
Operating conditions
Table 5 describes the operating conditions for the device, and for which all the specifications
in the data sheet are valid, except where explicitly noted. The device operating conditions
must not be exceeded or the functionality of the device is not guaranteed.
Table 5. Operating conditions
Value(1)
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
FSYS
SR
P
Operating
system clock
frequency(2)
—
—
—
120
MHz
TA_125 Grade(3)
SR
D
Operating
Ambient
temperature
—
–40
—
125
°C
TJ_125 Grade(3)
SR
P
Junction
temperature
under bias
TA = 125 °C
–40
—
150
°C
TA_105 Grade(3)
SR
D
Ambient
temperature
under bias
—
–40
—
105
°C
TJ_105 Grade(3)
SR
D
Operating
Junction
temperature
TA = 105 °C
–40
—
130
°C
VDD_LV
SR
P
Core supply
voltage(4)
—
1.14
1.20
1.26(5) (6)
V
VDD_HV_IO_MAIN
VDD_HV_IO_ETH
VDD_HV_FLA
VDD_HV_OSC
SR
P
IO supply
voltage
—
3.0
—
5.5
V
VDD_HV_ADV
SR
P
ADC supply
voltage
—
3.0
—
5.5
V
VSS_HV_ADVVSS
SR
D
ADC ground
differential
voltage
—
–25
—
25
mV
VDD_HV_ADR_S
SR
P
SAR ADC
reference
voltage
—
3.0
—
5.5
V
D
SAR ADC
reference
differential
voltage
—
—
—
25
mV
P
SAR ADC
ground
reference
voltage
—
VDD_HV_ADR_SVDD_HV_ADV
VSS_HV_ADR_S
SR
SR
DS11701 Rev 4
VSS_HV_ADV
V
17/142
19
Electrical characteristics
SPC584Bx
Table 5. Operating conditions (continued)
Value(1)
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
VSS_HV_ADR_SVSS_HV_ADV
SR
D
VSS_HV_ADR_S
differential
voltage
—
–25
—
25
mV
VRAMP_HV
SR
D
Slew rate on
HV power
supply
—
—
—
100
V/ms
VIN
SR
P
I/O input
voltage range
—
0
—
5.5
V
Digital pins and
analog pins
–3.0
—
3.0
mA
Digital pins and
analog pins
–10
—
10
mA
IINJ1
SR
T
Injection
current (per
pin) without
performance
degradation(7)
(8) (9)
IINJ2
SR
D
Dynamic
Injection
current (per
pin) with
performance
degradation(9)
(10)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the
Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.
3. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to
Section 5.5: Package thermal characteristics.
4. Core voltage as measured on device pin to guarantee published silicon performance.
5. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that
HVD134_C monitor reset is disabled.
6. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to
1.236 V at the given temperature profile.
7. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these
limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements.
8. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is
above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
9. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
10. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not
granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for
maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011),
Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).
4.3.1
Power domains and power up/down sequencing
The following table shows the constraints and relationships for the different power domains.
Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and
column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as
well as during normal device operation.
18/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Table 6. Device supply relation during power-up/power-down sequence
Supply2
Supply1
VDD_LV
VDD_HV_IO_ETH
VDD_HV_IO_MAIN
VDD_HV_FLA
VDD_HV_OSC
VDD_HV_ADV
VDD_HV_ADR
not allowed
ok
ok
ok
ok
VDD_HV_IO_ETH
ok
VDD_HV_IO_MAIN
VDD_HV_FLA
VDD_HV_OSC
ok
ok
VDD_HV_ADV
ok
ok
not allowed
VDD_HV_ADR
ok
ok
not allowed
ok
not allowed
During power-up, all functional terminals are maintained in a known state as described in
the device pinout Microsoft Excel file attached to the IO_Definition document.
DS11701 Rev 4
19/142
19
Electrical characteristics
4.4
SPC584Bx
Electrostatic discharge (ESD)
The following table describes the ESD ratings of the device:
All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
Device failure is defined as: “If after exposure to ESD pulses, the device does not meet
the device specification requirements, which include the complete DC parametric and
functional testing at room temperature and hot temperature, maximum DC parametric
variation within 10 % of maximum specification”.
Table 7. ESD ratings
Parameter
ESD for Human Body Model (HBM)(1)
ESD for field induced Charged Device Model (CDM)(2)
C
Conditions
Value
Unit
T
All pins
2000
V
T
All pins
500
V
T
Corner pins
750
V
1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.
2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.
20/142
DS11701 Rev 4
SPC584Bx
4.5
Electrical characteristics
Electromagnetic compatibility characteristics
EMC measurements at IC-level IEC standards are available from STMicroelectronics on
request.
DS11701 Rev 4
21/142
21
Electrical characteristics
4.6
SPC584Bx
Temperature profile
The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL
1,000 h and HTDR 1,000 hrs, TJ = 150 °C.
22/142
DS11701 Rev 4
SPC584Bx
4.7
Electrical characteristics
Device consumption
Table 8. Device consumption
Value(1)
Symbol
IDD_LKG(2),(3)
C
CC
Parameter
Conditions
Unit
Min
Typ
Max
C
TJ = 40 °C
—
—
7
D
TJ = 25 °C
—
1.5
5
D Leakage current on the
VDD_LV supply
D
TJ = 55 °C
—
—
10
TJ = 95 °C
—
—
25
D
TJ = 120 °C
—
—
45
P
TJ = 150 °C
—
—
90
—
—
—
125
mA
mA
IDD_LV(3)
CC
P
Dynamic current on
the VDD_LV supply,
very high consumption
profile(4)
IDD_HV
CC
P
Total current on the
VDD_HV supply(4)
fMAX
—
—
55
mA
IDD_LV_GW
CC
T
Dynamic current on
the VDD_LV supply,
gateway profile(5)
—
—
—
98
mA
IDD_HV_GW
CC
T
Dynamic current on
the VDD_HV supply,
gateway profile(5)
—
—
—
22
mA
IDD_LV_BCM
CC
T
Dynamic current on
the VDD_LV supply,
body profile(6)
—
—
—
79
mA
IDD_HV_BCM
CC
T
Dynamic current on
the VDD_HV supply,
body profile(6)
—
—
—
29
mA
IDD_HSM_AC
CC
T
HSM platform dynamic
operating current(7)
fMAX/2
—
—
15
mA
T
Dynamic current on
the VDD_LV supply
+Total current on the
VDD_HV supply
—
—
54
63
mA
T
Dynamic current on
the VDD_LV supply
+Total current on the
VDD_HV supply
—
—
18
24
mA
TJ = 25 °C
—
55
120
TJ = 40 °C
—
—
180
TJ = 55 °C
—
—
280
TJ = 120 °C
—
0.8
1.65
TJ = 150 °C
—
1.8
3.8
IDDHALT
(8)
IDDSTOP(9)
CC
CC
D
C
IDDSTBY8
CC
D
D
Total standby mode
current on VDD_LV and
VDD_HV supply, 8 KB
RAM(10)
P
DS11701 Rev 4
µA
mA
23/142
25
Electrical characteristics
SPC584Bx
Table 8. Device consumption (continued)
Value(1)
Symbol
C
Parameter
Typ
Max
TJ = 25 °C
—
60
130
TJ = 40 °C
—
—
200
TJ = 55 °C
—
—
300
TJ = 120 °C
—
—
1.8
P
TJ = 150 °C
—
—
4.1
D
TJ = 25 °C
—
90
160
µA
TJ = 40 °C
—
—
250
µA
TJ = 55 °C
—
—
370
µA
TJ = 120 °C
—
1.2
2.2
TJ = 150 °C
—
2.8
5.0
D
SSWU running over all
STANDBY period with
OPC/TU commands
execution and keeping
ADC off(11)
TJ = 40 °C
—
1.0
3.5
mA
D
SSWU running over all
STANDBY period with
OPC/TU/ADC
commands execution
and keeping ADC
on(12)
TJ = 40 °C
—
3.5
5.0
mA
C
CC
D
D
C
IDDSTBY128
CC
D
D
Total standby mode
current on VDD_LV and
VDD_HV supply, 32 KB
RAM(10)
Total standby mode
current on VDD_LV and
VDD_HV supply,
128 KB RAM(10)
P
IDDSSWU1
IDDSSWU2
CC
CC
Unit
Min
D
IDDSTBY32
Conditions
µA
mA
mA
1. The ranges in this table are design targets and actual data may vary in the given range.
2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered,
and they are computed in the dynamic IDD_LV and IDD_HV parameters.
3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the
consumption contributors. The tests used in validation, characterization and production are verifying that the total
consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two
parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and
the software profile used.
4. Use case: 1 x e200Z4 @120 MHz, HSM @60 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash
consumption includes parallel read and program/erase, all SARADC in continuous conversion, DMA continuously triggered
by ADC conversion, 2 DSPI / 8 CAN / 2 LINFlex transmitting, RTC and STM running, 1 x EMIOS running (4 channels in
OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not
include I/O toggling, which is highly dependent on the application. Details of the software configuration are available
separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature.
5. Gateway use case: One core running at 120 MHz, HSM 40 MHz, DMA, PLL, FLASH read only 25%, 8xCAN, 1xSARADC.
6. BCM use case: One Core running at 80 MHz, HSM 40 MHz, DMA, PLL, FLASH read only 25%, 1xCAN, 3xSARADC.
7. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code
Book crypto algorithm on 1 block of 16 byte of shared RAM.
8. Flash in Low Power. Sysclk at 120 MHz, HSM 60 MHz, PLL0_PHI at 400 MHz, XTAL at 40 MHz, FIRC 16 MHz ON,
RCOSC1M off. FlexCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON
(configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.
9. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power
down mode.
10. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.
24/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
11. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total
standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size
and temperature.
12. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous
conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the
selected memory size and temperature.
DS11701 Rev 4
25/142
25
Electrical characteristics
4.8
SPC584Bx
I/O pad specification
The following table describes the different pad type configurations.
Table 9. I/O pad specification descriptions
Pad type
Description
Weak configuration
Provides a good compromise between transition time and low electromagnetic emission.
Medium configuration
Strong configuration
Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Provides fast transition speed; used for fast interface.
Very strong
configuration
Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Used for fast interface including Ethernet interface requiring fine control of rising/falling
edge jitter.
Differential
configuration
A few pads provide differential capability providing very fast interface together with good
EMC performances.
Input only pads
Standby pads
Note:
These low input leakage pads are associated with the ADC channels.
These pads (LP pads) are active during STANDBY. They are configured in CMOS level
logic and this configuration cannot be changed. Moreover, when the device enters the
STANDBY mode, the pad-keeper feature is activated for LP pads. It means that:
– if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor
is automatically enabled
– if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor
is automatically enabled.
For the pad-keeper high/low thresholds, consider(VDD_HV_IO_MAIN / 2) +/-20 %.
Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for
each IO segment.
Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY
for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be
configured as CMOS also in running mode in order to prevent device wrong behavior in
STANDBY.
4.8.1
I/O input DC characteristics
The following table provides input DC electrical characteristics, as described in Figure 3.
26/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 3. I/O input electrical characteristics
VIN
VDD
VIH
VHYS
VIL
VINTERNAL
(SIUL register)
Table 10. I/O input electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
TTL
Vihttl
SR
P
Input high level
TTL
—
2
—
VDD_HV_IO
+ 0.3
V
Vilttl
SR
P
Input low level
TTL
—
–0.3
—
0.8
V
Vhysttl
CC
C
Input hysteresis
TTL
—
0.3
—
—
V
CMOS
Vihcmos
SR
P
Input high level
CMOS
—
0.65 * VDD
—
VDD_HV_IO
+ 0.3
V
Vilcmos
SR
P
Input low level
CMOS
—
–0.3
—
0.35 * VDD
V
Vhyscmos
CC
C
Input hysteresis
CMOS
—
0.10 * VDD
—
—
V
COMMON
ILKG
CC
P
Pad input
leakage
INPUT-ONLY pads
TJ = 150 °C
—
—
200
nA
ILKG
CC
P
Pad input
leakage
STRONG pads
TJ = 150 °C
—
—
1,000
nA
ILKG
CC
P
Pad input
leakage
VERY STRONG pads,
TJ = 150 °C
—
—
1,000
nA
DS11701 Rev 4
27/142
36
Electrical characteristics
SPC584Bx
Table 10. I/O input electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
CP1
CC
D
Pad
capacitance
—
—
—
10
pF
Vdrift
CC
D
Input Vil/Vih
temperature
drift
In a 1 ms period, with a
temperature variation
3 V
TJ < 150 °C,
VDD_HV_ADV > 3 V,
V
DD_HV_ADR_S > 3 V
Total unadjusted error
in 12-bit
TJ < 150 °C,
configuration(7)
> 3 V,
V
Unit
Min
Max
–4
4
–6
6
LSB
–6
6
D
High frequency mode,
TJ < 150 °C,
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
–12
12
D
Mode 1, TJ < 150 °C,
VDD_HV_ADV > 3 V
VDD_HV_ADR_S > 3 V
–1.5
1.5
–2.0
2.0
DD_HV_ADV
(12b)
3 V > VDD_HV_ADR_S > 2 V
D
TUE10
CC
C
C
Mode 1, TJ < 150 °C,
VDD_HV_ADV > 3 V,
Total unadjusted error 3 V > V
DD_HV_ADR_S > 2 V
in 10-bit
Mode 2, TJ < 150 °C,
configuration(7)
VDD_HV_ADV > 3 V
VDD_HV_ADR_S > 3 V
Mode 3, TJ < 150 °C,
VDD_HV_ADV > 3 V
VDD_HV_ADR_S > 3 V
DS11701 Rev 4
LSB
(10b)
–3.0
3.0
–4.0
4.0
51/142
55
Electrical characteristics
SPC584Bx
Table 26. SARn ADC electrical specification (continued)
Value
Symbol
TUE12
C
CC
D
Parameter
Differential nonlinearity
CC
T
Unit
Min
Max
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[0:25 mV]
–1
1
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[25:50 mV]
–2
2
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[50:75 mV]
–4
4
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[75:100 mV]
–6
6
–2.5
2.5
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[25:50 mV]
–4
4
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[50:75 mV]
–7
7
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[75:100 mV]
–12
12
Standard frequency mode,
VDD_HV_ADV > 4 V
VDD_HV_ADR_S > 4 V
–1
2
High frequency mode,
VDD_HV_ADV > 4 V
VDD_HV_ADR_S > 4 V
–1
TUE degradation due V
DD_HV_ADV < VIN <
to VDD_HV_ADR offset V
DD_HV_ADR
with respect to
VDD_HV_ADR VDD_HV_ADV
VDD_HV_ADV
[0:25 mV]
P
DNL(8)
Conditions
LSB
(12b)
LSB
(12b)
2
1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing
and calculating the sampling window duration.
2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.
3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.
4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.
5. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven
by the transfer of charge between internal capacitances during the conversion.
6. Current parameter values are for a single ADC.
52/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
7. TUE is granted with injection current within the range defined in Table 25, for parameters classified as T and D.
8. DNL is granted with injection current within the range defined in Table 25, for parameters classified as T and D.
4.12.3
SAR ADC 10 bit electrical specification
The ADC comparators are 10-bit Successive Approximation Register analog-to-digital
converters with full capacitive DAC. The SARn architecture allows input channel
multiplexing.
Note:
The functional operating conditions are given in the DC electrical specifications. Absolute
maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the listed maximum may affect device reliability or cause
permanent damage to the device.
Table 27. ADC-Comparator electrical specification
Value
Symbol
C
P
Parameter
Conditions
SR
tADCINIT
SR
— ADC initialization time
tADCBIASINIT
SR
—
ADC BIAS initialization
time
tADCINITSBY
SR
—
ADC initialization time
in standby
tADCPRECH
SR
T
ADC precharge time
VPRECH
SR
D
Precharge voltage
precision
tADCSAMPLE
SR
P ADC sample time(1)
tADCEVAL
SR
IADCREFH(2),(3)
IADCREFL(4)
IADV_S(4)
CC
CC
CC
T
P
D
T
D
Clock frequency
ADC low reference
current
P V
DD_HV_ADV power
D supply current
7.5
13.33
>13.33
16.0
—
1.5
—
µs
—
5
—
µs
8
—
µs
Fast channel
1/fADCK
—
Standard channel
2/fADCK
—
0
0.25
V
10-bit ADC mode
5/fADCK
—
µs
ADC comparator mode
2/fADCK
—
µs
10-bit ADC mode
10/fADCK
—
ADC comparator mode
2/fADCK
—
Run mode
(average across all codes)
—
7
Power down mode
—
1
ADC comparator mode
—
19.5
Run mode
VDD_HV_ADR_S 5.5 V
—
15
Power Down mode
VDD_HV_ADR_S 5.5 V
—
1
ADC comparator mode
—
20.5
Run mode
—
4
Power down mode
—
0.04
High frequency mode
Standby mode
TJ < 150 °C
ADC evaluation time
ADC high reference
current
Max
Standard frequency mode
fADCK
Unit
Min
DS11701 Rev 4
MHz
µs
µs
µA
µA
mA
53/142
55
Electrical characteristics
SPC584Bx
Table 27. ADC-Comparator electrical specification (continued)
Value
Symbol
TUE10
C
Parameter
Conditions
TJ < 150 °C,
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
–2
2
P
TJ < 150 °C,
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
–3
3
CC
Total unadjusted error
in 10-bit configuration(5) TJ < 150 °C,
VDD_HV_ADV > 3 V,
3 V > VDD_HV_ADR_S > 2 V
54/142
TUE degradation due
to VDD_HV_ADR offset
D
with respect to
VDD_HV_ADV
LSB
–3
3
–3
3
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[0:25 mV]
–1.0
1.0
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[25:50 mV]
–2.0
2.0
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[50:75 mV]
–3.5
3.5
VIN < VDD_HV_ADV
VDD_HV_ADR VDD_HV_ADV
[75:100 mV]
–6.0
6.0
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[0:25 mV]
–2.5
2.5
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[25:50 mV]
–4.0
4.0
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[50:75 mV]
–7.0
7.0
VDD_HV_ADV < VIN <
VDD_HV_ADR
VDD_HV_ADR VDD_HV_ADV
[75:100 mV]
–12.0
12.0
High frequency mode,
TJ < 150 °C,
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
D
CC
Max
T
T
TUE10
Unit
Min
DS11701 Rev 4
(10b)
LSB
(10b)
SPC584Bx
Electrical characteristics
Table 27. ADC-Comparator electrical specification (continued)
Value
Symbol
C
P
DNL(6)
CC
Parameter
Conditions
Standard frequency mode,
VDD_HV_ADV > 4 V
Differential non-linearity VDD_HV_ADR_S > 4 V
std. mode
High frequency mode,
T
VDD_HV_ADV > 4 V
VDD_HV_ADR_S > 4 V
Unit
Min
Max
–1
2
LSB
(10b)
–1
2
1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing
and calculating the sampling window duration.
2. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven
by the transfer of charge between internal capacitances during the conversion.
3. Current parameter values are for a single ADC.
4. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC
and the channel subject to current injection.
5. TUE is granted with injection current within the range defined in Table 25, for parameters classified as T and D.
6. DNL is granted with injection current within the range defined in Table 25, for parameters classified as T and D.
DS11701 Rev 4
55/142
55
Electrical characteristics
4.13
SPC584Bx
Temperature sensor
The following table describes the temperature sensor electrical characteristics.
Table 28. Temperature sensor electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
—
CC
—
Temperature monitoring range
—
–40
—
150
°C
TSENS
CC
T
Sensitivity
—
—
5.18
—
mV/°C
TACC
CC
P
Accuracy
TJ < 150 °C
–3
—
3
°C
56/142
DS11701 Rev 4
SPC584Bx
4.14
Electrical characteristics
LFAST pad electrical characteristics
The LFAST(LVDS Fast Asynchronous Serial Transmission) pad electrical characteristics
apply to high-speed debug serial interfaces on the device.
4.14.1
LFAST interface timing diagrams
Figure 9. LFAST LVDS timing definition
Signal excursions above this level NOT allowed
Max. common mode input at RX
1743 mV
1600 mV
VOD
Max Differential Voltage =
285 mV (LFAST)
PAD_P
Minimum Data Bit Time
Opening =
0.55 * T (LFAST)
VOD
Min Differential
Voltage =
100 mV (LFAST)
“No-Go”
VOS = 1.2 V +/- 10 %
TX common mode
VICOM
PAD_N
PEREYE
PEREYE
Data Bit Period
T = 1 /FDATA
Min. common mode input at RX
Signal excursions below this level NOT allowed
DS11701 Rev 4
150 mV
0V
57/142
62
Electrical characteristics
SPC584Bx
Figure 10. Power-down exit time
H
lfast_pwr_down
L
tPD2NM_TX
Differential
Data Lines
TX
pad_p/pad_n
Data Valid
Figure 11. Rise/fall time
VIH
Differential
Data Lines
TX
|VOD(min)|
|VOD(min)|
pad_p/pad_n
VIL
tTR
tTR
4.14.2
LFAST LVDS interface electrical characteristics
The following table contains the electrical characteristics for the LFAST interface.
Table 29. LVDS pad startup and receiver electrical characteristics(1),(2)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
STARTUP(3),(4)
tSTRT_BIAS
CC T
Bias current reference startup
time(5)
—
—
0.5
4
s
tPD2NM_TX
CC T
Transmitter startup time (power
down to normal mode)(6)
—
—
0.4
2.75
s
58/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Table 29. LVDS pad startup and receiver electrical characteristics(1),(2) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
tSM2NM_TX
CC T
Transmitter startup time (sleep
mode to normal mode)(7)
Not applicable to the
MSC/DSPI LVDS pad
—
0.4
0.6
µs
tPD2NM_RX
CC T
Receiver startup time (power
down to normal mode)(8)
—
—
20
40
ns
tPD2SM_RX
CC T
Receiver startup time (power
down to sleep mode)(9)
Not applicable to the
MSC/DSPI LVDS pad
—
20
50
ns
ILVDS_BIAS
CC D LVDS bias current consumption
Tx or Rx enabled
—
—
0.95
mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Z0
SR D
Transmission line characteristic
impedance
—
47.5
50
52.5
ZDIFF
SR D
Transmission line differential
impedance
—
95
100
105
(10)
—
1.6(11)
V
RECEIVER
0.15
VICOM
SR T
Common mode voltage
—
|VI|
SR T
Differential input voltage(12)
—
100
—
—
mV
VHYS
CC T
Input hysteresis
—
25
—
—
mV
RIN
CC D
Terminating resistance
VDD_HV_IO = 5.0 V ±
10 %
-40 °C < TJ< 150 °C
80
—
150
VDD_HV_IO = 3.3 V ±
10 %
-40 °C < TJ < 150 °C
80
—
175
—
—
3.5
6.0
pF
CIN
CC D Differential input capacitance(13)
ILVDS_RX
CC C
Receiver DC current
consumption
Enabled
—
—
1.6
mA
IPIN_RX
CC D
Maximum consumption on
receiver input pin
VI = 400 mV,
RIN = 80
—
—
5
mA
1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug
(HSD) LVDS pad.
2. All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.
3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS
control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD
modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for
MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding
SIUL2 MSCR ODC field.
4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter
electrical characteristic tables.
5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled.
6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock periods.
7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode.
DS11701 Rev 4
59/142
62
Electrical characteristics
SPC584Bx
8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.
9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode.
10. Absolute min = 0.15 V – (285 mV/2) = 0 V
11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V
12. Value valid for LFAST mode. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure
proper LFAST receive timing.
13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.
Table 30. LFAST transmitter electrical characteristics(1),(2),(3)
Value
Symbol
fDATA
SR
VOS
C
Parameter
D
Conditions
Unit
Min
Typ
Max
Data rate
—
—
—
320
Mbps
CC P
Common mode voltage
—
1.08
—
1.32
V
|VOD|
CC P
Differential output voltage swing
(terminated)(4),(5)
—
110
—
285
mV
tTR
CC T
Rise time from -|VOD(min)| to
+|VOD(min)|. Fall time from
+|VOD(min)| to -|VOD(min)|
—
0.26
—
1.25
ns
CL
SR
External lumped differential load
capacitance(4)
VDD_HV_IO = 4.5 V
—
—
6.0
VDD_HV_IO = 3.0 V
—
—
4.0
—
3.6
mA
2.85
mA
D
ILVDS_TX
CC C
Transmitter DC current consumption
Enabled
—
IPIN_TX
CC D
Transmitter DC current sourced through
output pin
—
1.1
1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101).
2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
values shown in Figure 12.
3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.
4. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 12.
5. Valid for maximum external load CL.
60/142
DS11701 Rev 4
pF
SPC584Bx
Electrical characteristics
Figure 12. LVDS pad external load diagram
Die
PCB
Package
GPIO Driver
CL
1pF
2.5pF
100
terminator
LVDS Driver
GPIO Driver
CL
1pF
2.5pF
4.14.3
LFAST PLL electrical characteristics
The following table contains the electrical characteristics for the LFAST PLL.
Table 31. LFAST PLL electrical characteristics(1)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
fRF_REF
SR D PLL reference clock frequency (CLKIN)
—
10(2)
—
30
MHz
ERRREF
CC D
—
-1
—
1
%
—
30
—
70
%
DCREF
PLL reference clock frequency error
CC D PLL reference clock duty cycle (CLKIN)
PN
CC D
Integrated phase noise
(single side band)
fRF_REF = 20 MHz
—
—
-58
dBc
fVCO
CC P
PLL VCO frequency
—
312
—
320(3)
MHz
—
150(4)
µs
tLOCK
CC D
PLL phase lock
—
DS11701 Rev 4
—
61/142
62
Electrical characteristics
SPC584Bx
Table 31. LFAST PLL electrical characteristics(1) (continued)
Value
Symbol
C
Parameter
Conditions
T
PERREF SR
Input reference clock jitter (peak to peak)
T
PEREYE CC T
Unit
Min
Typ
Max
Single period,
fRF_REF = 20 MHz
—
—
350
ps
Long term,
fRF_REF = 20 MHz
-500
—
500
ps
—
—
—
400
ps
Output Eye Jitter (peak to peak)(5)
1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.
3. The 320 MHz frequency is achieved with a 20 MHz reference clock.
4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device (to set the PLL enable bit).
5. Measured at the transmitter output across a 100 termination resistor on a device evaluation board. See Figure 12.
62/142
DS11701 Rev 4
SPC584Bx
4.15
Electrical characteristics
Power management
The power management module monitors the different power supplies as well as it
generates the required internal supplies. The device can operate in the following
configurations:
Table 32. Power management regulators
Device
External
regulator
Internal
SMPS
regulator
SPC584Bx
—
—
Internal
linear
regulator
external
ballast
Internal
linear
regulator
internal
ballast
Auxiliary
regulator
Clamp
regulator
Internal
standby
regulator(1)
X(2)
X
X
X
X
1. Standby regulator is automatically activated when the device enters standby mode.
2. For compatibility purpose with SPC584Cx/SPC58ECx, or for the optimization of the power dissipation, the operability of the
device with external ballast can be used. The external ballast option is available only on specific devices, contact the local
sales.
4.15.1
Power management integration
Use the integration schemes provided below to ensure the proper device function,
according to the selected regulator configuration.
The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate
VDD_LV supply.
Place capacitances on the board as near as possible to the associated pins and limit the
serial inductance of the board to less than 5 nH.
It is recommended to use the internal regulators only to supply the device itself.
DS11701 Rev 4
63/142
72
Electrical characteristics
SPC584Bx
Figure 13. Internal regulator with external ballast mode
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9''B+9
&(
966
%&75/
9''B+9B)/$
&%
9''B+9B,2
4(;7
&%9
9''B+9B,2
&+9Q
0DLQ5HJ
966
9''B/9
$X[5HJ
&/9Q
966
&ODPS5HJ
966B+9B$'9
&$'&
64/142
DS11701 Rev 4
9''B+9B$'9
SPC584Bx
Electrical characteristics
Figure 14. Internal regulator with internal ballast mode
&)/$
&(
966
9''B+9B,2
%&75/
9''B+9B)/$
&%9
9''B+9B,2
0DLQ5HJ
9''B/9
&/9Q
966
&+9Q
$X[5HJ
966
&ODPS5HJ
966B+9B$'9
9''B+9B$'9
&$'&
DS11701 Rev 4
65/142
72
Electrical characteristics
SPC584Bx
Figure 15. Standby regulator with external ballast mode
&)/$
9''B+9
&%9
&(
966
9''B+9B,2
%&75/
&%
9''B+9B)/$
4(;7
9''B+9B,2
&+9Q
6WDQGE\UHJ
9''B/9
&/9Q
966
966B+9B$'9
9''B+9B$'9
&$'&
66/142
DS11701 Rev 4
966
SPC584Bx
Electrical characteristics
Figure 16. Standby regulator with internal ballast mode
&)/$
&(
966
9''B+9B,2
9''B+9B)/$
&%9
9''B+9B,2
&+9Q
6WDQGE\ 5HJ
9''B/9
966
&/9Q
966
966B+9B$'9
9''B+9B$'9
&$'&
Table 33. External components integration
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
—
1.1
2.2
3.0
Total resistance including
board track
—
—
50
m
Each VDD_LV/VSS pair
—
47
—
nF
Common Components
CE
SR
D
Internal voltage regulator stability
external capacitance(2) (3)
RE
SR
D
Stability capacitor equivalent
serial resistance
CLVn
SR
Internal voltage regulator
D decoupling external
capacitance(3) (4) (5)
RLVn
SR
D
Stability capacitor equivalent
serial resistance
—
—
—
50
m
CBV
SR
D Bulk capacitance for HV supply(3)
on one VDD_HV_IO_MAIN/
VSS pair
—
4.7
—
µF
CHVn
SR
D
on all VDD_HV_IO/VSS and
VDD_HV_ADR/VSS pairs
—
100
—
nF
Decoupling capacitance for
ballast and IOs(3)
DS11701 Rev 4
µF
67/142
72
Electrical characteristics
SPC584Bx
Table 33. External components integration (continued)
Symbol
C
Value
Conditions(1)
Parameter
CFLA
SR
D
Decoupling capacitance for Flash
supply(6)
CADC
SR
D
ADC supply external
capacitance(2)
Unit
Min
Typ
Max
—
—
10
—
nF
VDD_HV_ADV/VSS_HV_ADV
pair.
—
1
—
µF
2.0
—
HV_IO
Internal Linear Regulator with External Ballast Mode
QEXT
SR
D
Recommended external NPN
transistors
VQ
SR
D
External NPN transistor collector
voltage
—
NJD2873T4, BCP68
VDD_
V
_MAIN
CB
SR
Internal voltage regulator stability
D external capacitance on ballast
base(4) (7)
—
—
2.2
—
µF
RB
SR
D
Stability capacitor equivalent
serial resistance
Total resistance including
board track
—
—
50
m
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TJ = –40 / 150 °C, unless otherwise specified.
2. Recommended X7R or X5R ceramic –50 % / +35 % variation across process, temperature, voltage and after aging.
3. CE capacitance is required both in internal and external regulator mode.
4. For noise filtering, add a high frequency bypass capacitance of 10 nF.
5. For applications it is recommended to implement at least 5 CLV capacitances.
6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF.
7. CB capacitance is required if only the external ballast is implemented.
68/142
DS11701 Rev 4
SPC584Bx
4.15.2
Electrical characteristics
Voltage regulators
Table 34. Linear regulator specifications
Value
Symbol
C
Parameter
Conditions
CC P
Main regulator output voltage
VMREG
CC P
Typ
Max
Power-up, before
trimming, no load
1.14
1.22
1.30
After trimming,
maximum load
1.09
1.19
1.24
—
—
325
—
—
450
—
—
150
mA
-100
—
100
mA
IMREG = max
—
—
17
IMREG = 0 mA
—
—
—
Main regulator current provided to Internal ballast
VDD_LV domain
T The maximum current supported
is the sum of the Main Regulator External ballast
and the Auxiliary Regulator
maximum current both regulators
are working in parallel.
IDDMREG
CC
IDDCLAMP
Main regulator rush current
sinked from VDD_HV_IO_MAIN
CC D
domain during VDD_LV domain
loading
IDDMREG
CC
T
IMREGINT
CC
D Main regulator current
D consumption
Main regulator output current
variation
Unit
Min
Power-up condition
20 µs observation
window
V
mA
mA
Table 35. Auxiliary regulator specifications
Value
Symbol
C
Parameter
Conditions
VAUX
CC
P Aux regulator output voltage
IDDAUX
CC
T
IDDAUX
CC
T Aux regulator current variation
IAUXINT
CC
D Aux regulator current
D consumption
Unit
Min
Typ
Max
After trimming, internal
regulator mode
1.09
1.19
1.22
V
—
—
—
150
mA
-100
—
100
mA
IMREG = max
—
—
1.1
IMREG = 0 mA
—
—
1.1
Aux regulator current provided to
VDD_LV domain
20 µs observation
window
DS11701 Rev 4
mA
69/142
72
Electrical characteristics
SPC584Bx
Table 36. Clamp regulator specifications
Value
Symbol
VCLAMP
C
Parameter
Conditions
CC P Clamp regulator output voltage
IDDCLAMP CC T Clamp regulator current variation
ICLAMPINT
CC D
Clamp regulator current
consumption
Unit
Min
Typ
Max
After trimming, internal
regulator mode
1.18
1.22
1.33
V
20 µs observation
window
-100
—
100
mA
—
—
0.7
mA
IMREG = 0 mA
Table 37. Standby regulator specifications
Value
Symbol
VSBY
IDDSBY
4.15.3
C
Parameter
Conditions
CC P Standby regulator output voltage
CC T
Standby regulator current
provided to VDD_LV domain
Unit
Min
Typ
Max
After trimming,
maximum load
1.02
1.06
1.26
External Ballast
—
—
50
Internal Ballast
—
—
10
V
mA
Voltage monitors
The monitors and their associated levels for the device are given in Table 38. Figure 17
illustrates the workings of voltage monitoring threshold.
70/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 17. Voltage monitor threshold definition
VDD_xxx
VHVD
VLVD
TVMFILTER
TVMFILTER
HVD TRIGGER
(INTERNAL)
TVMFILTER
TVMFILTER
LVD TRIGGER
(INTERNAL)
Table 38. Voltage monitor electrical characteristics
Symbol
C
Supply/Parameter(1)
Value(2)
Conditions
Unit
Min
Typ
Max
1.80
2.18
2.40
V
PowerOn Reset HV
VPOR200_C
CC P VDD_HV_IO_MAIN
—
Minimum Voltage Detectors HV
VMVD270_C
CC P VDD_HV_IO_MAIN
—
2.71
2.76
2.80
V
VMVD270_F
CC P VDD_HV_FLA
—
2.71
2.76
2.80
V
CC P VDD_HV_IO_MAIN (in Standby)
—
2.71
2.76
2.80
V
VMVD270_SBY
Low Voltage Detectors HV
VLVD290_C
CC P VDD_HV_IO_MAIN
—
2.89
2.94
2.99
V
VLVD290_F
CC P VDD_HV_FLA
—
2.89
2.94
2.99
V
VLVD290_AS
CC P VDD_HV_ADV (ADCSAR pad)
—
2.89
2.94
2.99
V
VLVD290_IF
CC P VDD_HV_IO_ETH
—
2.89
2.94
2.99
V
VLVD400_AS
CC P VDD_HV_ADV (ADCSAR pad)
—
4.15
4.23
4.31
V
DS11701 Rev 4
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72
Electrical characteristics
SPC584Bx
Table 38. Voltage monitor electrical characteristics (continued)
Symbol
C
Supply/Parameter(1)
Value(2)
Conditions
Unit
Min
Typ
Max
VLVD400_IM
CC P VDD_HV_IO_MAIN
—
4.15
4.23
4.31
V
VLVD400_IF
CC P VDD_HV_IO_ETH
—
4.15
4.23
4.31
V
3.68
3.75
3.82
V
High Voltage Detectors HV
VHVD400_IF
CC P VDD_HV_IO_ETH
—
Upper Voltage Detectors HV
VUVD600_F
CC P VDD_HV_FLA
—
5.72
5.82
5.92
V
VUVD600_IF
CC P VDD_HV_IO_ETH
—
5.72
5.82
5.92
V
—
0.29
0.60
0.97
V
PowerOn Reset LV
VPOR031_C
CC P VDD_LV
Minimum Voltage Detectors LV
VMVD082_C
CC P VDD_LV
—
0.85
0.88
0.91
V
VMVD094_C
CC P VDD_LV
—
0.98
1.00
1.02
V
VMVD094_FA
CC P VDD_LV (Flash)
—
1.00
1.02
1.04
V
VMVD094_FB
CC P VDD_LV (Flash)
—
1.00
1.02
1.04
V
Low Voltage Detectors LV
VLVD100_C
CC P VDD_LV
—
1.06
1.08
1.11
V
VLVD100_SB
CC P VDD_LV (In Standby)
—
0.99
1.01
1.03
V
VLVD100_F
CC P VDD_LV (Flash)
—
1.08
1.10
1.12
V
1.28
1.31
1.33
V
High Voltage Detectors LV
VHVD134_C
CC P VDD_LV
—
Upper Voltage Detectors LV
VUVD140_C
CC P VDD_LV
—
1.34
1.37
1.39
V
VUVD140_F
CC P VDD_LV (Flash)
—
1.34
1.37
1.39
V
—
5
—
25
s
Common
TVMFILTER
CC D Voltage monitor filter(3)
1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative
condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with
minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented.
For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing
the limitations provided in Section 4.2: Absolute maximum ratings.
2. The values reported are Trimmed values, where applicable.
3. See Figure 17. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be
delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to
temperature, process and voltage variations.
72/142
DS11701 Rev 4
SPC584Bx
4.16
Electrical characteristics
Flash
The following table shows the Wait state configuration.
Table 39. Wait state configuration
APC
RWSC
Frequency range (MHz)
0
f < 30
1
f < 60
2
f < 90
3
f < 120
0
f < 30
1
f < 60
2
f < 90
3
f < 120
2
55 f < 80
3
55f < 120
000(1)
100(2)
001(3)
1. STD pipelined, no address anticipation.
2. No pipeline (STD + 1 Tck).
3. Pipeline with 1 Tck address anticipation.
The following table shows the Program/Erase characteristics.
Table 40. Flash memory program and erase specifications
Value
Symbol
Characteristics(1)(2)
Lifetime
Initial max
Typ(3) C
(6)
All
temp
C
25 °C
(7)
Typical
end of
life(4)
max(5)
Unit
C
< 1 K < 250 K
cycles cycles
tdwprogram
Double Word (64 bits)
program time [Packaged part]
43
C
130
—
—
140
500
C
µs
tpprogram
Page (256 bits) program time
72
C
240
—
—
240
1000
C
µs
tpprogrameep
Page (256 bits) program time
Data Flash - EEPROM
(partition 1) [Packaged part]
83
C
264
—
—
276
1000
C
µs
Quad Page (1024 bits)
program time
220
C
1040
1200
P
850
2000
C
µs
Quad Page (1024 bits)
program time Data Flash EEPROM (partition 1)
[Packaged part]
245
C
1140
1320
P
978
2000
C
µs
tqprogram
tqprogrameep
DS11701 Rev 4
73/142
76
Electrical characteristics
SPC584Bx
Table 40. Flash memory program and erase specifications (continued)
Value
Symbol
Characteristics
Lifetime
Initial max
(1)(2)
Typ(3) C
(6)
All
temp
C
25 °C
(7)
Typical
end of
life(4)
max(5)
Unit
C
< 1 K < 250 K
cycles cycles
t16kpperase
16 KB block pre-program and
erase time
190
C
450
500
P
220
1000
—
C ms
t32kpperase
32 KB block pre-program and
erase time
250
C
520
600
P
290
1200
—
C ms
t64kpperase
64 KB block pre-program and
erase time
360
C
700
750
P
420
1600
—
C ms
t128kpperase
128 KB block pre-program
and erase time
600
C
1300
1600
P
800
4000
—
C ms
t256kpperase
256 KB block pre-program
and erase time
1050
C
1800
2400
P
1600
4000
—
C ms
t16kprogram
16 KB block program time
25
C
45
50
P
40
1000
—
C ms
t32kprogram
32 KB block program time
50
C
90
100
P
75
1200
—
C ms
t64kprogram
64 KB block program time
100
C
175
200
P
150
1600
—
C ms
t128kprogram
128 KB block program time
200
C
350
430
P
300
2000
—
C ms
t256kprogram
256 KB block program time
400
C
700
850
P
590
4000
—
C ms
30
C
52
58
P
64
1750
C ms
220
C
495
550
P
400
3600
C ms
Program 16 KB HSM Data
t16kprogrameep Flash - EEPROM (partition 1)
[Packaged part]
30
C
52
58
P
64
1750
C ms
Erase 16 KB HSM Data Flash
- EEPROM (partition 1)
[Packaged part]
220
C
495
550
P
400
3600
C ms
tprr
Program rate(8)
2.2
C
2.8
3.40
C
2.4
—
C
s/M
B
tpr
Erase rate(8)
4.8
C
7.2
9.6
C
6.4
—
C
s/M
B
ttprfm
Program rate Factory Mode(8)
1.12
C
1.4
1.6
C
—
—
C
s/M
B
terfm
Erase rate Factory Mode(8)
4.0
C
5.2
5.8
C
—
—
C
s/M
B
Full flash programming time(9)
3.45
C
6.0
7.3
P
5.1
C
s
Program 16 KB Data Flash t16kprogrameep EEPROM (partition 1)
[Packaged part]
t16keraseeep
t16keraseeep
tffprogram
74/142
Erase 16 KB Data Flash EEPROM (partition 1)
[Packaged part]
DS11701 Rev 4
—
—
SPC584Bx
Electrical characteristics
Table 40. Flash memory program and erase specifications (continued)
Value
Symbol
Characteristics
Lifetime
Initial max
(1)(2)
Typ(3) C
(6)
All
temp
C
25 °C
(7)
Typical
end of
life(4)
max(5)
Unit
C
< 1 K < 250 K
cycles cycles
tfferase
Full flash erasing time(9)
9.9
C
18.1
23.3
P
14.3
tESRT
Erase suspend request
rate(10)
200
T
—
—
—
—
—
— µs
tPSRT
Program suspend request
rate(10)
30
T
—
—
—
—
—
— µs
tAMRT
Array Integrity Check - Margin
Read suspend request rate
15
T
—
—
—
—
—
— µs
tPSUS
Program suspend latency(11)
—
—
—
—
—
—
12
T
µs
—
—
—
—
—
—
22
T
µs
latency(11)
—
—
C
s
tESUS
Erase suspend
tAIC0S
Array Integrity Check (2.0 MB,
sequential)(12)
12.8
T
—
—
—
—
—
—
— ms
Array Integrity Check (256
KB, sequential)(12)
1.5
T
—
—
—
—
—
—
— ms
tAIC0P
Array Integrity Check (2.0 MB,
proprietary)(12)
4.0
T
—
—
—
—
—
—
—
tMR0S
Margin Read (2.0 MB,
sequential)(12)
35
T
—
—
—
—
—
—
— ms
tMR256KS
Margin Read (256 KB,
sequential)(12)
4.0
T
—
—
—
—
—
—
— ms
tAIC256KS
s
1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.
2. Actual hardware operation times; this does not include software overhead.
3. Typical program and erase times assume nominal supply values and operation at 25 °C.
4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but
not tested.
5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5 %) supply
voltages.
7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5 %) supply
voltages.
8. Rate computed based on 256 KB sectors.
9. Only code sectors, not including EEPROM.
10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.
11. Timings guaranteed by design.
12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the
table is calculated at max frequency.
DS11701 Rev 4
75/142
76
Electrical characteristics
SPC584Bx
All the Flash operations require the presence of the system clock for internal
synchronization. About 50 synchronization cycles are needed: this means that the timings of
the previous table can be longer if a low frequency system clock is used.
Table 41. Flash memory life specification
Symbol
Value
Characteristics(1) (2)
Unit
Min
C
Typ
C
NCER16K
16 KB CODE Flash endurance
10
—
100
— Kcycles
NCER32K
32 KB CODE Flash endurance
10
—
100
— Kcycles
NCER64K
64 KB CODE Flash endurance
10
—
100
— Kcycles
1
—
100
— Kcycles
1
—
100
— Kcycles
10
—
100
— Kcycles
NCER128K 128 KB CODE Flash endurance
NCER256K
256 KB CODE Flash endurance
256 KB CODE Flash endurance
(3)
NDER16K
16 KB DATA EEPROM Flash endurance
250
—
—
— Kcycles
NDER16K
16 KB HSM DATA EEPROM Flash endurance
100
—
—
— Kcycles
tDR1k
Minimum data retention Blocks with 0 - 1,000 P/E
cycles
25
—
—
—
Years
tDR10k
Minimum data retention Blocks with 1,001 - 10,000
P/E cycles
20
—
—
—
Years
tDR100k
Minimum data retention Blocks with 10,001 - 100,000
P/E cycles
15
—
—
—
Years
tDR250k
Minimum data retention Blocks with 100,001 250,000 P/E cycles
10
—
—
—
Years
1. Program and erase cycles supported across specified temperature specifications.
2. It is recommended that the application enables the core cache memory.
3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time
are possible.
76/142
DS11701 Rev 4
SPC584Bx
4.17
Electrical characteristics
AC specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
4.17.1
Debug and calibration interface timing
4.17.1.1
JTAG interface timing
Table 42. JTAG pin AC electrical characteristics
Value(1),(2)
#
Symbol
C
Characteristic
Unit
Min
Max
1
tJCYC
CC D TCK cycle time
100
—
ns
2
tJDC
CC T TCK clock pulse width
40
60
%
3
tTCKRISE
CC D TCK rise and fall times (40 %–70 %)
—
3
ns
4
tTMSS, tTDIS
CC D TMS, TDI data setup time
5
—
ns
5
tTMSH, tTDIH
CC D TMS, TDI data hold time
5
—
ns
ns
6
tTDOV
CC D TCK low to TDO data valid
—
15(3)
7
tTDOI
CC D TCK low to TDO data invalid
0
—
ns
8
tTDOHZ
CC D TCK low to TDO high impedance
—
15
ns
9
tJCMPPW
CC D JCOMP assertion time
100
—
ns
10
tJCMPS
CC D JCOMP setup time to TCK low
40
—
ns
ns
11
tBSDV
CC D TCK falling edge to output valid
—
600(4)
12
tBSDVZ
CC D TCK falling edge to output valid out of high impedance
—
600
ns
13
tBSDHZ
CC D TCK falling edge to output high impedance
—
600
ns
14
tBSDST
CC D Boundary scan input valid to TCK rising edge
15
—
ns
15
tBSDHT
CC D TCK rising edge to boundary scan input invalid
15
—
ns
1. These specifications apply to JTAG boundary scan only. See Table 43 for functional specifications.
2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the
datasheet.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
DS11701 Rev 4
77/142
101
Electrical characteristics
SPC584Bx
Figure 18. JTAG test clock input timing
TCK
2
3
2
1
3
Figure 19. JTAG test access port timing
TCK
4
5
TMS, TDI
6
8
7
TDO
78/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 20. JTAG JCOMP timing
TCK
10
JCOMP
9
Figure 21. JTAG boundary scan timing
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
DS11701 Rev 4
79/142
101
Electrical characteristics
4.17.1.2
SPC584Bx
Nexus interface timing
Table 43. Nexus debug port timing
Value(1)
#
Symbol
C
Characteristic
7
tEVTIPW
8
tEVTOPW CC D EVTO pulse width
tTCYC
Max
4
—
tCYC(2)
40
CC D EVTI pulse width
—
ns
(3),(4)
—
tCYC(2)
Absolute minimum TCK cycle time(5)
CC D (TDO sampled on posedge of TCK)
40(6)
—
Absolute minimum TCK cycle time(7)
(TDO sampled on negedge of TCK)
(6)
TCK cycle time
9
Unit
Min
2
ns
20
—
11
tNTDIS
CC D TDI data setup time
5
—
ns
12
tNTDIH
CC D TDI data hold time
5
—
ns
13
tNTMSS
CC D TMS data setup time
5
—
ns
14
tNTMSH
CC D TMS data hold time
5
—
ns
15
—
CC D TDO propagation delay from falling edge of TCK(8)
—
16
ns
16
—
CC D
2.25
—
ns
TDO hold time with respect to TCK falling edge
(minimum TDO propagation delay)
1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.
6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
7. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge.
8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
80/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 22. Nexus output timing
1
2
MCKO
3
4
6
MDO
MSEO
EVTO
Output Data Valid
Figure 23. Nexus event trigger and test clock timings
TCK
EVTI
EVTO
9
TCK
EVTI
EVTO
9
DS11701 Rev 4
7
7
8
8
81/142
101
Electrical characteristics
SPC584Bx
Figure 24. Nexus TDI, TMS, TDO timing
TCK
11
13
12
14
TMS, TDI
15
16
TDO
4.17.1.3
External interrupt timing (IRQ pin)
Table 44. External interrupt timing
Characteristic
Symbol
Min
Max
Unit
IRQ Pulse Width Low
tIPWL
3
—
tcyc
IRQ Pulse Width High
tIPWH
3
—
tcyc
tICYC
6
—
tcyc
IRQ Edge to Edge
Time(1)
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
82/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 25. External interrupt timing
IRQ
2
1
3
Figure 26. External interrupt timing
D_CLKOUT
4
IRQ
2
1
3
4.17.2
DSPI timing with CMOS pads
DSPI channel frequency support is shown in Table 45.
Timing specifications are shown in the tables below.
DS11701 Rev 4
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101
Electrical characteristics
SPC584Bx
Table 45. DSPI channel frequency support
Max usable
frequency
(MHz)(2),(3)
DSPI use mode(1)
Full duplex – Classic timing (Table 46)
Full duplex – Modified timing (Table 47)
CMOS (Master
mode)
DSPI_0, DSPI_1,
DSPI_2, DSPI_3,
DSPI_5, DSPI_6,
10
DSPI_4
17
DSPI_0, DSPI_1,
DSPI_2, DSPI_3,
DSPI_5, DSPI_6,
10
DSPI_4
30
DSPI_0, DSPI_1,
Output only mode (SCK/SOUT/PCS) (Table 46 and DSPI_2, DSPI_3,
DSPI_5, DSPI_6,
Table 47)
Output only mode TSB mode (SCK/SOUT/PCS)
10
DSPI_4
30
DSPI_0, DSPI_1,
DSPI_2, DSPI_3,
DSPI_5, DSPI_6,
10
DSPI_4
30
CMOS (Slave mode Full duplex) (Table 48)
—
16
1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file
attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum
performance with every possible combination of pins.
2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
3. Maximum usable frequency does not take into account external device propagation delay.
4.17.2.1
DSPI master mode full duplex timing with CMOS pads
4.17.2.1.1 DSPI CMOS master mode – classic timing
Note:
In the following table, all output timing is worst case and includes the mismatching of rise
and fall times of the output pads.
Table 46. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1
Value(1)
Condition
#
Symbol
C
Characteristic
Unit
Pad drive(2)
Load (CL)
Min
Max
SCK drive strength
1
tSCK
84/142
CC D SCK cycle time
Very strong
25 pF
59.0
—
Strong
50 pF
80.0
—
Medium
50 pF
200.0
—
DS11701 Rev 4
ns
SPC584Bx
Electrical characteristics
Table 46. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1 (continued)
Value(1)
Condition
#
Symbol
C
Characteristic
Unit
Pad drive(2)
Load (CL)
Min
Max
SCK and PCS drive strength
2
tCSC
CC D
PCS to SCK
delay
Very strong
25 pF
(N(3) × tSYS(4)) –
16
—
Strong
50 pF
(N(3) × tSYS(4)) –
16
—
Medium
50 pF
(N(3) × tSYS(4)) –
16
—
PCS medium
and SCK
strong
PCS = 50 pF
SCK = 50 pF
(N(3) × tSYS(4)) –
29
—
ns
SCK and PCS drive strength
3
tASC
Very strong
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) –
35
—
Strong
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) –
35
—
Medium
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) –
35
—
PCS medium
and SCK
strong
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) –
35
—
CC D After SCK delay
ns
SCK drive strength
4
tSDC
CC D
SCK duty
cycle(6)
Very strong
Strong
Medium
0 pF
1/
0 pF
1/
0 pF
1/
2tSCK
2tSCK
2tSCK
–2
1/
2tSCK
+2
–2
1/
2tSCK
+2
–5
1/
2tSCK
+5
ns
PCS strobe timing
5
tPCSC
CC D
PCSx to PCSS
time(7)
PCS and PCSS drive strength
6
tPASC
CC D
PCSS to PCSx
time(7)
PCS and PCSS drive strength
Strong
25 pF
Strong
16.0
—
ns
16.0
—
ns
25 pF
25.0
—
50 pF
31.0
—
50 pF
52.0
—
25 pF
SIN setup time
SCK drive strength
7
tSUI
CC D
SIN setup time to Very strong
SCK(8)
Strong
Medium
DS11701 Rev 4
ns
85/142
101
Electrical characteristics
SPC584Bx
Table 46. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1 (continued)
Value(1)
Condition
#
Symbol
C
Characteristic
Unit
Pad drive(2)
Load (CL)
Min
Max
SIN hold time
SCK drive strength
8
tHI
CC D
SIN hold time
from SCK(8)
Very strong
0 pF
–1.0
—
Strong
0 pF
–1.0
—
Medium
0 pF
–1.0
—
25 pF
—
7.0
50 pF
—
8.0
50 pF
—
16.0
25 pF
–7.7
—
50 pF
–11.0
—
50 pF
–15.0
—
ns
SOUT data valid time (after SCK edge)
SOUT and SCK drive strength
9
tSUO
CC D
SOUT data valid Very strong
time from SCK(9) Strong
Medium
ns
SOUT data hold time (after SCK edge)
SOUT and SCK drive strength
10
tHO
CC D
SOUT data hold Very strong
time after SCK(9) Strong
Medium
ns
1. All timing values for output signals in this table are measured to 50 % of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS =10 ns).
5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7. PCSx and PCSS using same pad configuration.
8. Input timing assumes an input slew rate of 1 ns (10 % – 90 %) and uses TTL voltage thresholds.
9. SOUT Data valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
86/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 27. DSPI CMOS master mode — classic timing, CPHA = 0
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSDC
tSUI
tHI
First Data
SIN
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 28. DSPI CMOS master mode — classic timing, CPHA = 1
3&6[
6&.2XWSXW
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6&.2XWSXW
&3 2/
W68,
6,1
W+,
)LUVW'DWD
'DWD
W682
6287
)LUVW'DWD
DS11701 Rev 4
'DWD
/DVW'DWD
W+2
/DVW'DWD
87/142
101
Electrical characteristics
SPC584Bx
Figure 29. DSPI PCS strobe (PCSS) timing (master mode)
tPCSC
tPASC
PCSS
PCSx
4.17.2.1.2 DSPI CMOS master mode — modified timing
Note:
In the following table, all output timing is worst case and includes the mismatching of rise
and fall times of the output pads.
Table 47. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1
Value(1)
Condition
#
Symbol
C
Characteristic
Pad drive(2)
Unit
Load (CL)
Min
Max
SCK drive strength
1
tSCK
CC D SCK cycle time
Very strong
25 pF
33.0
—
Strong
50 pF
80.0
—
Medium
50 pF
200.0
—
ns
SCK and PCS drive
strength
2
tCSC
CC D
PCS to SCK
delay
Very strong
25 pF
(N(3) × tSYS(4)) – 16
—
Strong
50 pF
(N(3) × tSYS(4)) – 16
—
Medium
50 pF
PCS
PCS = 50 pF
medium and
SCK = 50 pF
SCK strong
(3)
(4)
× tSYS ) – 16
—
(N(3) × tSYS(4)) – 29
—
(N
ns
SCK and PCS drive
strength
3
tASC
88/142
CC D After SCK delay
Very strong
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) – 35
—
Strong
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) – 35
—
Medium
PCS = 0 pF
SCK = 50 pF
(M(5) × tSYS(4)) – 35
—
PCS
PCS = 0 pF
medium and
SCK = 50 pF
SCK strong
(M(5) × tSYS(4)) – 35
—
DS11701 Rev 4
ns
SPC584Bx
Electrical characteristics
Table 47. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1 (continued)
Value(1)
Condition
#
Symbol
C
Characteristic
Pad drive(2)
Unit
Load (CL)
Min
Max
SCK drive strength
4
tSDC
CC D SCK duty cycle(6)
Very strong
Strong
Medium
0 pF
1
1
/2tSCK + 2
0 pF
1
1
/2tSCK + 2
0 pF
1
1
/2tSCK + 5
/2tSCK – 2
/2tSCK – 2
/2tSCK – 5
ns
PCS strobe timing
5
6
tPCSC CC D
PCSx to PCSS
time(7)
PCSS to PCSx
tPASC CC D
time(7)
PCS and PCSS drive
strength
Strong
25 pF
16.0
—
ns
16.0
—
ns
PCS and PCSS drive
strength
Strong
25 pF
SIN setup time
SCK drive strength
SIN setup time to Very strong
SCK
Strong
CPHA = 0(8)
7
tSUI
Medium
CC D
25 pF
50 pF
50 pF
25 – (P(9) × tSYS(4))
—
× tSYS )
—
(P(9)
tSYS(4))
—
31 – (P
52 –
(4)
(9)
×
ns
SCK drive strength
SIN setup time to Very strong
SCK
Strong
CPHA = 1(8)
Medium
25 pF
25.0
—
50 pF
31.0
—
50 pF
52.0
—
ns
SIN hold time
SCK drive strength
SIN hold time
from SCK
CPHA = 0(8)
8
tHI
CC D
Very strong
0 pF
–1 + (P(9) × tSYS(3))
(9)
(3)
—
Strong
0 pF
–1 + (P
× tSYS )
—
Medium
0 pF
–1 + (P(9) × tSYS(3))
—
ns
SCK drive strength
SIN hold time
from SCK
CPHA = 1(8)
Very strong
0 pF
–1.0
—
Strong
0 pF
–1.0
—
Medium
0 pF
–1.0
—
DS11701 Rev 4
ns
89/142
101
Electrical characteristics
SPC584Bx
Table 47. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1 (continued)
Value(1)
Condition
#
Symbol
C
Characteristic
Pad drive(2)
Unit
Load (CL)
Min
Max
SOUT data valid time (after SCK edge)
SOUT data valid
time from SCK
CPHA = 0, (10)
9
tSUO
SOUT and SCK drive
strength
Very strong
25 pF
—
7.0 + tSYS(4)
Strong
50 pF
—
8.0 + tSYS(4)
—
tSYS(4)
Medium
CC D
SOUT data valid
time from SCK
CPHA = 1(10)
50 pF
16.0 +
ns
SOUT and SCK drive
strength
Very strong
25 pF
—
7.0
Strong
50 pF
—
8.0
Medium
50 pF
—
16.0
25 pF
–7.7 + tSYS(4)
—
50 pF
–11.0 +
tSYS(4)
—
–15.0 +
tSYS(4)
—
ns
SOUT data hold time (after SCK edge)
SOUT data hold
time after SCK
CPHA = 0(10)
10
tHO
SOUT and SCK drive
strength
Very strong
Strong
Medium
CC D
SOUT data hold
time after SCK
CPHA = 1(10)
50 pF
ns
SOUT and SCK drive
strength
Very strong
25 pF
–7.7
—
Strong
50 pF
–11.0
—
Medium
50 pF
–15.0
—
ns
1. All timing values for output signals in this table are measured to 50 % of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7. PCSx and PCSS using same pad configuration.
8. Input timing assumes an input slew rate of 1 ns (10 % – 90 %) and uses TTL voltage thresholds.
9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_
MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1.
90/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
10. SOUT Data valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
Figure 30. DSPI CMOS master mode — modified timing, CPHA = 0
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 31. DSPI CMOS master mode — modified timing, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
tHI
Data
First Data
tSUO
SOUT
First Data
DS11701 Rev 4
Data
Last Data
tHO
Last Data
91/142
101
Electrical characteristics
SPC584Bx
Figure 32. DSPI PCS strobe (PCSS) timing (master mode)
tPCSC
tPASC
PCSS
PCSx
4.17.2.2
Slave mode timing
Table 48. DSPI CMOS slave timing — full duplex — normal and modified transfer formats
(MTFE = 0/1)
Condition
#
1
Symbol
tSCK
CC
C
D
Characteristic
SCK Cycle Time(1)
Pad Drive
Load
Min
Max
Unit
—
—
62
—
ns
Delay(1)
—
—
16
—
ns
2
tCSC
SR
D
SS to SCK
3
tASC
SR
D
SCK to SS Delay(1)
—
—
16
—
ns
4
tSDC
CC
D
SCK Duty Cycle(1)
—
—
30
—
ns
Very
strong
25 pF
—
50
ns
Strong
50 pF
—
50
ns
Medium
50 pF
—
60
ns
Slave SOUT Disable Time(1)
Very
strong
25 pF
—
5
ns
(SS inactive to SOUT HighZ or invalid)
Strong
50 pF
—
5
ns
Medium
50 pF
—
10
ns
5
6
tA
tDIS
CC
CC
D
D
(1) (2) (3)
Slave Access Time
(SS active to SOUT driven)
(2) (3)
9
tSUI
CC
D
Data Setup Time for
Inputs(1)
—
—
10
—
ns
10
tHI
CC
D
Data Hold Time for Inputs(1)
—
—
10
—
ns
Very
strong
25 pF
—
30
ns
Strong
50 pF
—
30
ns
Medium
50 pF
—
50
ns
Very
strong
25 pF
2.5
—
ns
Strong
50 pF
2.5
—
ns
Medium
50 pF
2.5
—
ns
11
12
tSUO
tHO
CC
CC
D
D
SOUT Valid Time(1) (2) (3)
(after SCK edge)
SOUT Hold Time
(after SCK edge)
(1) (2) (3)
1. Input timing assumes an input slew rate of 1 ns (10 % - 90 %) and uses TTL voltage thresholds.
2. All timing values for output signals in this table, are measured to 50 % of the output voltage.
3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
92/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Figure 33. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0
tASC
tCSC
SS
tSCK
SCK Input
(CPOL = 0)
tSDC
tSDC
SCK Input
(CPOL = 1)
tSUO
tA
First Data
SOUT
Data
tDIS
Last Data
tSUI
tHI
Data
First Data
SIN
tHO
Last Data
Figure 34. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
tSUO
tA
SOUT
tHO
First Data
tSUI
SIN
4.17.3
Data
Last Data
Data
Last Data
tDIS
tHI
First Data
Ethernet timing
The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be
configured for either CMOS or TTL signal levels compatible with devices operating at either
5.0 V or 3.3 V. Check the device pinout details to review the packages supporting MII and
RMII.
DS11701 Rev 4
93/142
101
Electrical characteristics
4.17.3.1
SPC584Bx
MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1 %.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the RX_CLK frequency.
Note:
In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the
valid input levels, 0.8 V and 2.0 V.
Table 49. MII receive signal timing
Value
Symbol
C
Characteristic
Unit
Min
Max
M1
CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup
5
—
ns
M2
CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold
5
—
ns
M3
CC D RX_CLK pulse width high
35 %
65 %
RX_CLK period
M4
CC D RX_CLK pulse width low
35 %
65 %
RX_CLK period
Figure 35. MII receive signal timing diagram
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
4.17.3.2
M2
MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1 %.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
option allows the use of non-compliant MII PHYs.
Refer to the SPC584Bx 32-bit Power Architecture microcontroller reference manual’s
Ethernet chapter for details of this option and how to enable it.
Note:
94/142
In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the
valid output levels, 0.8 V and 2.0 V.
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Table 50. MII transmit signal timing
Value(1)
Symbol
C
Characteristic
Unit
Min
Max
M5
CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
—
ns
M6
CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
M7
CC D TX_CLK pulse width high
35 %
65 %
TX_CLK period
M8
CC D TX_CLK pulse width low
35 %
65 %
TX_CLK period
1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance
is accounted for, and does not need to be subtracted from the 25 pF value
Figure 36. MII transmit signal timing diagram
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
4.17.3.3
MII async inputs signal timing (CRS and COL)
Table 51. MII async inputs signal timing
Value
Symbol
M9
C
Characteristic
Unit
CC D CRS, COL minimum pulse width
Min
Max
1.5
—
TX_CLK period
Figure 37. MII async inputs timing diagram
CRS, COL
M9
DS11701 Rev 4
95/142
101
Electrical characteristics
4.17.3.4
SPC584Bx
MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.
Figure 38. MII serial management channel timing diagram
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
4.17.3.5
M13
MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.
Note:
In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)
to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is
referenced from MDC = 50 % to 2.2 V/3.5 V input and output levels.
Table 52. MII serial management channel timing
Value
Symbol
C
Characteristic
Unit
Min
Max
M10
CC D
MDC falling edge to MDIO output invalid
(minimum propagation delay)
0
—
ns
M11
CC D
MDC falling edge to MDIO output valid
(maximum propagation delay)
—
25
ns
M12
CC D MDIO (input) to MDC rising edge setup
10
—
ns
M13
CC D MDIO (input) to MDC rising edge hold
0
—
ns
M14
CC D MDC pulse width high
40 %
60 %
MDC period
M15
CC D MDC pulse width low
40 %
60 %
MDC period
96/142
DS11701 Rev 4
SPC584Bx
Note:
Electrical characteristics
In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)
to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is
referenced from MDC = 50 % to 2.2 V/3.5 V input and output levels.
Table 53. RMII serial management channel timing
Value
Symbol
C
Characteristic
Unit
Min
Max
M10
CC D
MDC falling edge to MDIO output invalid
(minimum propagation delay)
0
—
ns
M11
CC D
MDC falling edge to MDIO output valid
(maximum propagation delay)
—
25
ns
M12
CC D MDIO (input) to MDC rising edge setup
10
—
ns
M13
CC D MDIO (input) to MDC rising edge hold
0
—
ns
M14
CC D MDC pulse width high
40 %
60 %
MDC period
M15
CC D MDC pulse width low
40 %
60 %
MDC period
Figure 39. MII serial management channel timing diagram
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
4.17.3.6
M13
RMII receive signal timing (RXD[1:0], CRS_DV)
The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1 %.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.
DS11701 Rev 4
97/142
101
Electrical characteristics
Note:
SPC584Bx
In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the
valid input levels, 0.8 V and 2.0 V.
Table 54. RMII receive signal timing
Value
Symbol
C
Characteristic
Unit
Min
Max
R1
CC D RXD[1:0], CRS_DV to REF_CLK setup
4
—
ns
R2
CC D REF_CLK to RXD[1:0], CRS_DV hold
2
—
ns
R3
CC D REF_CLK pulse width high
35 %
65 %
REF_CLK period
R4
CC D REF_CLK pulse width low
35 %
65 %
REF_CLK period
Figure 40. RMII receive signal timing diagram
R3
REF_CLK (input)
R4
RXD[1:0] (inputs)
CRS_DV
R1
4.17.3.7
R2
RMII transmit signal timing (TXD[1:0], TX_EN)
The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1 %.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK
frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the
rising or falling edge of REF_CLK, and the timing is the same in either case. This option
allows the use of non-compliant RMII PHYs.
Note:
In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the
valid output levels, 0.8 V and 2.0 V.
RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on
the pad as 1ns.
98/142
DS11701 Rev 4
SPC584Bx
Electrical characteristics
Table 55. RMII transmit signal timing
Value
Symbol
C
Characteristic
Unit
Min
Max
R5
CC D REF_CLK to TXD[1:0], TX_EN invalid
2
—
ns
R6
CC D REF_CLK to TXD[1:0], TX_EN valid
—
14
ns
R7
CC D REF_CLK pulse width high
35 %
65 %
REF_CLK period
R8
CC D REF_CLK pulse width low
35 %
65 %
REF_CLK period
Figure 41. RMII transmit signal timing diagram
R7
REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN
R6
4.17.4
CAN timing
The following table describes the CAN timing.
Table 56. CAN timing
Value
Symbol
tP(RX:TX)
tPLP(RX:TX)
C
CC
D
CC
D
CC
D
CC
D
CC
D
CC
D
CC
D
CC
D
Parameter
CAN
controller
propagation
delay time
standard
pads
CAN
controller
propagation
delay time
low power
pads
Condition
Unit
Min
Typ
Max
Medium type pads 25 pF load
—
—
70
Medium type pads 50 pF load
—
—
80
STRONG, VERY STRONG type pads
25 pF load
—
—
60
STRONG, VERY STRONG type pads
50 pF load
—
—
65
Medium type pads 25 pF load
—
—
90
Medium type pads 50 pF load
—
—
100
STRONG, VERY STRONG type pads
25 pF load
—
—
80
STRONG, VERY STRONG type pads
50 pF load
—
—
85
DS11701 Rev 4
ns
ns
99/142
101
Electrical characteristics
4.17.5
SPC584Bx
UART timing
UART channel frequency support is shown in the following table.
Table 57. UART frequency support
LINFlexD clock
frequency LIN_CLK
(MHz)
Oversampling rate
16
6
4
16
13.33
16
20
6.25
3:1 majority voting
8
6
12.5
16.67
Limited voting on one
sample with configurable
sampling point
5
4
4.17.6
10
Limited voting on one
sample with configurable
sampling point
5
100
5
3:1 majority voting
8
80
Max usable frequency
(Mbaud)
Voting scheme
20
25
I2C timing
The I2C AC timing specifications are provided in the following tables.
Note:
In the following table, I2C input timing is valid for Automotive and TTL inputs levels,
hysteresis enabled, and an input edge rate no slower than 1 ns (10 % – 90 %).
Table 58. I2C input timing specifications – SCL and SDA
Value
No. Symbol C
Parameter
Unit
Min
Max
1
—
CC
D Start condition hold time
2
—
PER_CLK
Cycle(1)
2
—
CC
D Clock low time
8
—
PER_CLK Cycle
3
—
CC
D Bus free time between Start and Stop condition
4.7
—
µs
4
—
CC
D Data hold time
0.0
—
ns
5
—
CC
D Clock high time
4
—
PER_CLK Cycle
6
—
CC
D Data setup time
0.0
—
ns
7
—
CC
D Start condition setup time (for repeated start condition only)
2
—
PER_CLK Cycle
8
—
CC
D Stop condition setup time
2
—
PER_CLK Cycle
1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.
Note:
100/142
In the following table:
DS11701 Rev 4
SPC584Bx
Electrical characteristics
•
All output timing is worst case and includes the mismatching of rise and fall times of the
output pads.
•
Output parameters are valid for CL = 25 pF, where CL is the external load to the device
(lumped). The internal package capacitance is accounted for, and does not need to be
subtracted from the 25 pF value.
•
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may
reduce operating speeds and may cause incorrect operation.
•
Programming the IBFD register (I2C bus Frequency Divider) with the maximum
frequency results in the minimum output timings listed. The I2C interface is designed to scale
the data transition time, moving it to the middle of the SCL low period. The actual position is
affected by the pre-scale and division values programmed in the IBC field of the IBFD
register.
Table 59. I2C output timing specifications — SCL and SDA
Value
No. Symbol C
Parameter
Unit
Min
Max
1
—
CC
D Start condition hold time
6
—
PER_CLK
Cycle(1)
2
—
CC
D Clock low time
10
—
PER_CLK Cycle
3
—
CC
D Bus free time between Start and Stop condition
4.7
—
µs
4
—
CC
D Data hold time
7
—
PER_CLK Cycle
5
—
CC
D Clock high time
10
—
PER_CLK Cycle
6
—
CC
D Data setup time
2
—
PER_CLK Cycle
7
—
CC
D Start condition setup time (for repeated start condition only)
20
—
PER_CLK Cycle
8
—
CC
D Stop condition setup time
10
—
PER_CLK Cycle
1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.
Figure 42. I2C input/output timing
2
5
SCL
1
4
8
6
7
3
SDA
DS11701 Rev 4
101/142
101
Package information
5
SPC584Bx
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
The following table lists the case numbers for SPC584Bx.
Table 60. Package case numbers
5.1
Package type
Device type
eTQFP64
Production
eTQFP100
Production
eTQFP144
Production
eLQFP176
Production
eTQFP64 package information
Refer to Section 5.1.1: Package mechanical drawings and data information for full
description of below figures and table notes.
102/142
DS11701 Rev 4
SPC584Bx
Package information
Figure 43. eTQFP64 package outline
OLIHDXJPHQWHG
DS11701 Rev 4
103/142
122
Package information
SPC584Bx
Figure 44. eTQFP64 section A-A
ș
ș
ș
ș
Figure 45. eTQFP64 section B-B
104/142
DS11701 Rev 4
SPC584Bx
Package information
Table 61. eTQFP64 package mechanical data
Dimensions(7),(17)
Symbol
Min.
Typ.
Max.
0°
3.5°
7°
1
0°
—
—
2
10°
12°
14°
3
10°
12°
14°
(15)
—
—
1.20
(12)
A1
0.05
—
0.15
A2(15)
0.95
1.00
1.05
0.17
0.22
0.27
A
(8),(9),(11)
b
(11)
0.17
0.20
0.23
c(11)
0.09
—
0.20
c1(11)
0.09
—
0.16
b1
D(4)
D1
12 BSC
(2),(5)
D2
(13)
D3(14)
10 BSC
—
—
5.85
4.10
—
—
e
0.50 BSC
(4)
12 BSC
E
E1(2),(5)
E2(13)
10 BSC
—
—
5.85
(14)
4.10
—
—
L
0.45
0.60
0.75
E3
L1
1 REF
N(16)
64
R1
0.08
—
—
R2
0.08
—
0.20
S
0.20
—
—
aaa(1),(18)
0.20
(1),(18)
0.20
(1),(18)
ccc
0.08
ddd(1),(18)
0.08
bbb
DS11701 Rev 4
105/142
122
Package information
5.1.1
SPC584Bx
Package mechanical drawings and data information
The following notes are related to Figure 43, Figure 44, Figure 45 and Table 61:
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All dimensions are in millimeter except where explicitly noted.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself. Type of exposed pad on SPC584Bx(variable) is as Figure 46.
End user should verify D2 and E2 dimensions according to the specific device
application.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the max number of terminal positions for the specified body size.
17. Critical dimensions:
a)
Stand-Off
b)
Overall Width
c)
Lead Coplanarity
18. For symbols, recommended values and tolerances, see Table 62.
19. Notch may be present in this area (MAX 1.5mm square) if center top gate molding
technology is applied. Resin gate residual not protruding out of package top surface.
106/142
DS11701 Rev 4
SPC584Bx
Package information
Figure 46. eTQFP64 leadframe pad design
Note: number, dimensions and positions of grooves are for reference only.
Table 62. eTQFP64 symbol definitions
5.2
Symbol
Definition
Notes
aaa
The tolerance that controls the position of
the terminal pattern with respect to Datum A
and B. The center of the tolerance zone for
each terminal is defined by basic dimension
e as related to Datum A and B.
For flange-molded packages, this tolerance
also applies for basic dimensions D1 and
E1. For packages tooled with intentional
terminal tip protrusions, aaa does not apply
to those protrusions.
bbb
The bilateral profile tolerance that controls
the position of the plastic body sides. The
centers of the profile zones are defined by
the basic dimensions D and E.
ccc
The unilateral tolerance located above the
This tolerance is commonly know as the
seating plane where in the bottom surface of
“coplanarity” of the package terminals.
all terminals must be located.
ddd
The tolerance that controls the position of
the terminals to each other. The centers of
the profile zones are defined by basic
dimension e.
—
This tolerance is normally compounded with
tolerance zone defined by “b”.
eTQFP100 package information
Refer to Section 5.2.1: Package mechanical drawings and data information for full
description of below figures and table notes.
DS11701 Rev 4
107/142
122
Package information
SPC584Bx
Figure 47. eTQFP100 package outline
OLIHDXJPHQWHG
108/142
DS11701 Rev 4
SPC584Bx
Package information
Figure 48. eTQFP100 section A-A
ș
ș
ș
ș
Figure 49. eTQFP100 section B-B
DS11701 Rev 4
109/142
122
Package information
SPC584Bx
Table 63. eTQFP100 package mechanical data
Dimensions(7),(17)
Symbol
Min.
Typ.
Max.
0
3.5
7
1
0
—
—
2
10
12
14
3
10
12
14
A(15)
—
—
1.20
(12)
A1
0.05
—
0.15
A2(15)
0.95
1.00
1.05
0.17
0.22
0.27
(8),(9),(11)
b
(11)
0.17
0.20
0.23
c(11)
0.09
—
0.20
c1(11)
0.09
—
0.16
b1
D(4)
16.00 BSC
(2),(5)
14.00 BSC
D1
D2
(13)
D3(14)
—
—
6.77
5.10
—
—
e
0.50 BSC
(4)
16.00 BSC
E
E1(2),(5)
E2(13)
—
—
6.77
(14)
5.10
—
—
L
0.45
0.60
0.75
E3
L1
1.00 REF
N(16)
100
R1
0.08
—
—
R2
0.08
—
0.20
S
0.20
—
—
aaa(1),(18)
0.20
(1),(18)
0.20
(1),(18)
ccc
0.08
ddd(1),(18)
0.08
bbb
110/142
14.00 BSC
DS11701 Rev 4
SPC584Bx
5.2.1
Package information
Package mechanical drawings and data information
The following notes are related to Figure 47, Figure 48, Figure 49 and Table 63:
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All dimensions are in millimeter except where explicitly noted.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself. Type of exposed pad on SPC584Bx is as Figure 50. End user
should verify D2 and E2 dimensions according to the specific device application.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the max number of terminal positions for the specified body size.
17. Critical dimensions:
a)
Stand-Off
b)
Overall Width
c)
Lead Coplanarity
18. For symbols, recommended values and tolerances, see Table 64.
DS11701 Rev 4
111/142
122
Package information
SPC584Bx
Figure 50. eTQFP100 leadframe pad design
Note: number, dimensions and positions of grooves are for reference only.
Table 64. eTQFP100 symbol definitions
Symbol
Definition
Notes
aaa
The tolerance that controls the position of the
terminal pattern with respect to Datum A and B. The
center of the tolerance zone for each terminal is
defined by basic dimension e as related to Datum A
and B.
For flange-molded packages, this tolerance also
applies for basic dimensions D1 and E1. For
packages tooled with intentional terminal tip
protrusions, aaa does not apply to those
protrusions.
bbb
The bilateral profile tolerance that controls the
position of the plastic body sides. The centers of the
profile zones are defined by the basic dimensions D
and E.
—
ccc
The unilateral tolerance located above the seating
plane where in the bottom surface of all terminals
must be located.
This tolerance is commonly know as the
“coplanarity” of the package terminals.
ddd
The tolerance that controls the position of the
terminals to each other. The centers of the profile
zones are defined by basic dimension e.
This tolerance is normally compounded with
tolerance zone defined by “b”.
5.3
eTQFP144 package information
Refer to Section 5.3.1: Package mechanical drawings and data information for full
description of below figures and table notes.
112/142
DS11701 Rev 4
SPC584Bx
Package information
Figure 51. eTQFP144 package outline
OLIHDXJPHQWHG
DS11701 Rev 4
113/142
122
Package information
SPC584Bx
Figure 52. eTQFP144 section A-A
ș
ș
ș
ș
Figure 53. eTQFP144 section B-B
114/142
DS11701 Rev 4
SPC584Bx
Package information
Table 65. eTQFP144 package mechanical data
Dimensions(7),(17)
Symbol
Min.
Typ.
Max.
0.0°
3.5°
7.0°
1
0.0°
—
—
2
10.0°
12.0°
14.0°
3
10.0°
12.0°
14.0°
(15)
—
—
1.20
(12)
A1
0.05
—
0.15
A2(15)
0.95
1.00
1.05
0.17
0.22
0.27
A
(8),(9),(11)
b
(11)
0.17
0.20
0.23
c(11)
0.09
—
0.20
c1(11)
0.09
—
0.16
D(4)
b1
—
22.00 BSC
—
(2),(5)
—
20.00 BSC
—
(13)
—
—
6.77
5.10
—
—
—
22.00 BSC
—
D1
D2
D3(14)
(4)
E
(2),(5)
—
20.00 BSC
—
E2(13)
—
—
6.77
E3(14)
5.10
—
—
E1
e
0.50 BSC
L
0.45
0.60
0.75
L1
—
1.00 REF
—
N(16)
144
R1
0.08
—
—
R2
0.08
—
0.20
S
0.20
—
—
aaa(1),(18)
0.20
(1),(18)
0.20
(1),(18)
ccc
0.08
ddd(1),(18)
0.08
bbb
DS11701 Rev 4
115/142
122
Package information
5.3.1
SPC584Bx
Package mechanical drawings and data information
The following notes are related to Figure 51, Figure 52, Figure 53 and Table 65:
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All dimensions are in millimeter except where explicitly noted.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself. Type of exposed pad on SPC584Bx is as Figure 54. End user
should verify D2 and E2 dimensions according to the specific device application.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the max number of terminal positions for the specified body size.
17. Critical dimensions:
a)
Stand-Off
b)
Overall Width
c)
Lead Coplanarity
18. For symbols, recommended values and tolerances, see Table 66.
116/142
DS11701 Rev 4
SPC584Bx
Package information
Figure 54. eTQFP144 leadframe pad design
Note: number, dimensions and positions of grooves are for reference only.
Table 66. eTQFP144 symbol definitions
Symbol
Definition
Notes
aaa
The tolerance that controls the position of the
terminal pattern with respect to Datum A and B. The
center of the tolerance zone for each terminal is
defined by basic dimension e as related to Datum A
and B.
For flange-molded packages, this tolerance also
applies for basic dimensions D1 and E1. For
packages tooled with intentional terminal tip
protrusions, aaa does not apply to those
protrusions.
bbb
The bilateral profile tolerance that controls the
position of the plastic body sides. The centers of the
profile zones are defined by the basic dimensions D
and E.
—
ccc
The unilateral tolerance located above the seating
plane where in the bottom surface of all terminals
must be located.
This tolerance is commonly know as the
“coplanarity” of the package terminals.
ddd
The tolerance that controls the position of the
terminals to each other. The centers of the profile
zones are defined by basic dimension e.
This tolerance is normally compounded with
tolerance zone defined by “b”.
5.4
eLQFP176 package information
Refer to Section 5.4.1: Package mechanical drawings and data information for full
description of below figures and table notes.
DS11701 Rev 4
117/142
122
Package information
SPC584Bx
Figure 55. eLQFP176 package outline
OLIHDXJPHQWHG
118/142
DS11701 Rev 4
SPC584Bx
Package information
Figure 56. eLQFP176 section A-A
ș
ș
ș
ș
Figure 57. eLQFP176 section B-B
DS11701 Rev 4
119/142
122
Package information
SPC584Bx
Table 67. eLQFP176 package mechanical data
Dimensions(7),(17)
Symbol
Min.
Nom.
Max.
0°
3.5°
7°
1
0°
—
—
2
10°
12°
14°
3
10°
12°
14°
(15)
—
—
1.60
(12)
A1
0.05
—
0.15
A2(15)
1.35
1.40
1.45
0.17
0.22
0.27
A
(8),(9),(11)
b
(11)
0.17
0.20
0.23
c(11)
0.09
—
0.20
c1(11)
0.09
—
0.16
b1
D(4)
26.00 BSC
(2),(5)
24.00 BSC
D1
D2
(13)
D3(14)
—
—
7.77
6.10
—
—
e
0.50 BSC
(4)
26.00 BSC
E
E1(2),(5)
E2(13)
—
—
7.77
(14)
6.10
—
—
L
0.45
0.60
0.75
E3
L1
1.00 REF
N(16)
176
R1
0.08
—
—
R2
0.08
—
0.20
S
0.20
—
aaa(1),(18)
0.20
(1),(18)
0.20
(1),(18)
0.08
ddd(1),(18)
0.08
bbb
ccc
120/142
24.00 BSC
DS11701 Rev 4
SPC584Bx
5.4.1
Package information
Package mechanical drawings and data information
The following notes are related to Figure 55, Figure 56, Figure 57 and Table 67:
1.
Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2.
The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3.
Datums A-B and D to be determined at datum plane H.
4.
To be determined at seating datum plane C.
5.
Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6.
Details of pin 1 identifier are optional but must be located within the zone indicated.
7.
All dimensions are in millimeter except where explicitly noted.
8.
No intrusion allowed inwards the leads.
9.
Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself. Type of exposed pad on SPC584Bx is as Figure 58. End user
should verify D2 and E2 dimensions according to the specific device application.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the max number of terminal positions for the specified body size.
17. Critical dimensions:
a)
Stand-Off
b)
Overall Width
c)
Lead Coplanarity
18. For symbols, recommended values and tolerances, see Table 68.
DS11701 Rev 4
121/142
122
Package information
SPC584Bx
Figure 58. eLQFP176 leadframe pad design
Note: number, dimensions and positions of grooves are for reference only.
Table 68. eLQFP176 symbol definitions
122/142
Symbol
Definition
Notes
aaa
The tolerance that controls the position of
the terminal pattern with respect to Datum A
and B. The center of the tolerance zone for
each terminal is defined by basic dimension
e as related to Datum A and B.
For flange-molded packages, this tolerance
also applies for basic dimensions D1 and
E1. For packages tooled with intentional
terminal tip protrusions, aaa does not apply
to those protrusions.
bbb
The bilateral profile tolerance that controls
the position of the plastic body sides. The
centers of the profile zones are defined by
the basic dimensions D and E.
ccc
The unilateral tolerance located above the
This tolerance is commonly know as the
seating plane where in the bottom surface of
“coplanarity” of the package terminals.
all terminals must be located.
ddd
The tolerance that controls the position of
the terminals to each other. The centers of
the profile zones are defined by basic
dimension e.
DS11701 Rev 4
—
This tolerance is normally compounded with
tolerance zone defined by “b”.
SPC584Bx
5.5
Package information
Package thermal characteristics
The following tables describe the thermal characteristics of the device. The parameters in
this chapter have been evaluated by considering the device consumption configuration
reported in the Section 4.7: Device consumption.
5.5.1
eTQFP64
Table 69. Thermal characteristics for 64 exposed pad eTQFP package
Symbol
Parameter(1)
C
Conditions
Value
Unit
Four layer board (2s2p)
30.8
°C/W
RJA
CC
D Junction-to-Ambient, Natural Convection(2)
RJMA
CC
D
Junction-to-Moving-Air, Ambient(2)
at 200 ft./min., four layer
board (2s2p)
24.4
°C/W
RJB
CC
D
Junction-to-board(3)
—
12.1
°C/W
RJCtop
CC
D
Junction-to-case top(4)
—
15.2
°C/W
—
4.5
°C/W
Natural convection
3.7
°C/W
RJCbottom
JT
CC
CC
D
Junction-to-case
bottom(5)
(6)
D
Junction-to-package top
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.5.2
eTQFP100
Table 70. Thermal characteristics for 100 exposed pad eTQFP package
Symbol
C
Parameter(1)
(2)
Conditions
Value
Unit
Four layer board (2s2p)
28.9
°C/W
RJA
CC
D Junction-to-Ambient, Natural Convection
RJMA
CC
D
Junction-to-Moving-Air, Ambient(2)
At 200 ft./min., four layer
board (2s2p)
22.9
°C/W
RJB
CC
D
Junction-to-board(3)
—
14.1
°C/W
—
14
°C/W
—
4.4
°C/W
Natural convection
3.7
°C/W
RJCtop
RJCbottom
JT
CC
CC
CC
D
D
D
Junction-to-case top
Junction-to-case
(4)
bottom(5)
Junction-to-package
top(6)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
DS11701 Rev 4
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127
Package information
SPC584Bx
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.5.3
eTQFP144
Table 71. Thermal characteristics for 144 exposed pad eTQFP package
Symbol
C
Parameter(1)
Conditions
Value
Unit
Four layer board (2s2p)
28.5
°C/W
RJA
CC
D Junction-to-Ambient, Natural Convection(2)
RJMA
CC
D
Junction-to-Moving-Air, Ambient(2)
At 200 ft./min., four layer
board (2s2p)
22.1
°C/W
RJB
CC
D
Junction-to-board(3)
—
14.5
°C/W
RJCtop
CC
D
Junction-to-case top(4)
—
13.7
°C/W
—
4.4
°C/W
Natural convection
3.7
°C/W
RJCbottom
JT
CC
CC
D
D
Junction-to-case
bottom(5)
Junction-to-package
top(6)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.5.4
LQFP176
Table 72. Thermal characteristics for 176 exposed pad LQFP package
Symbol
C
Parameter(1)
RJA
CC
D Junction-to-Ambient, Natural Convection
RJMA
CC
D
Junction-to-Moving-Air, Ambient(2)
RJB
CC
D
Junction-to-board(3)
RJCtop
RJCbottom
JT
CC
CC
CC
D
D
D
Junction-to-case top
Junction-to-case
(2)
Value
Unit
Four layer board (2s2p)
28
°C/W
at 200 ft./min., four layer
board (2s2p)
21
°C/W
15.7
°C/W
18.1
°C/W
—
4.0
°C/W
Natural convection
3.7
°C/W
(4)
bottom(5)
Junction-to-package
Conditions
top(6)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
124/142
DS11701 Rev 4
SPC584Bx
Package information
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.5.5
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
Equation 1
TJ = TA + (RJA * PD)
where:
TA = ambient temperature for the package (°C)
RJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The differences between the
values determined for the single-layer (1s) board compared to a four-layer board that has
two signal layers, a power and a ground plane (2s2p), demonstrate that the effective
thermal resistance is not a constant. The thermal resistance depends on the:
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leaves
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:
DS11701 Rev 4
125/142
127
Package information
SPC584Bx
Equation 2
TJ = TB + (RJB * PD)
where:
TB = board temperature for the package perimeter (°C)
RJB = junction-to-board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:
Equation 3
RJA = RJC + RCA
where:
RJA = junction-to-ambient thermal resistance (°C/W)
RJC = junction-to-case thermal resistance (°C/W)
RCA = case to ambient thermal resistance (°C/W)
RJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RCA. For example, change
the air flow around the device, add a heat sink, change the mounting arrangement on the
printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case
thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (JT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:
Equation 4
TJ = TT + (JT x PD)
where:
TT = thermocouple temperature on top of the package (°C)
JT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
126/142
DS11701 Rev 4
SPC584Bx
Package information
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1
mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (JPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:
Equation 5
TJ = TB + (JPB x PD)
where:
TT = thermocouple temperature on bottom of the package (°C)
JT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
DS11701 Rev 4
127/142
127
Ordering information
6
SPC584Bx
Ordering information
Figure 59. Ordering information scheme
Example code:
SPC58
4
B
70
E7
C
M
Product identifier Core Product Memory Package Frequency/ Custom
Tempertaure version
F
0
Security Silicon
revision
X
Packing
Y = Tray
X = Tape and Reel (pin 1 top right)
0 = 1st production version
1 = 2nd production version
0 = No security
C = Security HW (HSM)
0 = 4x std CAN
D = 4x ISO CAN FD
G = 8x std CAN
H = 8x ISO CAN FD
E = 8x std CAN / Ethernet
M = 8x ISO CAN FD / Ethernet
B = 64 MHz at 105 °C
C = 80 MHz at 105 °C
E = 120 MHz at 105 °C
L = 64 MHz at 125 °C
M = 80 MHz at 125 °C
N = 120 MHz at 125 °C
E7 = eLQFP176
E5 = eTQFP144
E3 = eTQFP100
E1 = eTQFP64
70 = 2 MB
64 = 1.5 MB
60 = 1 MB
B = SPC584Bx line
4 = Single computing e200z4 core
SPC58 = Power Architecture in 40 nm
Note:
Contact your ST sales office to ask for the availability of a particular commercial product.
Features (for instance, flash, RAM or peripherals) not included in the commercial product
cannot be used.
ST cannot be called to take any liability for features used outside the commercial product.
128/142
DS11701 Rev 4
SPC584Bx
Ordering information
Table 73. Code Flash options
SPC584B70
(2M)
SPC584B64
(1.5M)
SPC584B60
(1M)
Partition
Start address
End address
16
16
16
0
0x00FC0000
0x00FC3FFF
16
16
16
0
0x00FC4000
0x00FC7FFF
32
32
32
0
0x00FC8000
0x00FCFFFF
32
32
32
0
0x00FD0000
0x00FD7FFF
32
32
32
0
0x00FD8000
0x00FDFFFF
128
128
128
0
0x00FE0000
0x00FFFFFF
256
256
256
0
0x01000000
0x0103FFFF
256
256
256
0
0x01040000
0x0107FFFF
256
256
256
0
0x01080000
0x010BFFFF
256
256
NA
0
0x010C0000
0x010FFFFF
256
256
NA
0
0x01100000
0x0113FFFF
256
NA
NA
0
0x01140000
0x0117FFFF
256
NA
NA
0
0x01180000
0x011BFFFF
Table 74. RAM options
SPC584B70
SPC584B64
SPC584B60
192(1)
160(1)
128(1)
8
8
24
Type
Start address
End address
8
PRAMC_2
(STBY)
0x400A8000
0x400A9FFF
24
24
PRAMC_2
(STBY)
0x400AA000
0x400AFFFF
32
32
32
PRAMC_2
(STBY)
0x400B0000
0x400B7FFF
32
32
NA
PRAMC_2
(STBY)
0x400B8000
0x400BFFFF
32
NA
NA
PRAMC_2
(STBY)
0x400C0000
0x400C7FFF
64
64
64
D-MEM
CPU_2
0x52800000
0x5280FFFF
1. RAM size is the sum of TCM and SRAM
DS11701 Rev 4
129/142
129
Revision history
7
SPC584Bx
Revision history
Table 75. Document revision history
Date
Revision
06-Oct-2016
1
Changes
Initial version.
Changed Microsoft Excel® workbook attached to this document (was
SPC584Bx_IO_Definition_v1.xlsx dated July 26, 2016).
For details, refer to the sheet Revision History of the attached file
“SPC584Bx_IO_Definition_v2.xlsx”.
Section 3.2: Absolute maximum ratings:
Table 4: Absolute maximum ratings: For parameter “IINJ”, text “DC” removed
from description.
Section 3.3: Operating conditions:
Table 5: Operating conditions:
– Footnote “1.260 V - 1.290 V range .. temperature profile” updated to Text “...
average supply value below or equal to 1.236 V ...”
– In parameter “IINJ1” description, text “DC” removed.
13-Dec-2016
2
Section 3.7: Device consumption:
Table 8: Device consumption:
– For parameter “IDDSSWU1”, typical value updated from “TBD” to “1 mA”
– For parameter “IDDSSWU1”, description updated to “SSWU running
over...ADC off”
– For parameter “IDDSSWU2”, typical value updated from “TBD” to “3.5 mA”
– For parameter “IDDSSWU2”, description updated to “SSWU running
over...ADC on”
– For parameter “IDDSTOP”, typical value updated from “TBD” to “18” for TJ=25
°C
– For parameter “IDDSTDBY8”, typical value updated from “TBD” to “85” for
TJ=25 °C
– For parameter “IDDSTDBY32”, typical value updated from “TBD” to “100” for
TJ=25 °C
– For parameter “IDDSTDBY128”, typical value updated from “TBD” to “160” for
TJ=25 °C
Section 3.8: I/O pad specification:
Section 3.8.2: I/O output DC characteristics:
– Updated “WEAK” to “WEAK/SLOW”
– Updated “STRONG” to “STRONG/FAST”
– Updated “VERY STRONG” to “VERY STRONG / VERY FAST”
Table 9: I/O pad specification descriptions:
– Added “Standby Pads”
Added footnote “Logic level is configurable in running mode while it is
CMOS...”
130/142
DS11701 Rev 4
SPC584Bx
Revision history
Table 75. Document revision history (continued)
Date
Revision
Changes
Table 12: WEAK/SLOW I/O output characteristics: Added “10%-90% in
description of parameter “tTR_W”.
Table 13: MEDIUM I/O output characteristics: Added “10%-90% in description
of parameter “tTR_M”.
Table 14: STRONG/FAST I/O output characteristics: Added “10%-90% in
description of parameter “tTR_S”.
Table 10: I/O input electrical characteristics: Parameter “ILKG” (Medium Pads
(P), TJ=150°C/360 mA) removed.
Table 11: I/O pull-up/pull-down electrical characteristics: Added note “When
the device enters into standby mode... an ADC function.”
13-Dec-2016
2
(cont’d)
Section 3.11: Oscillators:
Removed figure “Test circuit”
Table 21: External 40 MHz oscillator electrical specifications:
– Footnote “Ixatl is the oscillator...Test circuit is shown in Figure 8” modified to
“Ixatl is the oscillator...startup of the oscillator”.
– Minimum value of parameter “VIHEXT” updated from “VREF+0.6” to
“VREF+0.75”
– Maximum value of parameter “VILEXT” updated from “VREF-0.6” to “VREF0.75”
– Parameter “gm”, value “D” updated to “P” for “fXTAL < 8 MHz”, and “D” for
others.
– Footnote “This parameter is...100% tested” updated to “Applies to an...to
crystal mode”. Also added to parameter “VILEXT”.
– For parameters “VIHEXT” and “VILEXT”, Condition “–” updated to “VREF = 0.29
* VDD_HV_OSC”
Table 23: 1024 kHz internal RC oscillator electrical characteristics: For
parameter “fvar_V”, minimum and maximum value updated from “-0.05” and
“+0.05” to “-5” and “+5”.
Section 3.12: ADC system:
Table 26: ADC-Comparator electrical specification: For parameter tADCSAMPLE
Standard channel, minimum value updated to “6/fADCK”
Section 3.14: LFAST pad electrical characteristics:
Table 29: LFAST transmitter electrical characteristics,,: Footnote “The
transition time is measured from...” removed.
Section 3.15: Power management:
Table 31: Power management regulators: Added option for “Internal linear
regulator internal ballast” and added footnote “For compatibility purpose...local
sales”.
Table 33: Linear regulator specifications: Updated description of IDDMREG.
Table 35: Voltage monitor electrical characteristics: Added Parameter
VUVD140_F.
Added Figure 13: Internal regulator with external ballast mode, Figure 15:
Standby regulator with external ballast mode, Figure 14: Internal regulator with
internal ballast mode
DS11701 Rev 4
131/142
141
Revision history
SPC584Bx
Table 75. Document revision history (continued)
Date
Revision
Changes
Section 3.17: AC Specifications:
Updated Figure 28: DSPI CMOS master mode — classic timing, CPHA = 1
13-Dec-2016
2
(cont’d)
Section 4: Package information:
Updated Figure 43: eTQFP64 package outline
Updated Table 61: eTQFP64 package mechanical data
Updated Table 62: eTQFP100 package mechanical data
Updated Table 64: eLQFP176 package mechanical data
Section 6: Ordering information:
Updated Figure 59: Ordering information scheme
Section : Features
Changed core name to e200z420 (was e200z4d)
Added first bullet “AEC-Q100 qualified”
Changed document classification “Target Specification” by “Production Data”
Removed ST Restricted watermark on all document
16-Mar-2018
3
Section 1: Introduction
Section 2: Description: Updated latest sentence with “one processor core”
(was two)
Table 2: Features list:
Updated MPU description
Added “Semaphores”
Updated “System SRAM”
Updated “DMA channels values”
Removed “Interrupt controller”
Figure 2: Periphery allocation:
Removed SEMA42 block
Section 2.3: Features overview:
Updated:
– 64 KB local data RAM for Core_2
– 8 KB I-Cache and 4 KB D-Cache for Core_2
– 128 KB on-chip general-purpose SRAM (+ 64 KB local data RAM: 64 KB
included in the CPU)
– Multi channel direct memory access controllers
Section 3: Package pinouts and signal descriptions:
Changed introduction sentence since the pin out excel file will no longer be
attached to the datasheet
Section 3: Electrical characteristics
Section 4.1: Introduction:
Removed text “The IPs and...for the details”
Removed the two notes applicable for preliminary data
132/142
DS11701 Rev 4
SPC584Bx
Revision history
Table 75. Document revision history (continued)
Date
Revision
Changes
Table 3: Parameter classifications:
Updated the description of classification tag “T”
Section 4.2: Absolute maximum ratings:
Added text “Exposure to absolute ... reliability”
Added text “even momentarily”
Table 4: Absolute maximum ratings:
Updated values in conditions column
Added parameter TTRIN
For parameter “TSTG”, maximum value updated from “175” to “125”
Added new parameter “TPAS”
For parameter “IINJ”, description updated from “maximum...PAD” to “maximum
DC...pad”
Changed VDD_HV_IO_FLEX to VDD_HV_IO_ETH
16-Mar-2018
3
(cont’d)
Section 4.3: Operating conditions
Table 5: Operating conditions:
For parameter “VDD_LV”, changed the classification from “D” to “P”
Removed note “Core voltage as ....”
Added parameter IINJ2
Removed parameter “VRAMP_LV”
Changed parameter VDD_HV_IO_FLEX to VDD_HV_IO_ETH
Updated the table footnote “Positive and negative Dynamic current....”
Table 6: Device supply relation during power-up/power-down sequence:
Parameter “VDD_LV” removed
Changed parameter VDD_HV_IO_FLEX to VDD_HV_IO_ETH
Section 3.3.1: Power domains and power up/down sequencing:
Replaced reference to IO_definition excel file by "the device pin out IO
definition excel file"
Section 4.7: Device consumption
Table 8: Device consumption:
Updated parameter “IDDHALT”
Updated parameter “IDDSTOP”
Added note to parameters IDDHALT and IDDSTOP
Updated “IDD_LKG”: Classification “P” changed to “C” for all devices when <
TJ = 40 °C, added footnote “IDD_LKG and IDD_LV are reported as...”
Updated “IDD_LV”: added footnote “IDD_LKG and IDD_LV are reported as...”
Updated values of IDD_LKG, IDDHALT, IDDSTOP, IDDSTBY8, IDDSTBY32,
IDDSTBY128, IDDSSWU1 and IDDSSWU2
Updated “IDD_HV”: changed Max value “45” to “55”
Updated Max values of IDDSTBY8, IDDSTBY32, IDDSTBY128
Updated table footnotes 4, 5, 6 and 8
Changed “mA” by “µA” for IDDSTBY128
DS11701 Rev 4
133/142
141
Revision history
SPC584Bx
Table 75. Document revision history (continued)
Date
16-Mar-2018
Revision
3
(cont’d)
Changes
Section 4.8: I/O pad specification
Removed note “The external ballast....”
Reformated note from introduction
Replaced all occurences of “50 pF load” with “CL=50pF”
Replaced all references to the IO_definitions excel file by “the device pinout IO
definition excel file”
Section 4.8.2: I/O output DC characteristics: Added note “10%/90% is the....”
Table 9: I/O pad specification descriptions:
Description of “Standby pads” updated from “Some pads are active...weak-pull
currents” to “These pads are active...CMOS threshhold”
Removed FlexRay at Very strong configuration description
Changed “the CMOS threshold” by “(VDD_HV_IO_MAIN / 2) +/-20%” at
Standby pads type
Table 12: WEAK/SLOW I/O output characteristics:
For parameter “Fmax_W”, updated condition “25 pF load” to “CL=25pF”
For parameter “|tSKEW_W|”, changed max value from “30” to “25”
Table 14: STRONG/FAST I/O output characteristics:
Parameter “IDCMAX_S” updated:
– Condition added “VDD=5V+10%
– Condition added “VDD=3.3V+10%
– Max value updated to 5.5mA
Updated values for tTR_S for condition CL = 25 pF and CL = 50 pF
Table 15: VERY STRONG/VERY FAST I/O output characteristics:
“tTR20-80” replaced by “tTR20-8_V”
“tTRTTL” replaced by “tTRTTL_V”
“tTR20-80” replaced by “tTR20-80_V”
Removed FlexRay Standard in bracket at tTR20-80_V parameter
Table 16: I/O consumption:
Updated all the max values of parameters IDYN_W and IDYN_M
Section 3.9: Reset pad (PORST) electrical characteristics:
Table 17: Reset PAD electrical characteristics:
Replaced reference to IO_definition excel file by "Refer to the device pin out IO
definition excel file"
Table 18: Reset Pad state during power-up and reset: added this table
Section 3.10: PLLs
Table 19: PLL0 electrical characteristics:
For parameter “IPLL0”, classification changed from “C” to “T”
Footnote “Jitter values...measurement” added for parameters:
– PLL0PHI0SPJ|
– PLL0PHI1SPJ|
– PLL0LTJ
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Revision history
Table 75. Document revision history (continued)
Date
Revision
Changes
Updated footnote “Jitter values...contribution of pad used as CLKOUT for
measurement” to “Jitter values...contribution of the divider and the path of the
output CLKOUT pin” for parameters:
– PLL0PHI0SPJ|
– PLL0PHI1SPJ|
– PLL0LTJ
Added “fINFIN” for all devices
Symbol “fINFIN”: changed “C” by “—” in column “C”
UpdatedPLL0PHI0SPJ|: changed “T” by “D” and added pk-pk to Conditions
value
Updated PLL0PHI1SPJ|: added pk-pk to Conditions value
Table 20: PLL1 electrical characteristics:
For parameter “IPLL1”, classification changed from “C” to “T”.
Footnote “Jitter values...measurement” added for parameter “PLL1PHI0SPJ|”
Updated footnote “Jitter values...contribution of pad used as CLKOUT for
measurement” to “Jitter values...contribution of the divider and the path of the
output CLKOUT pin” for parameter “PLL1PHI0SPJ|”
Added “fINFIN”
Symbol “fINFIN”: changed “C” by “—” in column “C”
16-Mar-2018
3
(cont’d)
Section 4.11: Oscillators
Renamed the section “RC oscillator 1024 kHz” to Section 4.11.4: Low power
RC oscillator
Table 21: External 40 MHz oscillator electrical specifications:
Classification for parameters “CS_EXTAL” and “CS_XTAL” changed from “T” to
“D”
Min and Max value of parameters CS_EXTAL and CS_XTAL updated to “3” (min)
and “7” (max)
Updated classification, conditions, min and max values for parameter “gm”
Changed table footnote 3 by: This value is determined by the crystal
manufacturer and board design, and it can potentially be higher than the
maximum provided
Updated table footnote 1
Table 22: 32 kHz External Slow Oscillator electrical specifications: Added this
table
Table 23: Internal RC oscillator electrical specifications:
For parameter “IFIRC”, replaced max value of 300 with 600
Added footnote to the description
Min, Typ and Max value of ”fvar_SW” updated from “-1”, “-”, “1” to “-0.5”, “+0.3”
and “0.5” respectively
Table 24: 1024 kHz internal RC oscillator electrical characteristics
For parameter “fvar_T”, and “fvar_V“: changed the classification to “P”.
Section 4.12: ADC system:
Table 25: ADC pin specification
For ILKG, changed condition “C” to “—”.
For parameter CP2, updated the max value to “1”.
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Revision history
SPC584Bx
Table 75. Document revision history (continued)
Date
Revision
Changes
Updated Max value for CS
For parameter CP2, updated the max value from “1” to “2”
Added electrical specification for R20K symbol
Changed Max value = 1 by 2 for Cp2 SARB channels
Table 26: SARn ADC electrical specification:
Classification for parameter “IADCREFH” changed from “C” to “T”.
For parameter fADCK (High frequency mode), changed min value from “7.5” to
“> 13.33”
Deleted footnote “Values are subject to change (possibly improved to ±2 LSB)
after characterization”
Added symbols tADCINIT and tADCBIASINIT
Column “C” split and added “D” for IADV_S
Table 27: ADC-Comparator electrical specification
Classification for parameter “IADCREFH” changed from “C” to “T”
Removed table footnote “Values are subject to change (possibly improved to
±2 LSB) after characterization”
Added new parameter “tADCINITSBY”
Set min = 5/fADCK µs for 10-bit ADC mode, min = 2/fADCK” for ADC comparator
mode, at symbol tADCSAMPLE
Column “C” split and added “D” for IADV_S
Figure 8: Input equivalent circuit (Fast SARn and SARB channels): updated
16-Mar-2018
3
(cont’d)
Section 3.13: Temperature Sensor
Table 28: Temperature sensor electrical characteristics:
For “temperature monitoring range”: classification removed (was C)
Section 4.14: LFAST pad electrical characteristics:
Introduction paragraph:
– 1st sentence: hidden text “both the SIPI and”
– all 2nd sentence hidden: “The same LVDS.. tables”
Figure 9: LFAST LVDS timing definition:
Title changed to “LFAST LVDS timing definition”
Deleted:
– 400 mV p-p (MSC/DSPI)
– 0.50 * T (MSC/DSPI)
– (MSC/DSPI)
Table 29: LVDS pad startup and receiver electrical characteristics,:
For parameter ILVDS_BIAS, changed the characteristics to “C”
Table 31: LFAST PLL electrical characteristics:
– Min and Max value of parameter “ERRREF” updated from “TBD” to “-1” and
“+1” respectively
– Max value of parameter “PN” updated from “TBD” to “-58”
– Frequency of parameter “PERREF” updated from “10MHz” to “20MHz”
– Max value of parameter “PERREF” for condition “Single period” updated
from “TBD” to “350”
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Revision history
Table 75. Document revision history (continued)
Date
Revision
Changes
– Min and Max value of parameter “PERREF” for condition “Long period”
updated from “TBD” to “-500” and “+500” respectively
16-Mar-2018
3
(cont’d)
Section 4.15: Power management
Section 4.15.1: Power management integration
Added sentence “It is recommended...device itself” for all devices
Figure 17: Voltage monitor threshold definition: Updated figure
Table 32: Power management regulators
Removed text “In parts packaged with LQFP176, the auxiliary and clamp
regulators cannot be enabled” from note 2
Table 33: External components integration
For PMOS, replaced “STT4P3LLH6” with “PMPB100XPEA”
For NMOS, replaced “STT6N3LLH6” with “PMPB55XNEA”
Added table footnote to typ value of CS2
Removed table footnote “External components number.......”
Updated Min and Max values at symbol CE to 1.1 and 3.0 respectively
Table 34: Linear regulator specifications
Classification of parameter “IDDMREG” changed from “P” to “T”
Classification of parameter “IDDMREG” changed from “T” to “P”
Updated values for symbol “IDDMREG”:
– Min: added -100
– Max: added 100
Updated TBD values
Table 35: Auxiliary regulator specifications: added table
Table 36: Clamp regulator specifications: added table
Table 38: Voltage monitor electrical characteristics:
VPOR031_C: changed the max value from 0.85 to 0.97
TVMFILTER: replaced T with D
Min value of “VPOR200_C” updated from “1.96” to “1.80”
Max value of “VPOR031_C” updated from “.85” “0.97”
Changed the min value of parameter VPOR200_C from “1.96” to “1.80”
Changed the max value of parameter VPOR031_C from “0.85” to “0.97”
Changed the condition of parameter TVMFILTER from “T” to “D”
In Supply/Parameter: Replaced “_FLEX” by “_ETH” for VLVD290_IF, VLVD400_IF,
VHVD400_IF and VUVD600_IF symbols
Added symbol VUVD600_F
Section 3.16: Flash
Table 39: Wait state configuration: added column for “APC” and table
footnotes, other columns updated
Table 40: Flash memory program and erase specifications: updated
Table 38: Flash memory Life Specification: updated
Section 4.17: AC specifications
Section 4.17.4: CAN timing: added section
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Revision history
SPC584Bx
Table 75. Document revision history (continued)
Date
Revision
Changes
Table 43: Nexus debug port timing: Classification of parameters “tEVTIPW” and
“tEVTOPW” changed from “P” to “D”
Table 45: DSPI channel frequency support
Added column to show slower and faster frequencies
Added DSPI_5 to lower frequency and removed it from higher frequency
Table 46: DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1
Changed the Min value of tSCK (very strong) from 33 to 59
Table 56: CAN timing: Added columns for “CC” and “D”
16-Mar-2018
3
(cont’d)
Section 4: Package information
Table 61: eTQFP64 package mechanical data
Deleted angle lines
Updated values for D2, D3, E2, E3 and ddd
Table 62: eTQFP100 package mechanical data
Deleted angle lines
Table 64: eLQFP176 package mechanical data
Updated values for D2 and E2
Figure 43: eTQFP64 package outline: Removed “6.2x6.2 mm” after “eTQFP
10x10x1.0”
Figure 44: eTQFP100 package outline
Removed “6.4x6.4 mm” after “eTQFP 14x14x1.0”
Table 69: Thermal characteristics for 64 exposed pad eTQFP package:
Updated all parameters values
Table 70: Thermal characteristics for 100 exposed pad eTQFP package:
Updated all parameters values
Table 71: Thermal characteristics for 144 exposed pad eTQFP package:
Updated all parameters values
Table 72: Thermal characteristics for 176 exposed pad LQFP package:
Updated all parameters values
Section 6: Ordering information
Figure 59: Ordering information scheme:
Removed “R” value for the Packing options
Replaced “X” by “0” for Silicon revision
Added “”pin 1 top right” to “X” description in Packing
Table 73: Code Flash options and Table 74: RAM options: added these tables
138/142
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Revision history
Table 75. Document revision history (continued)
Date
Revision
Changes
Section 1: Introduction: Removed “Document overview” section title.
Section 2: Description: Changed title type.
10-Sep-2019
4
Section 4.2: Absolute maximum ratings
Table 4: Absolute maximum ratings: Added cross reference to footnote(2) to all
VDD_HV* and VIN
Section 4.3: Operating conditions
– Table 5: Operating conditions: VDD_HV_ADR_S: Removed line for C condition.
Section 4.5: Electromagnetic compatibility characteristics: Updated section
title from “Electromagnetic emission characteristics” to Section 4.5:
Electromagnetic compatibility characteristics.
Section 4.7: Device consumption
Table 8: Device consumption:
– Updated maximum values of all conditions and changed from ‘P’ to ‘C’ in C
column at TJ=40 °C condition for IDDSTBY8, IDDSTBY32 and IDDSTBY128
parameters.
– Moved table footnote 1. from table title to “Value”.
Section 4.9: Reset pad (PORST) electrical characteristics
Figure 5: Startup Reset requirements: Deleted VDDMIN.
Section 4.10: PLLs
– Table 19: PLL0 electrical characteristics: Changed condition from T to D for
PLL0PHI1SPJ|, PLL0LTJ and IPLL0.
– Table 20: PLL1 electrical characteristics: Changed condition from T to D for
IPLL1.
Section 4.11: Oscillators:
Table 23: Internal RC oscillator electrical specifications: Updated Max value for
IFIRC.
Section 4.12: ADC system:
– Figure 8: Input equivalent circuit (Fast SARn and SARB channels): Added
parameter “CEXT: external capacitance” and component to scheme.
– Table 25: ADC pin specification: Added row for symbol “CEXT / SR”.
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Revision history
SPC584Bx
Table 75. Document revision history (continued)
Date
10-Sep-2019
140/142
Revision
4
(cont’d)
Changes
Section 4.14: LFAST pad electrical characteristics:
– Figure 9: LFAST LVDS timing definition: Updated.
– Table 29: LVDS pad startup and receiver electrical characteristics,:
Removed the last sentence of Note “Total internal capacitance...”.
Section 4.15: Power management:
– Table 33: External components integration: Updated conditions for CBV.
– Table 38: Voltage monitor electrical characteristics: Added footnote “Even if
LVD/HVD ...”
Section 4.16: Flash:
– Table 39: Wait state configuration: for APC=001 changed the minimum
frequency from 40 to 55 MHz
– Table 40: Flash memory program and erase specifications: Updated.
Section 4.17: AC specifications:
Section 4.17.3.7: RMII transmit signal timing (TXD[1:0], TX_EN): Added note
“RMII transmit ... as 1 ns”.
Section 5: Package information:
– Added introduction sentence in each Package section.
– Added sub-section “Package mechanical drawings and data information”
and introduction sentence to the notes list.
– Table 60: Package case numbers: Removed package reference column.
– Figure 43: eTQFP64 package outline: Updated.
– Figure 44: eTQFP64 section A-A: Added.
– Table 61: eTQFP64 package mechanical data: Updated table, notes content
and numbering.
– Section 5.1.1: Package mechanical drawings and data information: Moved
notes to new section.
– Figure 46: eTQFP64 leadframe pad design: Added.
– Table 62: eTQFP64 symbol definitions: Added.
– Figure 47: eTQFP100 package outline: Updated.
– Figure 48: eTQFP100 section A-A: Added.
– Figure 49: eTQFP100 section B-B: Added.
– Table 63: eTQFP100 package mechanical data: Updated table, notes
content and numbering.
– Section 5.2.1: Package mechanical drawings and data information: Moved
notes to new section.
– Figure 50: eTQFP100 leadframe pad design: Updated.
– Figure 51: eTQFP144 package outline: Updated.
– Table 65: eTQFP144 package mechanical data: Updated table, notes
content and numbering.
– Section 5.3.1: Package mechanical drawings and data information: Moved
notes to new section.
– Figure 55: eLQFP176 package outline: Updated.
– Figure 57: eLQFP176 section B-B: Added.
– Table 67: eLQFP176 package mechanical data: Updated table, notes and
numbering.
DS11701 Rev 4
SPC584Bx
Revision history
Table 75. Document revision history (continued)
Date
10-Sep-2019
Revision
4
(cont’d)
Changes
– Section 5.4.1: Package mechanical drawings and data information: Moved
notes to new section.
– Table 68: eLQFP176 symbol definitions: Updated.
– Table 72: Thermal characteristics for 176 exposed pad LQFP package:
Updated values.
Section 6: Ordering information
Figure 59: Ordering information scheme:
– Added figure footnotes.
– Removed “F = Security HW + ST Firmware” in security.
DS11701 Rev 4
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