STB15810

STB15810 N-channel 100 V, 3.4 mΩ typ., 110 A, STripFET™ F7 Power MOSFET in a D²PAK package Datasheet - custom data Features TAB Order code VDS RDS(on)max ID PTOT STB15810 100 V 3.9 mΩ 110 A 250 W   2 3 1 100% avalanche tested Ultra low on-resistance Applications D²PAK  Switching applications Description Figure 1: Internal schematic diagram This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packaging STB15810 15810 D²PAK Tape and reel March 2017 DocID030395 Rev 1 This is a document intended for a specific customer. It must not be released without first contacting Division marketing. 1/14 www.st.com Contents STB15810 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/14 4.1 D²PAK (TO-263) type B package information ................................... 9 4.2 D²PAK type B packing information .................................................. 11 Revision history ............................................................................ 13 DocID030395 Rev 1 STB15810 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate- source voltage ±20 V ID Drain current (continuous) at TC = 25 °C 110 A ID Drain current (continuous) at TC = 100 °C 110 A Drain current (pulsed) TC = 25 °C 440 A PTOT Total dissipation at TC = 25 °C 250 W EAS(2) Single pulse avalanche energy 495 mJ -55 to 175 °C Value Unit IDM (1) TJ Operating junction temperature range Tstg Storage temperature range Notes: (1)Pulse width is limited by safe operating area. (2)Starting Tj = 25 °C, ID = 30 A, VDD = 50 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.6 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 35 °C/W Notes: (1) When mounted on 1 inch² FR-4 board, 2 oz Cu DocID030395 Rev 1 3/14 Electrical characteristics 2 STB15810 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 250 µA Min. Typ. Max. 100 Unit V VGS = 0 V, VDS = 100 V 1 µA VGS = 0 V, VDS = 100 V, TC = 125 °C(1) 100 µA Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 55 A 3.4 3.9 mΩ Min. Typ. Max. Unit - 8115 - pF - 1510 - pF - 67 - pF - 117 - nC - 47 - nC - 26 - nC IDSS Zero gate voltage drain current IGSS 2.5 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol 4/14 Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 50 V, ID = 110 A, VGS = 0 to 10 V (see Figure 14: "Test circuit for gate charge behavior") DocID030395 Rev 1 STB15810 Electrical characteristics Table 6: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD = 50 V, ID = 55 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 33 - ns - 57 - ns - 72 - ns - 33 - ns Min. Typ. Max. Unit Table 7: Source drain diode Symbol Parameter Test conditions ISD Source-drain current - 110 A ISDM(1) Source-drain current (pulsed) - 440 A VSD (2) Forward on voltage ISD = 110 A, VGS = 0 - 1.2 V ISD = 110 A, di/dt = 100 A/µs, VDD = 80 V, TJ =150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 70 ns - 165 nC - 4.7 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width is limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID030395 Rev 1 5/14 Electrical characteristics 2.1 STB15810 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance AM18051v1 ID (A) 100 is ea n) ar S(o D is h t R in ax n tio y m b ra e d p ite O Lim 10 100µs 1ms 1 Tj=175°C Tc=25°C Single pulse 0.1 0.1 1 10ms VDS(V) 10 Figure 4: Output characteristics Figure 5: Transfer characteristics AM18042v1 ID(A) VGS=10V 400 8V AM18043v1 ID (A) VDS=4V 300 350 7V 300 250 200 250 200 150 6V 150 100 100 50 50 5V 0 0 4 2 6 8 VDS(V) Figure 6: Gate charge vs gate-source voltage AM18044v1 VGS (V) VDD=50V ID=110A 12 0 0 2 4 8 6 VGS(V) Figure 7: Static drain-source on-resistance RDS(on) (mΩ) 3.430 VGS=10V 3.420 10 3.410 8 3.400 6 3.390 4 3.380 2 3.370 3.360 0 0 6/14 40 80 120 Qg(nC) DocID030395 Rev 1 0 20 40 60 80 100 ID(A) STB15810 Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 8: Capacitance variations AM18047v1 VGS(th) (norm) ID=250µA 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 -75 Figure 10: Normalized on-resistance vs temperature 25 75 125 TJ(°C) Figure 11: Normalized V(BR)DSS vs temperature AM18048v1 RDS(on) -25 AM18049v1 V(BR)DSS (norm) (norm) ID=55A 2 1.04 1.8 1.03 1.6 1.02 1.4 1.01 1.2 1 1 0.99 0.8 0.98 ID=1mA 0.6 0.97 0.4 -75 0.96 -75 -25 25 75 TJ(°C) 125 -25 25 75 125 TJ(°C) Figure 12: Source-drain diode forward characteristics AM18055v1 VSD(V) TJ=-55°C 1 0.9 TJ=25°C 0.8 0.7 TJ=175°C 0.6 0.5 0.4 0.3 0 20 40 60 80 DocID030395 Rev 1 100 ISD(A) 7/14 Test circuits 3 8/14 STB15810 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID030395 Rev 1 STB15810 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 D²PAK (TO-263) type B package information Figure 19: D²PAK (TO-263) type B package outline 0079457_23_B DocID030395 Rev 1 9/14 Package information STB15810 Table 8: D²PAK (TO-263) type B mechanical data mm Dim. Min. Max. A 4.36 4.56 A1 0 0.25 b 0.70 0.90 b1 0.51 0.89 b2 1.17 1.37 b3 1.36 1.46 c 0.38 0.694 c1 0.38 0.534 c2 1.19 1.34 D 8.60 9.00 D1 6.90 7.50 E 10.15 10.55 E1 8.10 8.70 e 2.54 BSC H 15.00 15.60 L 1.90 2.50 L1 1.65 L2 1.78 L3 L4 10/14 Typ. 0.25 4.78 DocID030395 Rev 1 5.28 STB15810 Package information Figure 20: D²PAK (TO-263) type B recommended footprint (dimensions are in mm) 4.2 D²PAK type B packing information Figure 21: D2PAK type B tape outline DocID030395 Rev 1 11/14 Package information STB15810 Figure 22: D2PAK type B reel outline Table 9: D²PAK type B reel mechanical data mm Dim. Min. A 330 B 1.5 C 12.8 D 20.2 G 24.4 N 100 T 12/14 Max. 13.2 26.4 30.4 DocID030395 Rev 1 STB15810 5 Revision history Revision history Table 10: Document revision history Date Revision 07-Mar-2017 1 Changes First release DocID030395 Rev 1 13/14 STB15810 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 14/14 DocID030395 Rev 1