STFU10NK60Z

STFU10NK60Z N-channel 600 V, 0.68 Ω typ., 10 A, SuperMESH™ Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features 1 2 Order code VDS RDS(on) max. ID STFU10NK60Z 600 V 0.75 Ω 10 A     3 Ptot 35 W Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Zener-protected Applications TO-220FP ultra narrow leads  Switching applications Figure 1: Internal schematic diagram Description This high voltage device is a Zener-protected N-channel Power MOSFET developed using the SuperMESH™ technology by STMicroelectronics, an optimization of the well-established PowerMESH™. In addition to a significant reduction in on-resistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. Table 1: Device summary Order code Marking Package Packaging STFU10NK60Z 10NK60Z TO-220FP ultra narrow leads Tube December 2016 DocID028779 Rev 3 This is information on a product in full production. 1/13 www.st.com Contents STFU10NK60Z Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 5 2/13 TO-220FP ultra narrow leads package information ......................... 10 Revision history ............................................................................ 12 DocID028779 Rev 3 STFU10NK60Z 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 600 V VGS Gate-source voltage ±30 V ID(1) Drain current (continuous) at TC= 25 °C 10 A ID(1) Drain current (continuous) at TC = 100 °C 5.7 A IDM(2) Drain current (pulsed) 36 A PTOT Total dissipation at TC = 25 °C 35 W ESD Gate-source, human body model (R = 1.5 kΩ, C = 100 pF) 4 kV 4.5 V/ns 2500 V -55 to 150 °C Value Unit dv/dt (3) Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1s; TC= 25 °C) VISO Tj Operation junction temperature range Tstg Storage temperature range Notes: (1)Limited (2)Pulse (3)I SD by package width limited by safe operating area < 10 A , di/dt < 200 A/μs , VDD = 80 % V(BR)DSS Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 3.6 °C/W Rthj-amb Thermal resistance junction-ambient max 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or non-repetitive (pulse width limited by TJ max) 10 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 300 mJ DocID028779 Rev 3 3/13 Electrical characteristics 2 STFU10NK60Z Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Test conditions Min. VGS = 0 V, ID = 250 μA 600 Typ. Max. Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V, TC = 125 °C(1) 50 µA Gate-body leakage current VDS = 0 V, VGS = +20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3.75 4.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 4.5 A 0.68 0.75 Ω Min. Typ. Max. Unit - 1370 - pF - 156 - pF - 37 - pF 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz Coss Output capacitance Crss Reverse transfer capacitance (1) Equivalent output capacitance VGS= 0 V, VDS= 0 to 480 V - 93 - pF Qg Total gate charge - 48 - nC Qgs Gate-source charge - 8 - nC Qgd Gate-drain charge VDD = 480 V, ID = 8 A, VGS = 10 V (see Figure 13: "Test circuit for gate charge behavior") - 25 - nC Coss eq Notes: (1)C oss eq is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% Table 7: Switching times Symbol td(on) tr td(off) tf 4/13 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V (see Figure 12: "Test circuit for resistive load switching times" and Figure 17: "Switching time waveform") - 20 - ns - 20 - ns - 55 - ns - 30 - ns DocID028779 Rev 3 STFU10NK60Z Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions ISD(1) Source-drain current ISDM(2) Source-drain current (pulsed) VSD(3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Min. Typ. Max. Unit - 10 V - 36 A ISD= 10 A, VGS = 0 V - 1.6 V ISD = 8 A, di/dt = 100 A/µs, VDD = 40 V , TJ = 150 °C (see Figure 14: "Test circuit for inductive load switching and diode recovery times") - 570 ns - 4.1 µC - 15 A Min. Typ. Max. Unit ±30 - - V Notes: (1)Limited (2)Pulse by package width limited by safe operating area (3)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Test conditions Gate-source breakdown voltage IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID028779 Rev 3 5/13 Electrical characteristics 2.1 STFU10NK60Z Electrical characteristics (curves) Figure 2: Safe operating area Figure 4: Output characteristics 6/13 Figure 3: Thermal impedance Figure 5: Gate charge vs gate-source voltage DocID028779 Rev 3 STFU10NK60Z Electrical characteristics Figure 6: Capacitance variations Figure 7: Static drain-source on-resistance Figure 8: Normalized gate threshold voltage vs temperature Figure 9: Normalized on-resistance vs temperature DocID028779 Rev 3 7/13 Electrical characteristics STFU10NK60Z Figure 10: Source-drain diode forward characteristics 8/13 Figure 11: Maximum avalanche energy DocID028779 Rev 3 STFU10NK60Z 3 Test circuits Test circuits Figure 12: Test circuit for resistive load switching times Figure 13: Test circuit for gate charge behavior Figure 14: Test circuit for inductive load switching and diode recovery times Figure 15: Unclamped inductive load test circuit Figure 16: Unclamped inductive waveform Figure 17: Switching time waveform DocID028779 Rev 3 9/13 Package information 4 STFU10NK60Z Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 18: TO-220FP ultra narrow leads package outline 8576148_1 10/13 DocID028779 Rev 3 STFU10NK60Z Package information Table 10: TO-220FP ultra narrow leads mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 L9 3.20 3.60 - 1.30 Dia. 3.00 3.20 DocID028779 Rev 3 2.54 2.70 11/13 Revision history 5 STFU10NK60Z Revision history Table 11: Document revision history Date Revision 07-Jan-2016 1 Initial release. 12-Sep-2016 2 Document status changed from preliminary to production data. Minor text changes. 3 Updated Features on cover page. Updated Table 2: "Absolute maximum ratings" and added Table 4: "Avalanche characteristics". Updated Table 5: "On /off states", Table 6: "Dynamic", Table 8: "Source drain diode" and Table 9: "Gate-source Zener diode". Minor text changes 05-Dec-2016 12/13 Changes DocID028779 Rev 3 STFU10NK60Z IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID028779 Rev 3 13/13