STG4159BJR

STG4159 Low voltage 0.3Ω max single SPDT switch with break-before-make feature and 10kV contact ESD protection Features ■ Wide operating voltage range: VCC (OPR) = 1.65V to 4.8V ■ Low power dissipation: ICC = 0.2µA (max.) at TA = 85°C ■ Low "ON" resistance VIN = 0V: – RON = 0.40Ω (max. TA = 25ºC) at VCC = 2.25V – RON = 0.35Ω (max. TA = 25ºC) at VCC = 3.0V – RON = 0.30Ω (max. TA = 25ºC) at VCC = 4.3V Flip-Chip7 Description ■ Separate supply voltage for switch and control pin ■ Latch-up performance exceeds 100mA per JESD 78, Class II ■ ESD performance tested on common channel (D pin) – 10kV IEC-61000-4-2 ESD, contact discharge – 15kV IEC-61000-4-2 ESD, air discharge ■ ESD performance test on all other pins – 10kV IEC-61000-4-2 ESD, contact discharge – 500V machine model (JESD22 A115-A) – 1500V charged-device model (JESD22 C101) (s) t c u d o r P e t e l o s b O Table 1. April 2007 c u d ) s t( o r P The STG4159 is a high-speed CMOS low voltage single analog SPDT (Single Pole Dual Throw) switch or 2:1 multiplexer/demultiplexer switch fabricated in silicon gate C2MOS technology. It is designed to operate from 1.65V to 4.58V, making this device ideal for portable applications. It offers low ON-resistance (0.45Ω) at VCC = 4.3V. The SEL inputs are provided to control the switches. e t le o s b O - The switch S1 is ON (connected to common Port D) when the SEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low; the switch S2 is ON (it is connected to common Port D) when the SEL input is held low and OFF (high impedance state exist between the two ports) when SEL is held high. Additional key features are fast switching speed, break-before-make delay time and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. Device summary Part number Package Packaging STG4159 Flip-Chip7 Tube STG4159BJR Flip-Chip7 Tape and reel Rev 3 1/18 www.st.com 18 STG4159 Contents Contents 1 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Test circuits 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ................................................. 9 c u d e t le ) s ( ct u d o r P e t e l o s b O 2/18 o s b O - o r P ) s t( STG4159 1 Logic diagram Logic diagram Figure 1. Functional diagram S1 D S2 SEL Figure 2. Input equivalent circuit c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Table 2. O bs Truth table SEL Switch S1 Switch S2 H ON OFF (1) L OFF (1) ON 1. High Impedance 3/18 STG4159 Logic diagram Figure 3. Pin connection (bump side view) Table 3. Pin description Flip-Chip Symbol 1, 3 S1, S2 7 D 6 SEL Control 5 VCC Positive supply voltage 4 VL 8 GND ) s ( ct u d o r P e t e l o s b O 4/18 Name and function Independent channels Common channel o r P Logic supply voltage e t le Ground (0V) o s b O - c u d ) s t( STG4159 2 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol Value Unit Supply voltage -0.5 to 5.5 V VL Logic supply voltage -0.5 to 5.5 V VI DC input voltage -0.5 to VCC + 0.5 V VIC DC control input voltage VO DC output voltage IIKC DC input diode current on control pin (VSEL < 0V) IIK DC input diode current (VSEL < 0V) IOK DC output diode current IO DC output current IOP DC output current peak (pulse at 1ms, 10% duty cycle) VCC Parameter 1. V -50 mA c u d ro ±20 mA ±300 mA ±500 mA ±100 mA 500 mW -50 to 105 °C 260 °C Value Unit Supply voltage (1) 1.65 to 4.8 V Logic supply voltage (2) 1.65 to VCC V 0 to VCC V 0 to VL V Tstg Storage temperature ) s ( ct P e let o s b O - Power dissipation at TA = 70ºC (1) Lead temperature (10 sec) Derate above 70ºC by 18.5mW/C VCC t e l o VL u d o Recommended operating conditions r P e Symbol O -0.5 to VCC + 0.5 mA PD Table 5. bs V ±50 ICC or IGND DC VCC or ground current TL ) s t( -0.5 to VL + 0.5 Parameter VI Input voltage VIC Control input voltage VO Output voltage 0 to VCC V Top Operating temperature -40 to 85 °C dt/dv Input rise and fall time control input VL = 1.65V to 2.7V 0 to 20 VL = 3.0V to 4.8V 0 to 10 ns/V 1. Truth Table guaranteed: 1.65V to 4.8V 2. VL pin should not be left floating. 5/18 STG4159 Electrical characteristics 3 Electrical characteristics Table 6. DC specifications Test conditions Symbol Value TA = 25°C Parameter VCC (V) VL (V) -40 to 85°C Unit Min. Typ. Max. Min. Max. High level input voltage VIH Low level input voltage VIL 1.65-4.3 1.65-4.3 1.65-1.95 1.25 1.25 2.3-2.7 1.75 1.75 3.0-3.6 2.35 2.35 4.3 2.8 2.8 1.65-1.95 0.6 0.6 2.3-2.7 0.8 0.8 3.0-3.6 1.05 4.3 1.5 1.8 2.25 RON ON resistance 3 1.65-4.3 3.7 0.40 0.25 P e let 0.35 0.45 0.22 0.32 0.42 0.21 0.30 0.40 3 IS=100mA (s) u d o ON resistance flatness (2) r P e t e l o s b O 6/18 0.50 3 IS=100mA mΩ 3 4.3 3 1.8 300 400 450 130 170 230 90 120 170 90 120 170 90 120 170 2.5 3 1.65 - 4.3 3.7 VS=0V to VCC IS=100mA 4.3 IOFF Sn OFF state leakage current 1.65-4.3 1.65 - 4.3 ION Sn ON state leakage current 1.65-4.3 1.65 - 4.3 ID D ON state leakage current 1.65-4.3 1.65 - 4.3 VS=0 to VCC VD=0 to VCC VS=0 to VCC VD=Open VS=Open VD=0 to VCC Ω 3 VS=0V to VCC ct RFLAT 0.85 5 b O - 1.65-4.3 3.7 d o r V 1.5 0.30 so 2.25 ON resistance match between channels (1) uc 0.65 VS=0V to VCC 1.8 ) s t( 1.05 0.49 4.3 ∆RON V mΩ -20 20 -300 300 nA -20 20 -100 100 nA -20 20 -100 100 nA STG4159 Electrical characteristics Table 6. DC specifications Test conditions Symbol Value TA = 25°C Parameter VCC (V) VL (V) -40 to 85°C Unit Min. Typ. Max. Min. Max. ICC Quiescent supply current 1.65-4.3 1.65 - 4.3 VSEL=VCC or GND -0.05 0.05 -0.2 0.2 µA ISEL SEL leakage current 1.65-4.3 1.65 - 4.3 VSEL=4.3V or GND -0.1 0.1 -1 1 µA 1. ∆RON = RON(Max) - RON(Min) 2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Table 7. AC electrical characteristics (CL = 35pF, RL = 50Ω, tr = tf ≤5ns) Test conditions Symbol Value TA = 25°C Parameter VCC (V) Min. tPLH, tPHL Propagation delay Max. 1.65-1.95 0.13 2.3-2.7 0.15 d o r P e let 1.65-4.3 0.16 3.6-4.3 2.3-2.7 TURN-ON time 3-3.6 so VS = VCC b O - 1.65-4.3 RL = 50Ω 1.65-1.95 tOFF t e l o o r P e tD s b O 2.3-2.7 du TURN-OFF time Breakbefore-make time delay 3-3.6 VS = VCC 1.65-4.3 RL = 50Ω 1.65-1.95 3-3.6 CL = 35pF 1.65-4.3 RL = 50Ω VS = VCC/2 4.3 1.65-1.95 Q Charge injection 1.65-4.3 3.6-4.3 95 123 160 48 62 80 33 43 56 29 38 49 12 15 20 12 16 21 13 17 22 13 17 22 10 42 10 22 5 15 5 12 ns 83 2.3-2.7 3.0-3.3 ns ns CL = 30pF 4.3 2.3-2.7 Max. ns CL = 30pF ) s ( ct 4.3 Min. 0.16 1.65-1.95 tON uc Typ. 3.0-3.3 ) s t( -40 to 85°C Unit VL (V) CL = 1nF 98 VGEN = 0V 114 pC 140 7/18 STG4159 Electrical characteristics Table 8. Analog switch characteristics (CL = 5pF, RL = 50Ω, TA = 25°C) Test conditions Symbol Value TA = 25°C Parameter VCC (V) Min. OIRR Xtalk Off Isolation -40 to 85°C Unit VL (V) (1) 1.65-4.3 4.3 Crosstalk 1.65-4.3 4.3 VS = 1VRMS f = 100kHz VS = 1VRMS f = 100kHz Typ. Max. Min. Max. -69 dB -69 dB 0.01 % RL = 600Ω Total harmonic distortion 2.3-4.3 BW -3dB Bandwidth (switch ON) 1.65-4.3 4.3 RL = 50Ω 28 CSEL Control pin input capacitance 1.8-4.3 1.8-4.3 VL = VCC 30 CSn Sn port capacitance 1.8-4.3 1.8-4.3 VL = VCC CD D port capacitance when switch is enabled 1.8-4.3 1.8-4.3 THD 1. CL = 50pF o s b O - e t le VL = VCC OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch ) s ( ct r P e t e l o 8/18 VS = VCC VPP f = 600Hz to 20kHz u d o s b O 4.3 o r P c u d 94 227 ) s t( MHz pF STG4159 Test circuits 4 Test circuits Figure 4. ON-Resistance Figure 6. Figure 5. OFF Leakage Figure 7. Bandwidth c u d Channel to channel crosstalk e t le ) s ( ct Figure 8. ) s t( o r P o s b O - u d o r P e OFF Isolation t e l o s b O 9/18 STG4159 Test circuits Figure 9. Test circuit Note: 1 CL = 5/35pF or equivalent: (includes jig capacitance) 2 RL = 50Ω or equivalent c u d 3 RT = ZOUT of pulse generator (typically 50Ω) Figure 10. Break-before-make time delay e t le ) s ( ct u d o r P e t e l o s b O 10/18 o s b O - o r P ) s t( STG4159 Test circuits Figure 11. Switching time and charge injection (VGEN = 0V, RGEN = 0Ω, RL = 1MΩ, CL = 100pF) Figure 12. Turn ON, turn OFF delay time c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 11/18 STG4159 Package mechanical data 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. c u d e t le ) s ( ct u d o r P e t e l o s b O 12/18 o s b O - o r P ) s t( STG4159 Table 9. Package mechanical data Flip-Chip7 mechanical data Data book (mm) Drawing (mm) Dim. Min Typ Max Min Typ Max A 0.585 0.65 0.715 0.60 0.65 0.70 A1 0.21 0.25 0.29 0.22 0.25 0.28 0.38 0.4 0.42 A2 0.4 b 0.265 0.315 0.365 0.290 0.315 0.340 D 1.018 1.068 1.118 1.053 1.068 1.083 0.49 0.5 0.51 2.018 2.068 2.118 2.053 2.068 2.083 1.49 1.5 1.51 0.46 0.5 0.54 0.272 0.284 0.292 0.08 ) s t( D1 0.5 E E1 e 1.5 0.45 0.5 f 0.284 ccc 0.08 0.55 Note: 1 The terminal Pin 1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear area" - typically 0.1mm diameter - ) The terminal Pin 1 on the backside of the product is identified by a distinguishing feature (for instance by a circular "dot" - typically 0.5mm diameter - ). c u d Figure 13. Package dimensions e t le ) s ( ct o r P o s b O - u d o r P e t e l o s b O 13/18 STG4159 Package mechanical data Figure 14. Foot print recommendations Figure 15. Marking c u d Dot, ST Logo S1 = Marking V = Manufacturing Location yww = Datecode (y = year, ww = week) e t le ) s ( ct Figure 16. Flip-Chip7 tape specification u d o r P e t e l o s b O 14/18 o s b O - o r P ) s t( STG4159 Package mechanical data Figure 17. Flip-Chip7 reel information c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 15/18 STG4159 Package mechanical data Figure 18. Flip-Chip7 reel information c u d e t le ) s ( ct u d o r P e t e l o s b O 16/18 o s b O - o r P ) s t( STG4159 6 Revision history Revision history Table 10. Revision history Date Revision Changes 05-May-2006 1 First release 22-Nov-2006 2 Schematic Figure 1 on page 3 updated 17-Apr-2007 3 Typo in cover page description c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 17/18 STG4159 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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