STL110N10F7

STL110N10F7 N-channel 100 V, 5 mΩ typ., 107 A, STripFET F7 Power MOSFET in a PowerFLAT 5x6 package Features PowerFLAT 5x6 D(5, 6, 7, 8) 8 7 5 6 Order code VDS RDS(on) max. ID PTOT STL110N10F7 100 V 6 mΩ 107 A 136 W • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications • Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. AM15540v2 Product status link STL110N10F7 Product summary Order code STL110N10F7 Marking 110N10F7 Package PowerFLAT 5x6 Packing Tape and reel DS9392 - Rev 6 - March 2020 For further information contact your local STMicroelectronics sales office. www.st.com STL110N10F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 107 A Drain current (continuous) at TC = 100 °C 75 A Drain current (pulsed) 428 A Drain current (continuous) at TC = 25 °C 21 A Drain current (continuous) at TC=100 °C 14 A IDM(2)(3) Drain current (pulsed) 84 A PTOT(1) Total power dissipation at TC = 25 °C 136 W PTOT Total power dissipation at Tpcb = 25 °C 4.8 W EAS(4) Single pulse avalanche energy 490 mJ -55 to 175 °C Value Unit ID(1) IDM(1)(2) ID(3) (3) TJ Tstg Operating junction temperature range Storage temperature range 1. This value is rated according to Rthj-c. 2. Pulse width limited by safe operating area. 3. This value is rated according to Rthj-pcb. 4. Starting TJ = 25 °C, ID = 18 A, VDD = 50 V. Table 2. Thermal resistance Symbol Parameter Rthj-case Thermal resistance junction-case 1.1 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 31.3 °C/W 1. When mounted on an FR-4 board of 1 inch², 2oz Cu, t < 10 s. DS9392 - Rev 6 page 2/14 STL110N10F7 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 250 µA Typ. 100 Zero gate voltage drain current IGSS Gate body leakage current VDS = 0, VGS = 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on‑resistance VGS = 10 V, ID= 10 A VGS = 0 V, VDS = 100 V, TC = 125 Unit V VGS = 0 V, VDS = 100 V IDSS Max. 1 °C(1) 10 µA 100 nA 4.5 V 5 6 mΩ Min. Typ. Max. Unit - 5117 - - 992 - - 39 - - 72 - - 30 - - 17 - Min. Typ. Max. Unit 2.5 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 50 V, ID = 21 A, VGS = 0 to 10 V (see Figure 13. Test circuit for gate charge behavior) pF nC Table 5. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 50 V, ID = 10 A, - 25 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 36 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 52 - ns - 21 - ns Min. Typ. Max. Unit 1.2 V Fall time Table 6. Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 21 A, VGS = 0 V - trr Reverse recovery time ISD = 21 A, di/dt = 100 A/µs, - 77 ns Qrr Reverse recovery charge VDD = 80 V, TJ = 150 °C - 150 nC IRRM Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 4.3 A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS9392 - Rev 6 page 3/14 STL110N10F7 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area AM16083v1 ID (A) AM16096v1 K δ=0.5 n) D S( o O Li per m at ite io d ni by n m this ax a R rea is 0.2 10 0.1 10 -1 0.05 0.02 1 10ms Tj=175°C Tpcb=25°C Single pulse 0.1 0.1 Single pulse 100ms 1s VDS(V) 10 1 10 -3 10 -4 Figure 3. Output characteristics VGS = 8, 9, 10 V 7V 140 10 -1 10 0 10 1 t p (s) AM16085v1 ID (A) 70 VDS=2V 50 100 6V 40 80 30 60 20 40 5V 20 0 2 4 6 8 4V VDS (V) Figure 5. Gate charge vs gate-source voltage VDS (V) GADG020320200919QVG 10 0 2 0 10 5.04 VDD = 50 V ID = 21 A 5.00 4 4.98 2 4.96 10 20 30 40 50 60 70 80 90 Qg (nC) 8 VGS(V) VGS =10V 5.02 6 0 0 6 AM16087v1 R DS (on) (m Ω) 5.06 8 4 Figure 6. Static drain-source on-resistance 12 DS9392 - Rev 6 10 -2 60 120 0 10 -3 Figure 4. Transfer characteristics AM16084v1 ID (A) 160 Zth = K Rthj-pcb 0.01 10 -2 4.94 2 4 6 8 10 12 14 16 18 20 ID(A) page 4/14 STL110N10F7 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations AM16088v1 C (pF) AM16089v1 VGS(th) (norm) 6000 1.2 1.1 Cis s 5000 ID=250µA 1 4000 0.9 3000 0.8 2000 0.7 0.6 1000 0 0 Cos s Crs s VDS (V) 10 20 30 40 50 60 70 80 0.5 0.4 -75 -50 -25 0 25 50 75 100 125 150 Figure 9. Normalized on-resistance vs temperature Figure 10. Source-drain diode forward characteristics AM16090v1 R DS (on) 1.8 AM16092v1 VS D(V) (norm) 2 TJ(°C) TJ =-55°C ID=10 A VGS =10 V 0.9 TJ =25°C 1.6 0.8 1.4 0.7 1.2 1 TJ =175°C 0.6 0.8 0.5 0.6 0.4 -75 -50 -25 0 25 50 75 100 125 150 TJ (°C) 0.4 2 4 6 8 10 12 14 16 18 20 IS D(A) Figure 11. Normalized V(BR)DSS vs temperature AM16091v1 V(BR)DSS (norm) ID=1mA 1.04 1.02 1 0.98 0.96 0.94 -50 DS9392 - Rev 6 -25 0 25 50 75 100 TJ(°C) page 5/14 STL110N10F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS9392 - Rev 6 page 6/14 STL110N10F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 type C package information Figure 18. PowerFLAT 5x6 type C package outline Bottom view Side view Top view 8231817_typeC_Rev20 DS9392 - Rev 6 page 7/14 STL110N10F7 PowerFLAT 5x6 type C package information Table 7. PowerFLAT 5x6 type C package mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e DS9392 - Rev 6 Typ. 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.05 1.35 L 0.725 1.025 L1 0.05 θ 0° 0.15 6.35 0.25 12° page 8/14 STL110N10F7 PowerFLAT 5x6 type C package information Figure 19. PowerFLAT 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_20 DS9392 - Rev 6 page 9/14 STL110N10F7 PowerFLAT 5x6 packing information 4.2 PowerFLAT 5x6 packing information Figure 20. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 21. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS9392 - Rev 6 page 10/14 STL110N10F7 PowerFLAT 5x6 packing information Figure 22. PowerFLAT 5x6 reel DS9392 - Rev 6 page 11/14 STL110N10F7 Revision history Table 8. Document revision history Date Revision 03-Dec-2012 1 Changes First release. Modified: PTOT value and Figure 1 in cover page Modified: ID, IDM and PTOT values in Table 2 Added: EAS value in Table 2 12-Dec-2013 2 Modified: all values in Table 3 Modified: IDSS, IGSS and ID for RDS(on) Updated: the entire typical values in Table 5, 6 and 7 Updated: Figure 13, 14, 15 and 16 Minor text changes Updated title and features on cover page. 25-Mar-2014 3 Added PTOT value at TC = 25 °C in Table 2: Absolute maximum ratings. Updated Section 4: Package mechanical data. Modified: title, features and description 20-Aug-2014 4 Modified: Figure 2 and 3 Updated: Section 4: Package mechanical data. Minor text changes Removed maturity status indication. Updated title and description on cover page. 17-Sep-2018 5 Updated Table 1. Absolute maximum ratings and Table 6. Source-drain diode. Updated Section 4.1 PowerFLAT™ 5x6 type C package information. Minor text changes 03-Mar-2020 DS9392 - Rev 6 6 Updated Figure 5. Gate charge vs gate-source voltage. Minor text changes. page 12/14 STL110N10F7 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.1 PowerFLAT 5x6 type C package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS9392 - Rev 6 page 13/14 STL110N10F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS9392 - Rev 6 page 14/14