STS4C3F60L

STS4C3F60L N-CHANNEL 60V - 0.045 Ω - 4A SO-8 P-CHANNEL 60V - 0.100 Ω - 3A SO-8 StripFET™ MOSFET Table 1: General Features TYPE STS4C3F60L (N-Channel) STS4C3F60L (P-Channel) s s s Figure 1: Package RDS(on) < 0.055 Ω < 0.120 Ω ID 4A 3A VDSS 60 V 60 V s TYPICAL RDS(on) (N-Channel) = 0.045 Ω TYPICAL RDS(on) (P-Channel) = 0.100 Ω STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY LOW THRESHOLD DRIVE SO-8 DESCRIPTION This MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Figure 2: Internal Schematic Diagram APPLICATIONS s DC/DC CONVERTERS s BACK LIGHT INVERTER FOR LCD Table 2: Order Codes PART NUMBER STS4C3F60L MARKING S4C3F60L PACKAGE SO-8 PACKAGING TAPE & REEL Rev. 2 September 2004 1/11 STS4C3F60L Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID ID IDM ( ) PTOT Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate-source Voltage Drain Current (continuous) at TC = 25°C Single Operating Drain Current (continuous) at TC = 100°C Single Operating Drain Current (pulsed) Total Dissipation at TC = 25°C Operating Junction Temperature Storage Temperature 4 2.5 16 2 -55 to 150 Value N-CHANNEL 60 60 ± 16 3 1.9 12 P-CHANNEL V V V A A A W °C Unit ( ) Pulse width limited by safe operating area Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed Table 4: Thermal Data Rthj-amb (1) Thermal Resistance Junction-ambient 62.5 °C/W (1) When mounted on 1 inch² pad of 2 oz. copper, t ≤ 10 s ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Test Conditions ID = 250 µA, VGS = 0 n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch 1 1.5 0.045 0.100 0.050 0.130 0.055 0.120 0.065 0.160 Min. 60 60 1 10 ±100 ±100 Typ. Max. Unit V V µA µA nA nA V V Ω Ω Ω Ω VDS= Max Rating Zero Gate Voltage Drain Current (VGS = 0) VDS= Max Rating, TC= 125°C Gate-body Leakage Current (VDS = 0) VGS= ± 16V VGS= ± 16V Gate Threshold Voltage VDS = VGS, ID= 250 µA Static Drain-source On Resistance VGS= 10 V, ID= 2 A VGS= 10 V, ID= 1.5 A VGS= 4.5 V, ID= 2 A VGS= 4.5 V, ID= 1.5 A Table 6: Dynamic Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 30 V, ID= 2 A VDS = 10 V, ID= 3 A VDS = 25V, f = 1 MHz, VGS = 0 n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch Min. Typ. 7 7.2 1030 630 140 121 40 49 Max. Unit S S pF pF pF pF pF pF (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 2/11 STS4C3F60L ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Switching On Symbol td(on) Parameter Turn-on Delay Time Test Conditions N-CHANNEL VDD = 30 V, ID = 2 A, RG= 4.7 Ω, VGS = 4.5 V P-CHANNEL VDD = 30 V, ID = 1.5 A, RG= 4.7 Ω, VGS = 4.5 V (Resistive Load see, Figure 28) N-CHANNEL VDD= 48 V, ID= 4 A, VGS= 4.5 V P-CHANNEL VDD = 48 V, ID = 3 A, VGS = 4.5 V (see, Figure 31) n-ch p-ch Min. Typ. 15 124 Max. Unit ns ns tr Rise Time n-ch p-ch 28 54 ns ns Qg Total Gate Charge n-ch p-ch n-ch p-ch n-ch p-ch 15 11.6 4 4.5 4 4.7 20.4 15.7 nC nC nC nC nC nC Qgs Qgd Gate-Source Charge Gate-Drain Charge Table 8: Switching Off Symbol td(off) Parameter Turn-off Delay Time Test Conditions N-CHANNEL VDD = 30 V, ID = 2 A, RG= 4.7 Ω, VGS = 4.5 V P-CHANNEL VDD = 30 V, ID = 1.5 A, RG= 4.7 Ω, VGS = 4.5 V (Resistive Load see, Figure 28) n-ch p-ch Min. Typ. 45 39 Max. Unit ns ns tf Fall Time n-ch p-ch 10 14.5 ns ns Table 9: Source-Drain Diodef Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 4 A, VGS = 0 ISD = 3 A, VGS = 0 N-CHANNEL ISD = 4 A, di/dt = 100 A/µs VDD = 20V, Tj = 150°C P-CHANNEL ISD = 3 A, di/dt = 100 A/µs VDD = 20V, Tj = 150°C (see test circuit, Figure 29) Test Conditions n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch 85 44 85 68.2 2 3.1 Min. Typ. Max. 4 3 16 12 1.2 1.2 Unit A A A A V V ns ns nC nC A A (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. 3/11 STS4C3F60L Figure 3: .Safe Operating n-channel Figure 6: Thermal Impedance For Complementary Pair Figure 4: Output Characteristics n-channel Figure 7: Transfer Characteristics n-channel Figure 5: Transconductance n-channel Figure 8: Static Drain-Source On Resistance nchannel 4/11 STS4C3F60L Figure 9: Gate Charge vs Gate-Source Voltage n-channel Figure 12: Capacitance Variations n-channel Figure 10: Normalized Gate Thereshold Voltage vs Temperature n-channel Figure 13: Normalized On Resistance vs Temperature n-channel Figure 11: Source-Drain Forward Characteristics n-channel Figure 14: Normalized BVdss vs Temperature n-channel 5/11 STS4C3F60L Figure 15: Safe Operating p-channel Figure 18: Thermal Impedance for Complementary Pair Figure 16: Output Characteristics p-channel Figure 19: Transfer Characteristics p-channel Figure 17: Transconductance p-channel Figure 20: Static Drain-Source On Resistance p-channel 6/11 STS4C3F60L Figure 21: Gate Charge vs Gate-Source Voltage p-channel Figure 24: Capacitances Variations p-channel Figure 22: Normalized Gate Thereshlod Voltage vs Temperature p-channel Figure 25: Normalized On Resistance vs Temperature p-channel Figure 23: Source-Drain Diode Forward Characteristics p-channel Figure 26: Normalized BVdss vs Temperature p-channel 7/11 STS4C3F60L Figure 27: Unclamped Inductive Load Test Circuit Figure 30: Unclamped Inductive Wafeform Figure 28: Switching Times Test Circuit For Resistive Load Figure 31: Gate Charge Test Circuit Figure 29: Test Circuit For Inductive Load Switching and Diode Recovery Times 8/11 STS4C3F60L SO-8 MECHANICAL DATA DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 9/11 STS4C3F60L Table 10: Revision History Date 16-Sep-2004 Revision 2 Complete Version Description of Changes 10/11 STS4C3F60L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 11/11