STWA48N60M6

STWA48N60M6 Datasheet N-channel 600 V, 61 mΩ typ., 39 A, MDmesh™ M6 Power MOSFET in a TO‑247 long leads package Features D(2, TAB) Order code VDS RDS(on) max. ID STWA48N60M6 600 V 69 mΩ 39 A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • G(1) S(3) AM01475V1 Switching applications LLC converters Boost PFC converters Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STWA48N60M6 Product summary Order code STWA48N60M6 Marking 48N60M6 Package TO-247 long leads Packing Tube DS12689 - Rev 2 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STWA48N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 39 A Drain current (continuous) at TC = 100 °C 25 A IDM(1) Drain current (pulsed) 140 A PTOT Total power dissipation at TC = 25 °C 250 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range VGS ID Tj Parameter Operating junction temperature range V/ns -55 to 150 °C Value Unit 1. Pulse width is limited by safe operating area. 2. ISD ≤ 39 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.5 °C/W Rthj-amb Thermal resistance junction-ambient 50 °C/W Value Unit Table 3. Avalanche characteristics Symbol DS12689 - Rev 2 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 5.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 950 mJ page 2/13 STWA48N60M6 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero-gate voltage drain current IGSS 1 VGS = 0 V, VDS = 600 V, TC = 125 100 °C(1) Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 19.5 A Unit V VGS = 0 V, VDS= 600 V IDSS Max. µA ±5 µA 4 4.75 V 61 69 mΩ Min. Typ. Max. Unit - 2578 - pF - 202 - pF - 3.1 - pF 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 480 V - 415 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 1.8 - Ω Qg Total gate charge VDD = 480 V, ID = 39 A, - 57 - nC Qgs Gate-source charge VGS = 0 to 10 V - 16 - nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 23 - nC VGS = 0 V, VDS = 100 V, f = 1 MHz 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td (on) tr td(off) tf DS12689 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 19.5 A, - 28 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 34 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 60 - ns - 9.5 - ns Fall time page 3/13 STWA48N60M6 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 39 A Source-drain current (pulsed) - 140 A 1.6 V Forward on voltage VGS = 0 V, ISD = 39 A - trr Reverse recovery time ISD = 39 A, di/dt = 100 A/µs, - 317 ns Qrr Reverse recovery charge - 4.4 μC IRRM Reverse recovery current VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 28 A trr Reverse recovery time ISD = 39 A, di/dt = 100 A/µs, - 475 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 8.67 μC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 36.5 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12689 - Rev 2 page 4/13 STWA48N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area K GADG110720180931SOA ID (A) Operation in this area is limited by R DS(on) δ=0.2 tp =1 µs 10 2 tp =10 µs 0.1 10 -1 0.05 0.02 tp =100 µs 10 1 tp =1 ms TJ≤150 °C TC=25 °C VGS=10 V single pulse 10 0 tp =10 ms 10 10 0 1 10 VDS (V) 2 10-5 VGS = 8 V 60 40 VGS = 6 V 20 20 VGS = 5 V 2 4 6 8 10 12 14 16 18 VDS (V) Figure 5. Gate charge vs gate-source voltage 0 1 RDS(on) (mΩ) 12 67 10 65 8 63 300 6 61 200 4 59 100 2 57 Qg 500 0 0 GADG130720181134QVG VGS VDD = 480 V ID = 39 A VDS Qgd Qgs 10 20 30 40 50 60 0 Qg (nC) 2 3 4 5 6 7 8 9 VGS (V) Figure 6. Static drain-source on-resistance (V) 400 VDS = 19 V 80 VGS = 7 V 40 600 tp(s) 10 -1 120 60 VDS (V) -2 GADG110720180932TCH 100 80 10 140 100 0 0 10-3 ID (A) VGS = 9, 10 V 120 10-4 Figure 4. Transfer characteristics GADG110720180932OCH 140 Single pulse -3 Figure 3. Output characteristics ID (A) 0.01 10 -2 10 10 -1 10 -1 DS12689 - Rev 2 GC18460_ZTH δ=0.5 55 0 GADG110720180933RID VGS = 10 V 6 12 18 24 30 36 ID (A) page 5/13 STWA48N60M6 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG110720180933CVR VGS(th) (norm.) 10 4 GADG210320171542VTH ID =250 A 1.1 CISS 10 3 1.0 0.9 10 2 COSS 0.8 f = 1 MHz 10 1 CRSS 0.7 10 10 -1 0 10 0 10 1 VDS (V) 10 2 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GADG110720180934RON 2.5 0.6 -75 V(BR)DSS (norm.) 1.05 1.5 1.00 1.0 0.95 0.5 0.9 -25 25 75 125 TJ (°C) Figure 11. Output capacitance stored energy EOSS (µJ) GADG110720180936EOS 1.0 16 0.9 12 0.8 8 0.7 4 0.6 DS12689 - Rev 2 300 400 500 600 VDS (V) -25 25 VSD (V) 20 200 TJ (°C) 75 125 TJ (°C) Figure 12. Source-drain diode forward characteristics 1.1 100 125 ID = 1 mA 0.85 -75 24 0 0 75 GADG210320171543BDV 1.10 VGS = 10 V 25 Figure 10. Normalized V(BR)DSS vs temperature 2.0 0.0 -75 -25 0.5 0 GADG110720180936SDF Tj = -50 °C Tj = 25 °C Tj = 150 °C 6 12 18 24 30 36 ISD (A) page 6/13 STWA48N60M6 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD RG VGS IG= CONST VGS + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12689 - Rev 2 page 7/13 STWA48N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12689 - Rev 2 page 8/13 STWA48N60M6 TO-247 long leads package information 4.1 TO-247 long leads package information Figure 19. TO-247 long leads package outline 8463846_2_F DS12689 - Rev 2 page 9/13 STWA48N60M6 TO-247 long leads package information Table 8. TO-247 long leads package mechanical data Dim. mm Min. Typ. Max. A 4.90 5.00 5.10 A1 2.31 2.41 2.51 A2 1.90 2.00 2.10 b 1.16 1.26 b2 3.25 b3 2.25 c 0.59 0.66 D 20.90 21.00 21.10 E 15.70 15.80 15.90 E2 4.90 5.00 5.10 E3 2.40 2.50 2.60 e 5.34 5.44 5.54 L 19.80 19.92 20.10 L1 DS12689 - Rev 2 4.30 P 3.50 Q 5.60 S 6.05 3.60 3.70 6.00 6.15 6.25 page 10/13 STWA48N60M6 Revision history Table 9. Document revision history Date Version 11-Jul-2018 1 Changes Initial release. Modified Table 1. Absolute maximum ratings, Table 4. On/off states and Table 5. Dynamic. 30-Oct-2018 2 Modified Figure 1. Safe operating area, Figure 5. Gate charge vs gate-source voltage, Figure 6. Static drain-source on-resistance, Figure 9. Normalized onresistance vs temperature, Figure 10. Normalized V(BR)DSS vs temperature and Figure 12. Source-drain diode forward characteristics. Minor text changes. DS12689 - Rev 2 page 11/13 STWA48N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 TO-247 long leads package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 DS12689 - Rev 2 page 12/13 STWA48N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12689 - Rev 2 page 13/13