IG
N
TSA1005
DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER
S
NOT FOR NEW DESIGN
P 10-bit, dual-channel A/D converter in deep
D
NC
NC
VCCBE
44 43 42
GNDBE
VCCBI
VCCBI
OEB
48 47 46 45
AVCC
INCMI
REFMI
index
corner
AVCC
E
PIN CONNECTIONS (top view)
REFPI
P
submicron CMOS technology, 20/40Msps
Single supply voltage: 2.5V
Independent supply for CMOS output stage
with 2.5V/3.3V capability
ENOB=9.67 @ 20Msps, ENOB=9.4 @
40Msps, Fin=10MHz
SFDR typically up to 62.5dB @ 40Msps,
Fin=10MHz.
1GHz analog bandwidth Track-and-Hold
Common clocking between channels
Multiplexed outputs
41 40 39 38 37
)
s
(
t
c
u
d
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r
(
P
t
c
e u
t
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l od
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b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
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r
P
(
t
e uc
t
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l od
o
s Pr
b
O te
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l
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s
b
P
P
P
35 D1
AGND 3
34 D2
INIB 4
33 D3
32 D4
IPOL 6
31 D5
29 D7
28 D8
AGND 10
27 D9(MSB)
INBQ 11
26 VCCBE
25 GNDBE
AGND 12
13
14 15 16
R
F
T
O
N
GNDBI
DVCC
DGND
SELECT
CLK
CLK
SELECT OEB
VCCBE
Timing
VINI
AD 10
I channel
VINBI
VINCMI
VREFPI
common mode
REF I
VREFMI
IPOL
10
M
U
X
Polar.
VREFPQ
VREFMQ
10
10
Buffers
D0
TO
D9
REF Q
common mode
AD 10
Q channel
10
GNDBE
PACKAGE
Status
Conditioning
TSA1005-20IF
-40 C to +85 C
Sample
Tray
TSA1005-20IFT
-40 C to +85 C
Sample
Tape & Reel
TSA1005I-40IF
0 C to +85 C
Production
Tray
TSA1005-40IFT
0 C to +85 C
Production
Tape & Reel
April 2004
23 24
GND
Temperature
Range
EVAL1005-20/BA
EVAL1005-40/BA
DGND
+2.5V/3.3V
VINQ
VINBQ
ORDER CODE
Part Number
DVCC
O
Medical imaging and ultrasound
I/Q signal processing applications
High speed data acquisition system
Portable instrumentation
High resolution fax and scanners
AVCC
AGND
INCMQ
P
P
P
P
P
17 18 19 20 21 22
BLOCK DIAGRAM
VINCMQ
APPLICATIONS
30 D6
INQ 9
REFMQ
O
TSA1005
AGND 8
REFPQ
The TSA1005 belongs to a new generation of high
speed, dual-channel Analog to Digital converters,
processed in a mainstream 0.25 µm CMOS technology and yielding high performances.
The TSA1005 is specifically designed for applications requiring a very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction,
providing high static linearity at 20/40 Msp, and
Fin = 10 MHz.
For each channel, a voltage reference is integrated to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC output is multiplexed on a common bus
with small number of pins. A tri-state capability is
available for the output signals, allowing for chip
selection. The input signals of the ADC must be
differentially driven.
The TSA1005 is supports an extended (0 to
+85 C) temperature range, and is available in the
small 48-pin TQFP package.
AGND 5
AVCCB 7
N
DESCRIPTION
2
INI
W
P
36 D0(LSB)
AGND 1
E
P
7 × 7 mm TQFP48
Evaluation board
1/22
TSA1005
ABSOLUTE MAXIMUM RATINGS
AVCC
Analog Supply voltage (1)
DVCC
Digital Supply voltage 1)
ESD
Digital buffer Supply voltage
Digital output current
Storage temperature
HBM: Human Body Model(2)
CDM: Charged Device Model
Unit
0 to 3.3
V
0 to 3.3
V
0 to 3.6
V
0 to 3.3
V
-100 to 100
+150
mA
C
S
IDout
Tstg
1)
E
VCCBI
Digital buffer Supply voltage
(3)
2
kV
1.5
D
VCCBE
1)
Values
N
Parameter
IG
Symbol
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
Latch-up Class(4)
A
E
W
1 All voltage values, except for differential voltage, are with respect to the network ground terminal. The magnitude of input and output voltages must not exceed -0.3 V or VCC
2 ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ
3 Discharge to Ground of a device that has been previously charged.
4 Corporate ST Microelectronics procedure number 0018695
Parameter
R
Symbol
Analog Supply voltage
Digital Supply voltage
External Digital buffer Supply voltage
Internal Digital buffer Supply voltage
F
O
AVCC
DVCC
VCCBE
VCCBI
VREFPI
Forced top voltage reference
T
VREFPQ
VREFMI
O
VREFMQ
INCMI
N
INCMQ
O
2/22
N
OPERATING CONDITIONS
Forced bottom reference voltage
Forced input common mode voltage
TSA1005-20(1)
TSA1005-40
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
2.25
2.25
2.25
2.25
2.5
2.5
2.5
2.5
2.7
2.7
3.5
2.7
2.25
2.25
2.25
2.25
2.5
2.5
2.5
2.5
2.7
2.7
3.5
2.7
V
V
V
V
0.94
1.4
0.94
1.4
V
0
0.4
0
0.4
V
0.2
1
0.2
1
V
TSA1005
41 40 39 38 37
36 D0(LSB)
AGND 1
35 D1
AGND 3
34 D2
INIB 4
33 D3
E
S
2
INI
IG
NC
NC
VCCBE
GNDBE
44 43 42
VCCBI
VCCBI
47 46 45
OEB
AVCC
AVCC
48
INCMI
REFMI
REFPI
index
corner
N
PIN CONNECTIONS (top view)
AGND 5
IPOL 6
D
32 D4
31 D5
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
TSA1005
AVCCB 7
AGND 8
INQ 9
AGND 12
R
GNDBI
DVCC
DGND
SELECT
CLK
O
1
AGND
2
INI
3
AGND
4
INBI
5
AGND
6
IPOL
Analog bias current input
AVCC
Analog power supply
AGND
Analog ground
Description
F
Analog ground
Observation
Pin No
Name
25
GNDBE
Digital buffer ground
0V
26
VCCBE
Digital Buffer power supply
2.5V/3.3V
27
D9(MSB)
Most Significant Bit output
CMOS output (2.5V/3.3V)
28
D8
Digital output
CMOS output (2.5V/3.3V)
29
D7
Digital output
CMOS output (2.5V/3.3V)
30
D6
Digital output
CMOS output (2.5V/3.3V)
2.5V
31
D5
Digital output
CMOS output (2.5V/3.3V)
0V
32
D4
Digital output
CMOS output (2.5V/3.3V)
33
D3
Digital output
CMOS output (2.5V/3.3V)
34
D2
Digital output
CMOS output (2.5V/3.3V)
0V
I channel analog input
Analog ground
0V
I channel inverted analog input
T
O
26 VCCBE
25 GNDBE
DGND
DVCC
AVCC
Name
N
27 D9(MSB)
17 18 19 20 21 22 23 24
AGND
O
INCMQ
Pin No
8
REFMQ
REFPQ
PIN DESCRIPTION
7
14 15 16
N
13
E
INBQ 11
29 D7
28 D8
W
AGND 10
30 D6
Analog ground
9
INQ
10
AGND
Analog ground
11
INBQ
Q channel inverted analog input
12
AGND
Analog ground
0V
Q channel analog input
0V
0V
Description
35
D1
36
D0(LSB)
37
NC
Non connected
38
NC
Non connected
39
VCCBE
Digital Buffer power supply
Observation
Digital output
CMOS output (2.5V/3.3V)
Least Significant Bit output
CMOS output (2.5V/3.3V)
13
REFPQ
Q channel top reference voltage
14
REFMQ
Q channel bottom reference
voltage
15
INCMQ
Q channel input common mode
16
AGND
Analog ground
0V
40
GNDBE
Digital buffer ground
0V
17
AVCC
Analog power supply
2.5V
41
VCCBI
Digital Buffer power supply
2.5V
18
DVCC
Digital power supply
2.5V
42
VCCBI
Digital Power Supply
2.5V
19
DGND
Digital ground
0V
43
OEB
Output Enable input
2.5V/3.3V CMOS input
20
CLK
Clock input
2.5V CMOS input
44
AVCC
Analog power supply
2.5V
21
SELECT
Channel selection
2.5V CMOS input
45
AVCC
Analog power supply
2.5V
22
DGND
Digital ground
0V
46
INCMI
I channel input common mode
23
DVCC
Digital power supply
2.5V
47
REFMI
I channel bottom reference voltage 0V
24
GNDBI
Digital buffer ground
0V
48
REFPI
I channel top reference voltage
0V
2.5V/3.3V - See Application
Note
3/22
TSA1005
N
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5 V, Fs = 20/40 Msps, Fin = 10.13 MHz, Vin@ -1 dBFS, VREFP = 0.8 V,
VREFM = 0 V
IG
Tamb = 25 C (unless otherwise specified)
TIMING CHARACTERISTICS
TSA1005-20(1)
S
TSA1005-40
Parameter.
Min.
Sampling Frequency
0.5
Max.
Min.
20
0.5
D
FS
Typ.
E
Symbol
Typ.
Max.
Unit
40
MHz
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
Clock Duty Cycle
50
TC1
Clock pulse width (high)
25
12.5
ns
TC2
Clock pulse width (low)
25
12.5
ns
Tod
Data Output Delay (Clock edge to Data
Valid) - 10pF load capacitance
5
5
ns
Data Pipeline delay for Q channel
E
Data Pipeline delay for I channel
N
Tpd I
Tpd Q
W
DC
45
50
55
7
7
cycles
7.5
7.5
cycles
Falling edge of OEB to digital output
valid data
1
1
ns
Toff
Rising edge of OEB to digital output
tri-state
1
1
ns
R
Ton
O
1 Preliminary data.
F
TIMING DIAGRAM
T
Simultaneous sampling
on I/Q channels
N+4
O
N+3
N
N
N+13
N+12
N+11
N+7
N+2
N-1
N+5
N+6
I
N+1
N+8
N+9
Q
N+10
CLK
Tpd I + Tod
Tod
SELECT
CLOCK AND SELECT CONNECTED TOGETHER
O
OEB
sample N-8
I channel
sample N-6
Q channel
sample N
Q channel
sample N+1
Q channel
sample N+2
Q channel
DATA
OUTPUT
sample N-9
I channel
4/22
%
sample N-7
Q channel
sample N+1 sample N+2
I channel
I channel
sample N+3
I channel
TSA1005
N
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V
Tamb = 25 C (unless otherwise specified)
TSA1005-20(1)
Full scale reference voltage
Input capacitance
Equivalent input resistor
Analog Input Bandwidth
Min.
Typ.
Max.
1.1
2.0
7.0
3.3
2.8
Min.
Typ.
Max.
Unit
1.1
2.0
7
1.6
2.8
Vpp
pF
KΩ
D
VIN-VINB
Cin
Req
TSA1005-40
S
Parameter
E
Symbol
IG
ANALOG INPUTS
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
BW
Vin Full scale, Fs max
Effective Resolution Bandwidth
ERB
Parameter
Logic "1" voltage
Min
2.0
O
OEB input
Logic "0" voltage
VIH
Logic "1" voltage
Digital Outputs
Logic "0" voltage
Iol=10µA
VOH
Logic "1" voltage
IOZ
High Impedance leakage current OEB set to VIH
CL
Output Load Capacitance
T
Max
Unit
0
0.8
V
2.5
V
0.25 x
VCCBE
0.75 x VCCBE
VCCBE
VOL
0
Ioh=10µA
O
Typ
0
F
VIL
N
MHz
N
VIH
70
R
Logic "0" voltage
70
Test conditions
Clock and Select inputs
VIL
MHz
E
DIGITAL INPUTS AND OUTPUTS
Symbol
1000
W
1 Preliminary data
1000
V
V
0.1 x
VCCBE
0.9 x VCCBE
VCCBE
-1.67
0
V
V
1.67
µA
15
pF
REFERENCE VOLTAGE
Symbol
VREFPI
O
VREFPQ
VINCMI
VINCMQ
Parameter
TSA1005-20(1)
TSA1005-40
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Top internal reference voltage
0.81
0.88
0.94
0.81
0.88
0.94
V
Input common mode voltage
0.41
0.46
0.50
0.41
0.46
0.50
V
5/22
TSA1005
N
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V
Tamb = 25 C (unless otherwise specified)
TSA1005-20(1)
Min.
Typ.
Analog Supply current
30
Digital Supply Current
4
Digital Buffer Supply Current (10pF
load)
6
ICCBE
Max.
Min.
D
ICCA
ICCD
TSA1005-40
S
Parameter
E
Symbol
IG
POWER CONSUMPTION
Typ.
Max.
Unit
69.5
77.1
mA
3.5
3.77
mA
6.5
7.66
mA
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
Pd
Rthja
Digital Buffer Supply Current
274
131
176
µA
Power consumption in normal operation mode
100
199.5
218.6
mW
80
80
TSA1005-20(1)
TSA1005-40
Thermal resistance (TQFP48)
C/W
Symbol
Parameter
N
E
ACCURACY
W
ICCBI
Offset Error
GE
Gain Error
DNL
Differential Non Linearity
INL
-
Integral Non Linearity
Monotonicity and no missing codes
Typ.
O
R
OE
Min.
Max.
Min.
Typ.
Unit
2.97
2.97
LSB
0.1
0.1
%
±0.5
±0.6
LSB
±0.7
Guaranteed
F
Max.
±1
Guaranteed
LSB
O
Symbol
T
DYNAMIC CHARACTERISTICS
N
SFDR
SNR
THD
SINAD
ENOB
TSA1005-20(1)
Symbol
Min.
Spurious Free Dynamic Range
Typ.
Max.
TSA1005-40
Min.
-73
Max.
Unit
-62.6
-58.1
dBc
-57.5
dBc
Signal to Noise Ratio
60
Total Harmonics Distortion
-73
Signal to Noise and Distortion Ratio
59
54.9
57.3
dB
9.67
8.8
9.4
bits
Effective number of bits
57.1
Typ.
59.8
-62
dB
MATCHING BETWEEN CHANNELS
Symbol
Parameter
TSA1005-20(1)
Min.
O
GM
Typ.
Max.
TSA1005-40
Typ.
Max.
Unit
Gain match
0.04
Min.
0.04
1
%
OM
Offset match
0.5
0.5
LSB
PHM
Phase match
1
1
dg
XTLK
Crosstalk rejection
85
85
dB
1 Preliminary data
6/22
TSA1005
Static parameter: Integral Non Linearity
N
Fs=20MSPS; Icca=30mA; Fin=10MHz
IG
1
0.4
S
0.2
0
-0.2
E
INL (LSBs)
0.8
0.6
-0.4
D
-0.6
-0.8
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
-1
0
200
400
600
800
1000
Static parameter: Integral Non Linearity
N
Fs=40MSPS; Icca=45mA; Fin=10MHz
E
W
Output Code
2
R
1.5
O
0.5
0
-0.5
F
INL (LSBs)
1
-1
T
-1.5
-2
200
400
O
0
600
800
1000
N
Output Code
Static parameter: Differential Non Linearity
Fs=20MSPS; Icca=30mA; Fin=10MHz
1
0.8
O
DNL (LSBs)
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
200
400
600
800
1000
Output Code
7/22
TSA1005
Static parameter: Differential Non Linearity
IG
N
Fs=40MSPS; Icca=45mA; Fin=10MHz
1
0.8
S
0.4
0.2
0
E
DNL (LSBs)
0.6
-0.2
-0.4
D
-0.6
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
(
t
e uc
t
e
l od
o
s Pr
b
O te
e
l
o
s
b
-0.8
-1
200
400
600
800
1000
W
0
N
Linearity vs. Fin
Fs=20MHz; Icca=30mA
ENOB_Q
O
80
70
10
SINAD_Q
F
SNR_Q
60
50
SNR_I
40
O
30
9
8
7
SINAD_I
6
40
-80
-100
20
40
8
SNR_Q
SINAD_Q
7
60
6
50
SINAD_I
5
40
30
4
20
40
Fin (MHz)
60
Dynamic parameters (dBc)
ENOB_Q
80
70
60
Distortion vs. Fin
Fs=40MHz; Icca=45mA
9
ENOB_I
SFDR_Q
Fin (MHz)
90
0
THD_Q
-120
10
SNR_I
SFDR_I
THD_I
-60
0
ENOB (bits)
Dynamic parameters (dB)
-40
Fin (MHz)
100
8/22
-20
60
Linearity vs. Fin
Fs=40MHz; Icca=45mA
O
0
-140
5
20
N
0
11
ENOB_I
ENOB (bits)
90
R
12
T
Dynamic parameters (dB)
100
Distortion vs. Fin
Fs=20MHz; Icca=30mA
Dynamic parameters (dBc)
E
Output Code
0
-20
-40
THD_I
SFDR_I
-60
-80
SFDR_Q
THD_Q
-100
-120
0
20
40
Fin (MHz)
60
TSA1005
Linearity vs. AVCC
Fs=20MSPS; Icca=30mA; Fin=5MHz
9.4
70
9.2
65
SNR_Q
9
SINAD_Q
8.8
60
8.6
SINAD_I
8.4
SNR_I
IG
9.6
-50
-70
-80
-90
-100
SFDR_Q
THD_Q
-60
S
ENOB_Q
-40
E
ENOB_I
-30
THD_I
SFDR_I
D
9.8
75
ENOB (bits)
Dynamic parameters (dB)
Dynamic Parameters (dBc)
10
80
N
Distortion vs. AVCC
Fs=20MSPS; Icca=30mA; Fin=5MHz
)
s
(
t
c
u
d
o s)
r
(
P
t
c
e u
t
e
l od
o
s Pr
b
O ete
l
)
o
s
(
s
t
b
c
u -O
d
o s)
r
P
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8.2
-120
2.25
8
2.35
2.45
2.55
2.65
E
AVCC (V)
10
SNR_Q
60
50
8
7.5
SINAD_Q
7
6.5
6
SNR_I
SINAD_I
2.45
5.5
2.55
2.55
2.65
AVCC (V)
Distortion vs. AVCC
-30
-40
-50
2.65
SFDR_Q
THD_Q
-60
-70
-80
SFDR_I
-90
THD_I
-100
-110
-120
2.25
5
2.35
2.45
2.35
2.45
2.55
2.65
AVCC (V)
AVCC (V)
N
O
40
2.25
9
8.5
F
70
ENOB_I
O
ENOB_Q
80
9.5
ENOB (bits)
R
90
T
Dynamic parameters (dB)
100
2.35
Fs=40MSPS; Icca=45mA; Fin=5MHz
N
Linearity vs. AVCC
Fs=40MSPS; Icca=45mA; Fin=5MHz
-110
W
50
2.25
Dynamic Parameters (dBc)
55
Linearity vs. DVCC
Fs=20MSPS; Icca=30mA; Fin=10MHz
ENOB_Q
ENOB_I
9.6
9.4
70
9.2
65
SNR_Q
9
SNR_I
8.8
60
55
8.6
SINAD_I
8.4
SINAD_Q
8.2
50
2.25
8
2.35
2.45
DVCC (V)
2.55
2.65
ENOB (bits)
Dynamic parameters (dB)
9.8
75
Dynamic Parameters (dBc)
10
80
O
Distortion vs. DVCC
Fs=20MSPS; Icca=30mA; Fin=10MHz
-40
-50
-60
THD_Q
SFDR_Q
-70
-80
-90
THD_I
SFDR_I
-100
-110
-120
2.25
2.35
2.45
2.55
2.65
DVCC (V)
9/22
TSA1005
8.5
80
8
7.5
70
SINAD_Q
SNR_Q
7
60
6.5
SNR_I
SINAD_I
ENOB (bits)
9
ENOB_I
6
N
IG
ENOB_Q
-20
-40
SFDR_I
S
9.5
90
0
SFDR_Q
-60
-80
-100
E
Dynamic Parameters (dBc)
10
100
Dynamic parameters (dB)
Distortion vs. DVCC
Fs=40MSPS; Icca=45mA; Fin=10MHz
THD_I
THD_Q
D
Linearity vs. DVCC
Fs=40MSPS; Icca=45mA; Fin=10MHz
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-120
2.25
5
2.35
2.45
2.55
2.65
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Linearity vs. VCCBI
Fs=20MSPS; Icca=30mA; Fin=10MHz
E
DVCC (V)
10
75
F
70
65
9
8.8
8.6
60
55
8.4
SINAD_I
2.35
8.2
SINAD_Q
2.55
2.55
2.65
DVCC (V)
Distortion vs. VCCBI
Fs=20MSPS; Icca=30mA; Fin=10MHz
-40
-50
2.65
THD_Q
-60
SFDR_Q
-70
-80
-90
SFDR_I
THD_I
-100
-110
-120
2.25
8
2.45
2.45
2.35
2.45
2.55
2.65
VCCBI (V)
VCCBI (V)
N
O
50
2.25
9.6
9.2
SNR_Q
SNR_I
9.8
9.4
O
80
ENOB_Q
ENOB (bits)
R
ENOB_I
T
Dynamic parameters (dB)
90
85
2.35
W
40
2.25
Dynamic Parameters (dBc)
50
10
9.5
85
ENOB_I
9
ENOB_Q
8.5
75
8
70
7.5
65
SINAD_Q
7
SNR_Q
6.5
60
55
50
2.25
6
SINAD_I
5.5
SNR_I
5
2.35
2.45
2.55
VCCBI (V)
10/22
2.65
ENOB (bits)
O
Dynamic parameters (dB)
90
80
Distortion vs. VCCBI
Fs=40MSPS; Icca=45mA; Fin=10MHz
Dynamic Parameters (dBc)
Linearity vs. VCCBI
Fs=40MSPS; Icca=45mA; Fin=10MHz
-40
-50
THD_Q
-60
SFDR_Q
-70
-80
-90
THD_I
SFDR_I
-100
-110
-120
2.25
2.35
2.45
VCCBI (V)
2.55
2.65
TSA1005
ENOB_I
9.6
ENOB_Q
9.4
75
9.2
70
9
65
8.8
SNR_I
SINAD_I
8.6
60
8.4
SNR_Q
THD_Q
-65
-70
-75
-80
-85
-90
SFDR_Q
THD_I
SFDR_I
D
80
N
9.8
IG
85
-60
S
10
E
90
Dynamic Parameters (dBc)
Distortion vs. VCCBE
Fs=20MSPS; Icca=30mA; Fin=10MHz
ENOB (bits)
Dynamic parameters (dB)
Linearity vs. VCCBE
Fs=20MSPS; Icca=30mA; Fin=10MHz
-95
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SINAD_Q
8.2
50
2.8
1.8
3.3
10
90
9.8
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70
9.2
65
F
SNR_I
60
9
8.8
SINAD_I
8.6
ENOB (bits)
9.4
ENOB_I
75
9.6
ENOB_Q
O
80
8.4
55
SINAD_Q
O
50
2.25
T
SNR_Q
8.2
N
80
9
75
70
8.5
SINAD_I
8
60
55
7.5
SINAD_Q
SNR_Q
50
7
47
49
51
53
Positive Duty Cycle (%)
55
Dynamic parameters (dBc)
9.5
ENOB_Q
ENOB (bits)
Dynamic parameters (dB)
-70
-80
THD_I
-90
SFDR_I
-100
-110
2.75
3.25
-40
10
SNR_I
SFDR_Q
THD_Q
-60
Distortion vs. Duty Cycle
Fs=20MHz; Icca=30mA; Fin=5MHz
85
45
-50
VCCBE (V)
90
65
-40
VCCBE (V)
Linearity vs. Duty Cycle
Fs=20MHz; Icca=30mA; Fin=5MHz
O
-30
-120
2.25
3.25
ENOB_I
3.3
Distortion vs. VCCBE
Fs=40MSPS; Icca=45mA; Fin=10MHz
8
2.75
2.8
VCCBE (V)
Dynamic Parameters (dBc)
E
N
Linearity vs. VCCBE
Fs=40MSPS; Icca=45mA; Fin=10MHz
85
2.3
W
2.3
VCCBE (V)
Dynamic parameters (dB)
-100
8
1.8
-50
SFDR_Q
-60
THD_Q
-70
-80
-90
SFDR_I
THD_I
-100
-110
-120
45
47
49
51
53
55
Positive Duty Cycle (%)
11/22
TSA1005
Distortion vs. Duty Cycle
Fs=40MHz; Icca=45mA; Fin=5MHz
8.5
80
8
70
SNR
7.5
SINAD
7
60
6.5
ENOB (bits)
9
ENOB
6
-50
SFDR
-60
-70
S
90
-80
THD
E
9.5
-90
-100
D
Dynamic parameters (dBc)
Dynamic parameters (dB)
-40
10
100
IG
N
Linearity vs. Duty Cycle
Fs=40MHz; Icca=45mA; Fin=5MHz
)
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50
5.5
40
5
47
49
51
53
-120
55
W
45
-110
47
49
51
53
Positive Duty Cycle (%)
E
Positive Duty Cycle (%)
45
N
Single-tone 8K FFT at 24.8Msps - Q Channel
Fin=10MHz; Icca=30mA, Vin@-1dBFS
R
-20
-40
O
-60
-80
-100
-120
F
Power spectrum (dB)
0
T
-140
4
O
2
6
8
10
12
Frequency (MHz)
N
Single-tone 8K FFT at 39.7Msps - Q Channel
Fin=10MHz; Icca=45mA, Vin@-1dBFS
O
Power spectrum (dB)
0
-20
-40
-60
-80
-100
-120
-140
2
4
6
8
10
12
Frequency (MHz)
12/22
14
16
18
20
55
TSA1005
IG
S
Signal to Noise and Distortion Ratio (SINAD)
Similar ratio as for SNR but including the
harmonic distortion components in the noise
figure (not DC signal). It is expressed in dB.
E
Differential Non Linearity (DNL)
The average deviation of any output code width
from the ideal code width of 1 LSB.
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
D
STATIC PARAMETERS
Static measurements are performed using a
histogram method with on a 2 MHz input signal,
sampled at 40 Msps, which is high enough to fully
characterize the test frequency response. An
input level of +1 dBFS is required to saturate the
signal.
N
DEFINITIONS OF SPECIFIED PARAMETERS
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N
E
W
Integral Non linearity (INL)
An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERS
O
R
Dynamic measurements are performed by
spectral analysis, applied to an input sine wave of
various frequencies and sampled at 40 Msps.
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD2Ao = SINADFull Scale+ 20 log (2A0/FS)
SINAD2Ao = 6.02 × ENOB + 1.76dB + 20 log (2A0/FS)
The ENOB is expressed in bits.
Analog Input Bandwidth
The maximum analog input frequency at which
the spectral response of a full power signal is
reduced by 3 dB. Higher values can be achieved
with smaller input levels.
Spurious Free Dynamic Range (SFDR)
The ratio between the power of the worst spurious
signal (not always an harmonic) and the amplitude
of fundamental tone (signal power) over the full
Nyquist band. It is expressed in dBc.
Effective Resolution Bandwidth (ERB)
The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
N
O
T
F
The input level is -1 dBFS to measure the linear
behavior of the converter. All the parameters are
given without correction for the full scale
amplitude performance except the calculated
ENOB parameter.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
Signal to Noise Ratio (SNR)
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
O
Pipeline delay
Delay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the output bus. Also called
data latency. It is expressed as a number of clock
cycles.
13/22
S
IG
N
TSA1005 APPLICATION NOTE
and enables to keep the same package as single
channel ADC like TSA1002.
D
The TSA1005 is a dual-channel, 10-bit resolution
analog to digital converter based on a pipeline
structure and the latest deep sub micron CMOS
process to achieve the best performances in
terms of linearity and power consumption.
Each channel achieves 10-bit resolution through
the pipeline structure. A latency time of 7 clock periods is necessary to obtain the digitized data on
the output bus.
The input signals are simultaneously sampled on
both channels on the rising edge of the clock. The
output data is valid on the rising edge of the clock
for I channel and on the falling edge of the clock
for Q channel. The digital data out from the different stages must be time delayed depending on
their order of conversion. Then a digital data correction completes the processing and ensures the
validity of the ending codes on the output bus.
The structure has been specifically designed to
accept differential signals.
The TSA1005 is pin to pin compatible with the
dual 12bits/20Msps TSA1204 and the dual 12bits/
40Msps TSA1203.
E
DETAILED INFORMATION
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E
W
The selection of the channel information is done
through the "SELECT" pin. When set to high level
(VIH), the I channel data are present on the bus
D0-D9. When set to low level (VIL), the Q channel
data are on the output bus D0-D9.
O
COMPLEMENTARY FUNCTIONS
N
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described as
followed.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a
low level again, the data are then present on the
output with a very short Ton delay.
Therefore, this allows the chip select of the device.
The timing diagram summarizes this functionality.
In order to remain in the normal operating mode,
this pin should be grounded through a low value of
resistor.
O
SELECT
Connecting SELECT to CLK allows I and Q channels to be simultaneously present on D0-D9; I
channel on the rising edge of the clock and Q
channel on the falling edge of the clock. (see timing diagram page 2).
REFERENCES AND COMMON MODE
CONNECTION
VREFM must be always connected externally.
Internal reference and common mode
In the default configuration, the ADC operates with
its own reference and common mode voltages
generated by its internal bandgap. VREFM pins
are connected externally to the Analog Ground
while VREFP (respectively INCM) are set to their
internal voltage of 0.88V (respectively 0.46V). It is
recommended to decouple the VREFP and INCM
in order to minimize low and high frequency noise
(refer to Figure 1)
Figure 1: Internal reference and common mode
setting
330pF 10nF
VIN
4.7uF
VREFP
TSA1005
VINB
INCM
330pF 10nF
4.7uF
VREFM
The digital data out from each ADC core are multiplexed together to share the same output bus.
This prevents from increasing the number of pins
14/22
TSA1005
N
S
IG
Each analog input can drive a 1.4Vpp amplitude
input signal, so the resultant differential amplitude
is 2.8Vpp.
Figure 3: Differential input configuration with
transformer
E
Each of the voltages VREFP and INCM can be
fixed externally to better fit to the application
needs
(Refer
to
table
íOPERATING
CONDITIONSí page 4 for min/max values).
The VREFP, VREFM voltages set the analog
dynamic at the input of the converter that has a full
scale amplitude of 2*(VREFP-VREFM). Using
internal references, the dynamic range is 1.8V.
The INCM is the mid voltage of the analog input
signal.
It is possible to use an external reference voltage
device for specific applications requiring even
better
linearity,
accuracy
or
enhanced
temperature behavior.
Using the STMicroelectronics TS821 or
TS4041-1.2 Vref leads to optimum performances
when configured as shown on Figure 2.
1:4) to reduce the driving requirement on the
analog signal source.
Analog source
ADT1-1
1:1
VIN
D
External reference and common mode
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50Ω
33pF
W
VINB
INCM
E
330pF
10nF
470nF
N
Figure 2: External reference setting
TSA1005
I or Q ch.
R
1kΩ
330pF 10nF 4.7uF
TSA1005
VINB
external
reference
Figure 4: AC-coupled differential input
O
T
F
VREFM
TS821
TS4041
O
VCCA VREFP
VIN
Figure 4 represents the biasing of a differential
input signal in AC-coupled differential input
configuration. Both inputs VIN and VINB are
centered around the common mode voltage, that
can be let internal or fixed externally.
N
DRIVING THE DIFFERENTIAL ANALOG
INPUTS
The TSA1005 has been designed to obtain
optimum performances when being differentially
driven. An RF transformer is a good way to
achieve such performances.
Figure 3 describes the schematics. The input
signal is fed to the primary of the transformer,
while the secondary drives both ADC inputs. The
common mode voltage of the ADC (INCM) is
connected to the center-tap of the secondary of
the transformer in order to bias the input signal
around this common voltage, internally set to
0.46V. It determines the DC component of the
analog signal. As being an high impedance input,
it acts as an I/O and can be externally driven to
adjust this DC component. The INCM is
decoupled to maintain a low noise level on this
node. Our evaluation board is mounted with a 1:1
ADT1-1WT transformer from Minicircuits. You
might also use a higher impedance ratio (1:2 or
O
15/22
50Ω
VIN
10nF
100kΩ
33pF
common
mode
50Ω
INCM
100kΩ
TSA1005
VINB
10nF
Figure 5: AC-coupled Single-ended input
Signal source
10nF
VIN
100kΩ
50Ω
INCM
33pF
TSA1005
100kΩ
VINB
Clock input
APPLICATION
The TSA1005 performance is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
Layout precautions
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
IG
S
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The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is recommended for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is mandatory to prevent noise from
coupling onto the input signal. The best
compromise is to connect from one part AGND,
DGND, GNDBI in a common point whereas
GNDBE must be isolated. Similarly, the power
supplies AVCC, DVCC and VCCBI must be
separated from the VCCBE one.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
D
The duty cycle must be between 45% and 55%.
N
TSA1005
W
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Power consumption
R
N
So as to optimize both performance and power
consumption of the TSA1005 according the
sampling frequency, a resistor is placed between
IPOL and the analog Ground pins. Therefore, the
total dissipation is adjustable from 5Msps up to
40Msps.
F
O
The TSA1005 will combine highest performances
and lowest consumption at 20Msps when Rpol is
equal to 70kΩ, at 40Msps when Rpol is equal to
35kΩ. These values are nevertheless dependant
on application and environment.
O
T
At lower sampling frequency range, this value of
resistor may be adjusted in order to decrease the
analog current without any degradation of
dynamic performances.
N
The figure 6 sums up the relevant data.
Figure 6: analog current consumption
optimization depending on Rpol value
Digital Interface application
100
250
90
200
70
60
150
ICCA
50
40
100
30
20
50
10
RPOL
0
0
5
15
25
35
Fs (MHz)
45
55
Rpol (kOhms)
O
Icca (mA)
80
Thanks to its wide external buffer power supply
range, the TSA1005 is perfectly suitable to plug in
to 2.5V low voltage DSPs or digital interfaces as
well as to 3.3V ones.
Medical Imaging application
Driven by the demand of the applications requiring
nowadays either portability or high degree of parallelism (or both), this product has been developed to satisfy medical imaging, and telecom infrastructures needs.
As a typical system diagram shows figure 10, a
narrow input beam of acoustic energy is sent into
a living body via the transducer and the energy reflected back is analyzed.
16/22
TSA1005
Figure 7: Medical imaging application
N
noise and very high linearity are mandatory factors.
These applications need high speed, low power
and high performance ADCs. 10-12 bit resolution
is necessary to lower the quantification noise. As
multiple channels are used, a dual converter is a
must for room saving issues.
The input signal is in the range of 2 to 20MHz
(mainly 2 to 7MHz) and the application uses mostly a 4 over-sampling ratio for Spurious Free Dynamic Range (SFDR) optimization.
The next RX beam former and processing blocks
enable the analysis of the outputs channels versus the input beam.
IG
HV TX amps
Mux
and
S
TX
RX
E
AD
D
TGC amplifier
)
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Proces
EVAL1005/BA evaluation board
W
The EVAL1005/BA is a 4-layer board with high
decoupling and grounding level. The schematic of
the evaluation board is reported figure 11 and its
top overlay view figure 10.The characterization of
the board has been made with a fully ADC
devoted test bench as shown on Figure 8. The
analog input signal must be filtered to be very
pure.
The dataready signal is the acquisition clock of the
logic analyzer.
The ADC digital outputs are latched by the octal
buffers 74LCX573.
All characterization measurements have been
made with:
- SFSR=1dB for static parameters.
- SFSR=-1dB for dynamic parameters.
F
O
R
N
E
The transducer is a piezoelectric ceramic such as
zirconium titanate. The whole array can reach up
to 512 channels.
The TX beam former, amplified by the HV TX
amps, delivers up to 100V amplitude excitation
pulses with phase and amplitude shifts.
The mux and T/R switch is a two way input signal
transmitter/ output receiver.
To compensate for skin and tissues attenuation
effects, The Time Gain Compensation (TGC) amplifier is an exponential amplifier that enables the
amplification of low voltage signals to the ADC input range. Differential output structure with low
N
O
T
Figure 8: Analog to Digital Converter characterization bench
HP8644
Sine Wave
Generator
Data
Vin
ADC
evaluation
Logic
Clk
Clk
O
17/22
HP8133
Pulse
HP8644
Sine Wave
Generator
PC
TSA1005
external
voltage (V)
AV
AVCC
2.5
AG
AGND
0
RPI
REFPI
0.88
Mode select
S
internal
voltage (V)
So as to evaluate a single channel or the dual
ones, you have to connect on the board the
relevant position for the SELECT pin.
With the strap connected:
- to the upper connectors, the I channel at the output is selected.
- horizontally, the Q channel at the output is selected.
- to the lower connectors, both channels are selected, relative to the clock edge.
E
connection
notation
So as to better reject noise on the board, connect
on the bottom overlay AG (AGND), DG(DGND),
GB1(GNDBI) together from one part, and
GB2(GNDBE) with GB3(GNDB3) from the other
part.
0.94 to 1.4
D
board
Grounding consideration
IG
Find below the connections to the board for the
power supplies and other pins:
N
Operating conditions of the evaluation board:
)
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RMI
REFMI
CMI
INCMI
0.46
0.2 to 1
RPQ
REFPQ
0.88
0.94 to 1.4
RMQ
REFMQ
CMQ
INCMQ
DV
DVCC
DG
DGND
GB1
GNDBI
VB1
VCCBI
GB2
GNDBE
VB2
VCCBE
GB3
GNDB3
0
VB3
VCCB3
2.5
0.46
E
0 to 0.4
W
0 to 0.4
0.2 to 1
N
2.5
Figure 9: mode select
T
F
O
R
0
SELECT
0
I channel
2.5
SELECT
0
Q channel
2.5/3.3
N
O
Care should be taken for the evaluation board
considering the fact that the outputs of the converter are 2.5V/3.3V (VB2) tolerant whereas the
74LCX573 external buffers are operating up to
2.5V.
The ADC outputs on the connector J6 are D11
(MSB) to D2 (LSB).
I/Q channels
CLK
DGND DVCC
schematic
board
Consumption adjustment
Before any characterization, care should be taken
to adjust the Rpol (Raj1) and therefore Ipol value
in function of your sampling frequency.
Single and Differential Inputs:
The ADC board components are mounted to test
the TSA1005 with single analog input; the
ADT1-1WT transformer enables the differential
drive into the converter; in this configuration, the
resistors RSI6, RSI7, RSI8 for I channel (respectively RSQ6, RSQ7, RSQ8 for Q one) are connected as short circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9) are open circuits.
The other way is to test it via JI1 and JI1B differential inputs. So, the resistances RSI5, RSI9 for I
channel (respectively RSQ5, RSQ9 for Q one) are
connected as short circuits whereas RSI6, RSI7,
RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q
one) are open circuits.
O
18/22
TSA1005
D
E
S
IG
N
Figure 10: Printed circuit of evaluation board.
N
O
T
F
O
R
N
E
W
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19/22
Fµ74
2BCCV
53C
Fn074 91C
CCVD
3R
1WS
05
KLC
4J
Fn001
5C
GV
Fp033 01C
Fn01 11C
Fµ01 32C
Fµ74 63C
Fn074 22C
CCVD Fn01 12C
Fn074 31C CCVA
Fµ01 13C
Fµ74 23C
DJ N C
LATIGID D C
2NOC
1
2
72J
Fp033 02C
Fn01 Fn074
11QC 21QC 31QC
Fp033
ccVD
42 32 22 12 02 91 81 71 61 51 41 31
G D D S C D D A A I R RE
F
QP
21IC
Fn01 Fn074
31IC
11IC
Fp033
21
11
01
9
8
7
6
5
4
3
2
1
Fn01 2DC
Fp033 3DC
+
Fn074 1DC
DNGA
QBNI
DNGA
QNI
DNGA
CCVA
LOPI
DNGA
IBNI
DNGA
INI
RE
F DNGA
C C E E I I B C C I I PI
N
E
VV
EBDNG N
DV
CG
N L KL G
NC
CG
N C MEF
EBCCV B C D CE D C C D M
QQ
T
)BSM(9D I
8D
7D
6D
B01 LAUD CDA
5D
4D
3D
2D
VN
GVV AA IR
1D
C
NE
CCOVVC
)BSL(0D N N C
F
BD
BC
BC
B E C C MM
73 83 93 04 14 24 34 44 54 64 74 84
Fp033 15C
Fn01 51C
Fp033 41C
K74
11R
CCVA Fn074 61C
Fn01 25C
44C
1BCCV
Fµ01 34C
Fn074 35C
Fµ74
TSPS-WS
4S
Fp033
NI RE RE
MC MF PF
Fn01 Fn074
03QC 13QC 23QC
K002
1jaR
Fn01 Fn074
K1
2R
Fp033
23IC
13IC
IFERV
2IJ
03IC
NI RE RE
MC MF PF
QFERV
2QJ
Fp033 Fn01 Fn074
1QC
Fp33
9QC 01QC
MN
8QC
6QC
MN
1IC
Fp33
01IC
MN0
32R
Fp033 Fn01 Fn074 Fµ01Fµ74
24C
2C
4C
3C 14C
6IC
9IC
Fp033 Fn01 Fn074
8IC
MN0
42R
CN 0
9QSR
5QSR
0 1-1TA-2T
TW
8QSR4
2
0
7QSR6 CN 20QT
CIGOLANA
DNG
CCV
AJ
CCVA
CN 0
9ISR
2
6
2IT
CN 0
5ISR
0TW1-1TA-2T
8ISR 4
0
7ISR
MN0
12R
éduos non :MN
MN0
22R
+
33C
R
Fp033
04C
Fn01 81C
aR
92C
Fp033 71C
Fµ01
52
62
72
82
92
03
13
23
33
43
53
63
Fp033
52C
Fn01
72C
Fn074
2BCC8V2C
2BCCV
2NOC
1
2
62J
O
Fn01
83C
N
01
9
8
7
6
5
4
3
2
1
01
9
8
7
6
5
4
3
2
1
05
5R
917GTS
1SDNG
D ccV
2S NI
1U
TSPS-WS
5S
K74
21R
F
Fn074
375XCL47
EL
DNG
7Q
7D
6Q
6D
5Q
5D
4Q
4D
3Q
3D
2Q
2D
1Q 3U 1D
0Q
0D
CCV BEO
E
375XCL47
EL
DNG
7Q
7D
6Q
6D
5Q
5D
4Q 2U 4D
3Q
3D
2Q
2D
1Q
1D
0Q
0D
CCV BEO
62C
1BCCV
ATADKC
52J
2BCC1VBCCV
T
11
21
31
41
51
61
71
81
91
02
11
21
31
41
51
61
71
81
91
02
Fp033
93C
2BCCV
WOPFUB
71J
O
W
D
E
KLC
11D
01D
9D
8D
7D
6D
5D
4D
3D
2D
1D
Fn01
73C
Fµ74
Fn074
43C
3BCCV
Vc Gn Vc Gn Vc Gn
B3c Bd B2c Bd B1c Bd
3 2 1
+
+
+
S
IG
DNG KLC
DNG 01D
)BSM( DNG 11D
DNG 9D
DNG 8D
DNG 7D
DNG 6D
DNG 5D
DNG 4D
DNG 3D
OD
trohS
nepO
5S hctiwS
3BCCV
edom tseT
edom lamroN
trohS
nepO
4S hctiwS
+
)BSL( DNG 2D
23
13
03
92
82
72
62
52
42
32
22
12
02
91
81
71
61
51
41
31
21
11
01
9
8
7
6
5
4
3
2
1
edom tuptuo ecnadepmI hgiH
edom lamroN
edoM BEO
tupni laitnereffid
tupni elgnis
)tluafed( remrofsnart htiw tupni golana
O
+
DNG 1D
DNG 0D
6J
C
C
C
C
C C C
9SR 8SR 7SR 6SR 5SR
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N
N
TSA1005
Figure 11: TSA1005 Evaluation board schematic
3
05
91QR
05
1QR
05
1IR
05
91IR
0
16QSR
3
0
1 6ISR
BQnI
B1QJ
BInI
B1IJ
Q
1
20/22
TSA1005
Figure 12: Printed circuit board - List of components
C26
C20
C33
C25
CI1
CQ1
C34
C42
C35
C44
C36
C32
C37
CQ10
C28
CI10
CQ32
CQ13
CI32
C13
C53
C16
C3
C22
CI13
C38
CD1
C19
Footprint Name Part
Footprint
Type
603
CQ6
NC
805
603
CI6
NC
805
603
U2
74LCX573
TSSOP20
603
U3
74LCX573
TSSOP20
603
U1
STG719
SOT23-6
603
JA
ANALOGIC connector
RB.1
J17
BUFPOW
connector
RB.1
J25
CKDATA
SMA
RB.1
J4
CLK
SMA
RB.1
J27
CON2
SIP2
RB.1
J26
CON2
SIP2
RB.1
JD
DIGITAL
connector
805
JI1
InI
SMA
805
JI1B
InIB
SMA
805
JQ1
InQ
SMA
805
JQ1B InQB
SMA
805
SW1 SWITCH
connector
805
S5
SW-SPST
connector
805
S4
SW-SPST
connector
805
TI2
T2-AT1-1WT ADT
805
TQ2
T2-AT1-1WT ADT
805
JI2
VREFI
connector
805
JQ2
VREFQ
connector
805
J6
32Pin
IDC-32
connector
805
805
805
NC: non soldered
805
N
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
603
Part
Type
330pF
330pF
330pF
330pF
33pF
33pF
47µF
47µF
47µF
47µF
47µF
47µF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
470nF
IG
Name
S
Footprint
E
Footprint Name Part
Type
805
CD2
10nF
805
C40
10nF
805
C39
10nF
805
CQ12 10nF
805
CQ9
10nF
805
C52
10nF
603
C18
10nF
603
C21
10nF
603
C4
10nF
603
C15
10nF
603
C27
10nF
603
C11
10nF
805
CI9
10nF
805
CI12
10nF
805
CI31
10nF
805
CQ31 10nF
805
CQ30 330pF
805
CI11
330pF
805
C51
330pF
805
C2
330pF
603
C17
330pF
603
CD3
330pF
603
C10
330pF
CQ8
330pF
VR5
trimmer
CQ11 330pF
10µF 1210
CI8
330pF
10µF 1210
C14
330pF
10µF 1210
CI30
330pF
D
Name Part
Type
RSQ6 0
RSQ7 0
RSQ8 0
RSI6 0
RSI7 0
RSI8 0
47
R3
47
R5
RQ19 47
47
RI1
RQ1 47
RI19 47
RSI9 0NC
RSQ5 0NC
RSQ9 0NC
RSI5 0NC
0NC
R24
0NC
R23
R21
0NC
R22
0NC
1K
R2
47K
R12
47K
R11
Raj1 200K
N
O
O
21/22
E
N
R
O
T
F
C23
C41
C29
W
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TSA1005
0 ( &+$1,&$/
'$7$
IG
74 ) 3
N
PACKAGE MECHANICAL DATA
PP
LQF
K
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0,1
7
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