SIHB15N60E-GE3

SiHB15N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) max. () at 25 °C • Low figure-of-merit (FOM) Ron x Qg 650 VGS = 10 V Qg max. (nC) • • • • • 0.28 78 Qgs (nC) 9 Qgd (nC) 17 Configuration Single Low input capacitance (Ciss) Reduced switching and conduction losses Ultra low gate charge (Qg) Avalanche energy rated (UIS) Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 D D2PAK (TO-263) APPLICATIONS • • • • Server and telecom power supplies Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) G G D S S N-Channel MOSFET ORDERING INFORMATION D2PAK (TO-263) SiHB15N60E-GE3 Package Lead (Pb)-free and Halogen-free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope VDS = 0 V to 80 % VDS Reverse Diode dV/dt d Soldering Recommendations (Peak temperature) c for 10 s V 15 9.6 A IDM 39 1.4 W/°C EAS 102 mJ Linear Derating Factor Single Pulse Avalanche Energy b UNIT PD 180 W TJ, Tstg -55 to +150 °C dV/dt 70 7.7 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 11.6 mH, Rg = 25 , IAS = 4.2 A. c. 1.6 mm from case. d. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S16-0799-Rev. F, 02-May-16 Document Number: 91485 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB15N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 0.7 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.71 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 10 Gate-Source Leakage IGSS Zero Gate Voltage Drain Current IDSS μA - 0.23 0.28  gfs VDS = 30 V, ID = 8 A - 4.6 - S Input Capacitance Ciss 1350 - Coss - 70 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output Capacitance - 5 - Effective Output Capacitance, Energy Related a Co(er) - 53 - Effective Output Capacitance, Time Related b Co(tr) - 177 - - 39 78 - 11 - Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 10 V ID = 8 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V ID = 8 A, VDS = 480 V Gate-Drain Charge Qgd - 17 - Turn-On Delay Time td(on) - 16 32 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VDD = 480 V, ID = 8 A, VGS = 10 V, Rg = 9.1  - 26 52 - 41 82 - 22 44 f = 1 MHz, open drain 0.3 0.86 1.7 - - 15 - - 60 nC ns  Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IS = 8 A, VGS = 0 V TJ = 25 °C, IF = IS = 8 A, dI/dt = 100 A/μs, VR = 25 V S - 1.0 1.2 V - 302 604 ns - 4.0 8 μC - 24 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S16-0799-Rev. F, 02-May-16 Document Number: 91485 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB15N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 40 30 ID = 8 A TJ = 25 °C RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 50 20 10 10 15 20 VGS = 10 V 1 0.5 30 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 10 000 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V BOTTOM 6 V 20 1.5 VDS, Drain-to-Source Voltage (V) TOP 25 25 TJ = 150 °C Ciss 1000 Capacitance (pF) ID, Drain-to-Source Current (A) 30 5 2 0 - 60 - 40 - 20 0 0 0 2.5 15 10 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Coss 100 Crss 10 5 5V 1 0 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 100 200 300 400 500 600 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 10 9 TJ = 25 °C 8 2000 7 30 6 TJ = 150 °C 20 Coss 5 Eoss 4 200 Eoss (μJ) 40 Coss (pF) ID, Drain-to-Source Current (A) 50 3 10 2 1 0 0 20 0 5 10 15 20 25 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S16-0799-Rev. F, 02-May-16 0 100 200 300 VDS 400 500 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 91485 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB15N60E www.vishay.com Vishay Siliconix 20 VDS = 480 V VDS = 300 V VDS = 120 V 20 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 15 10 5 4 0 0 0 20 40 60 25 80 Qg, Total Gate Charge (nC) 75 100 125 150 TJ, Case Temperature (°C) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature 750 100 725 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 50 TJ = 150 °C TJ = 25 °C 10 1 0.1 0.4 0.6 0.8 1 1.2 675 650 625 600 575 550 VGS = 0 V 0.2 700 1.4 1.6 525 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 VSD, Source-Drain Voltage (V) TJ, Junction Temperature (°C) Fig. 8 - Typical Source-Drain Diode Forward Voltage Fig. 11 - Temperature vs. Drain-to-Source Voltage 100 Operation in this Area Limited by RDS(on) IDM Limited ID, Drain Current (A) 10 100 μs Limited by RDS(on)* 1 1 ms 10 ms 0.1 TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S16-0799-Rev. F, 02-May-16 Document Number: 91485 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB15N60E www.vishay.com Vishay Siliconix Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.05 0.1 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS VG 10 % VGS td(on) td(off) tf tr Charge Fig. 17 - Basic Gate Charge Waveform Fig. 14 - Switching Time Waveforms L Vary tp to obtain required IAS QGD Current regulator Same type as D.U.T. VDS 50 kΩ D.U.T RG + - IAS 12 V 0.2 µF 0.3 µF V DD + D.U.T. 10 V tp 0.01 Ω - VDS VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S16-0799-Rev. F, 02-May-16 Document Number: 91485 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB15N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel           Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91485. S16-0799-Rev. F, 02-May-16 Document Number: 91485 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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