SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Low Figure-of-Merit Ron x Qg
560 V
RDS(on) (Ω)
VGS = 10 V
0.555
Qg (Max.) (nC)
48
Qgs (nC)
12
Qgd (nC)
• 100 % Avalanche Tested
• Gate Charge Improved
• Trr/Qrr Improved
15
Configuration
Single
TO-220AB
TO-220 FULLPAK
G
D
• Compliant to RoHS Directive 2002/95/EC
D
S
D2PAK
GD S
(TO-263)
G
S
G D
N-Channel MOSFET
S
ORDERING INFORMATION
Package
TO-220AB
D2PAK (TO-263)
TO-220 FULLPAK
Lead (Pb)-free
SiHP12N50C-E3
SiHB12N50C-E3
SiHF12N50C-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
LIMIT
TO220-AB
SYMBOL D2PAK (TO-263)
PARAMETER
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)a
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currentc
Single Pulse Avalanche
EAS
PD
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d
TJ, Tstg
for 10 s
A
28
1.67
Maximum Power Dissipation
V
7.5
IDM
Energyb
UNIT
12
ID
Linear Derating Factor
TO-220
FULLPAK
0.28
180
208
mJ
36
- 55 to + 150
300
W/°C
W
°C
Notes
a. Limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 12 A.
c. Repetitive rating; pulse width limited by maximum junction temperature.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
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1
SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TO220-AB D2PAK (TO-263)
TO-220 FULLPAK
Maximum Junction-to-Ambient
RthJA
62
65
Maximum Junction-to-Case (Drain)
RthJC
0.6
3.5
mount)a
RthJA
40
-
Junction-to-Ambient (PCB
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.6
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3.0
-
5.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
IGSS
IDSS
RDS(on)
gfs
VGS = ± 30 V
-
-
± 100
VDS = 500 V, VGS = 0 V
-
-
50
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
VGS = 10 V
-
0.46
0.555
Ω
-
3
-
S
-
1375
-
-
165
-
-
17
-
-
32
48
-
12
-
ID = 4 A
VDS = 50 V, ID = 3 A
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz
VGS = 10 V
ID = 10 A, VDS = 400 V
pF
nC
Gate-Drain Charge
Qgd
-
15
-
Turn-On Delay Time
td(on)
-
18
-
-
35
-
-
23
-
-
6
-
-
1.1
-
-
-
12
-
-
28
-
-
1.8
-
580
-
ns
-
4.3
-
μC
-
13
-
A
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VDD = 250 V, ID = 10 A
Rg = 4.3 Ω, VGS = 10 V
f = 1 MHz, open drain
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Body Diode Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 10 A, VGS = 0 V
TJ = 25 °C, IF = IS, dI/dt = 100 A/μs,
VR = 20 V
V
Note
• The information shown here is a preliminary product proposal, not a commercial product data sheet. Vishay Siliconix is not committed to
produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell
such products.
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2
Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
VGS
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTTOM 5.0 V
25
20
15
35
TJ = 25 °C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
30
10
5
7.0 V
0
25
20
TJ = 150 °C
15
10
5
0
0
5
10
15
20
25
0
30
5
10
15
20
25
VGS, Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics (TO-220)
Fig. 3 - Typical Transfer Characteristics
VGS
TJ = 150 °C
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
BOTTOM 5.0 V
15
12
9
RDS(on), Drain-to-Source On-Resistance
(Normalized)
VDS, Drain-to-Source Voltage (V)
18
ID, Drain-to-Source Current (A)
TJ = 25 °C
30
7.0 V
6
3
0
0
5
10
15
20
25
30
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics (TO-220)
Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
3
ID = 12 A
2.5
2
1.5
1
0.5
VGS = 10 V
0
- 60 - 40 - 20
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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3
SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
100
2400
C, Capacitance (pF)
2000
ISD, Reverse Drain Current (A)
VGS = 0 V, f = 1MHz
Ciss = Cgs +Cgd Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
1600
Ciss
1200
800
Coss
400
Crss
TJ = 150 °C
TJ = 25 °C
10
1
VGS = 0 V
0.1
0
1
10
100
0.2
1000
0.4
VDS, Drain-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
1.2
1.4
1.6
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
ID = 12 A
1
Fig. 7 - Typical Source-Drain Diode Forward Voltage
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
0.8
VSD, Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
24
0.6
16
12
8
4
10
100 µs
1 ms
1
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
0.1
0
0
10
20
30
40
50
10
60
100
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area (TO-220AB, D2PAK)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
ID, Drain-to-Source Current (A)
1000
10
100 µs
1 ms
1
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
0.1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 9 - Maximum Safe Operating Area (TO-220 FULLPAK)
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Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
VDS
RD
VDS
90 %
VGS
D.U.T.
RG
+
- VDD
10 %
VGS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
t d(on)
tr
t d(off) t f
Fig. 10b - Switching Time Waveforms
Fig. 10a - Switching Time Test Circuit
1
Thermal Response (ZthJC)
0.5
0.1
0.05
0.1
0.02
PDM
Single Pulse
(Thermal Response)
t1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
0.001
10-4
10-3
10-2
0.1
1
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case (TO-220AB, D2PAK)
1
Thermal Response (ZthJC)
0.5
0.2
0.1
PDM
0.1
0.05
t1
t2
0.02
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
0.001
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case (TO-220 FULLPAK)
Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
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5
SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
15 V
QG
VGS
L
VDS
Driver
QGS
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
0.01 Ω
Fig. 13a - Unclamped Inductive Test Circuit
QGD
VG
A
Charge
Fig. 14a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
V DS
50 kΩ
tp
12 V
0.2 µF
0.3 µF
D.U.T.
+
V
- DS
VGS
3 mA
I AS
IG
ID
Current sampling resistors
Fig. 13b - Unclamped Inductive Waveforms
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Fig. 14b - Gate Charge Test Circuit
Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
SiHP12N50C, SiHB12N50C, SiHF12N50C
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Body diode
VDD
forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 15 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91388.
Document Number: 91388
S10-0969-Rev. B, 26-Apr-10
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7
Package Information
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Vishay Siliconix
TO-220-1
A
E
F
D
H(1)
Q
ØP
3
2
L(1)
1
M*
L
b(1)
C
b
e
J(1)
e(1)
MILLIMETERS
DIM.
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.24
4.65
0.167
0.183
b
0.69
1.02
0.027
0.040
b(1)
1.14
1.78
0.045
0.070
c
0.36
0.61
0.014
0.024
D
14.33
15.85
0.564
0.624
E
9.96
10.52
0.392
0.414
e
2.41
2.67
0.095
0.105
e(1)
4.88
5.28
0.192
0.208
F
1.14
1.40
0.045
0.055
H(1)
6.10
6.71
0.240
0.264
J(1)
2.41
2.92
0.095
0.115
L
13.36
14.40
0.526
0.567
L(1)
3.33
4.04
0.131
0.159
ØP
3.53
3.94
0.139
0.155
Q
2.54
3.00
0.100
0.118
ECN: E21-0621-Rev. D, 04-Nov-2021
DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
Document Number: 66542
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revison: 04-Nov-2021
Package Information
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Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Revision: 01-Jan-2022
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Document Number: 91000