SIHP16N50C

SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration TO-220AB TO-220 FULLPAK FEATURES 560 V VGS = 10 V 68 17.6 21.8 Single D • Low Figure-of-Merit Ron x Qg 0.38 • 100 % Avalanche Tested • Gate Charge Improved • Trr/Qrr Improved • Compliant to RoHS Directive 2002/95/EC G D S GDS D2PAK (TO-263) G S GD S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free TO-220AB SiHP16N50C-E3 D2PAK (TO-263) SiHB16N50C-E3 TO-220 FULLPAK SiHF16N50C-E3 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted LIMIT PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C)a Pulsed Drain Currentc VGS at 10 V TC = 25 °C TC = 100 °C TO220-AB SYMBOL D2PAK (TO-263) VDS VGS ID IDM Energyb EAS PD TJ, Tstg for 10 s 250 - 55 to + 150 300 °C 500 ± 30 16 10 40 2 320 38 W/°C mJ W A TO-220 FULLPAK UNIT V Linear Derating Factor Single Pulse Avalanche Maximum Power Dissipation Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)d Notes a. Limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 16 A. c. Repetitive rating; pulse width limited by maximum junction temperature. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 www.vishay.com 1 SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) Junction-to-Ambient (PCB mount)a SYMBOL RthJA RthJC RthJA TO220-AB D2PAK (TO-263) 62 0.5 40 TO-220 FULLPAK 65 3.3 °C/W UNIT Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductancea Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Input Resistance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Body Diode Reverse Recovery Current IS ISM VSD trr Qrr IRRM MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf Rg TEST CONDITIONS VGS = 0 V, ID = 250 μA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 μA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 8 A VDS = 50 V, ID = 3 A MIN. 500 3.0 - TYP. 0.6 0.31 3 1900 230 24 45 18 22 27 156 29 31 1.6 MAX. 5.0 ± 100 50 250 0.38 68 - UNIT V V/°C V nA μA Ω S VGS = 0 V, VDS = 25 V, f = 1.0 MHz pF VGS = 10 V ID = 16 A, VDS = 400 V - nC VDD = 250 V, ID = 16 A, Rg = 9.1 Ω, VGS = 10 V f = 1 MHz, open drain - ns Ω - 555 5.5 18 16 A 30 1.8 V ns μC A G S TJ = 25 °C, IS = 10 A, VGS = 0 V TJ = 25 °C, IF = IS, dI/dt = 100 A/μs, VR = 20 V Note • The information shown here is a preliminary product proposal, not a commercial product data sheet. Vishay Siliconix is not committed to produce this or any similar product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products. www.vishay.com 2 Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 50 VGS 45 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V ID, Drain-to-Source Current (A) 40 35 30 25 20 15 10 5 0 0 TJ = 25 °C ID, Drain-to-Source Current (A) 45 40 35 30 25 20 15 10 5 0 0 2 4 6 8 TJ = 150 °C TJ = 25 °C 7.0 V 5 10 15 20 25 30 10 12 14 16 18 20 VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics (TO-220) VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On-Resistance (Normalized) 30 VGS TOP 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V BOTTOM 5.0 V 3 ID = 16 A 2.5 2 1.5 1 0.5 VGS = 10 V 0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 ID, Drain-to-Source Current (A) TJ = 150 °C 25 20 15 10 5 0 0 7.0 V 5 10 15 20 25 30 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics (TO-220) TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 www.vishay.com 3 SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix 2800 2400 2000 Ciss 1600 1200 Coss 800 400 Crss 0 1 10 100 1000 ISD, Reverse Drain Current (A) C, Capacitance (pF) VGS = 0 V, f = 1MHz Ciss = Cgs +Cgd Cds SHORTED Crss = Cgd Coss = Cds + Cgd 100 10 TJ = 150 °C TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage VSD, Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage 24 VGS, Gate-to-Source Voltage (V) 20 16 12 8 4 0 0 20 40 ID, Drain-to-Source Current (A) ID = 16 A VDS = 400 V VDS = 250 V VDS = 100 V 100 OPERATION IN THIS AREA LIMITED BY RDS(on) 10 100 µs 1 TTC==225°C TCC= 255°C TC = 25 °C °C 50 °C TTJ==1150°C TJ J= 150 °C TJ = 150 °C Single Pulse Single Pulse Single Pulse Single Pulse 0.1 10 100 1 ms 10 ms 60 80 1000 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area (TO-220AB, D2PAK) 100 OPERATION IN THIS AREA LIMITED BY RDS(on) ID, Drain-to-Source Current (A) 10 100 µs 1 TC = 25 °C TJ = 150 °C Single Pulse 0.1 10 100 1 ms 10 ms 1000 VDS, Drain-to-Source Voltage (V) Fig. 9 - Maximum Safe Operating Area (TO-220 FULLPAK) www.vishay.com 4 Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix VDS VGS RG RD VDS 90 % D.U.T. + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 10 % VGS t d(on) tr t d(off) t f Fig. 10a - Switching Time Test Circuit Fig. 10b - Switching Time Waveforms 1 0.5 Thermal Response (ZthJC) 0.2 0.1 0.1 0.05 0.02 PDM t1 t2 Single Pulse (Thermal Response) 0.01 10-4 10-3 10-2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 0.1 1 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case (TO-220AB, D2PAK) 1 0.5 Thermal Response (ZthJC) 0.2 0.1 0.1 0.05 0.02 t1 t2 Single Pulse (Thermal Response) 10-4 10-3 10-2 0.1 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 1 10 PDM 0.01 t1, Rectangular Pulse Duration (s) Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case (TO-220 FULLPAK) Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 www.vishay.com 5 SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix 15 V VGS VDS L Driver QGS D.U.T. IAS 20 V tp 0.01 Ω + A - VDD QGD QG RG VG A Charge Fig. 14a - Basic Gate Charge Waveform Fig. 13a - Unclamped Inductive Test Circuit Current regulator Same type as D.U.T. V DS tp 12 V 0.2 µF 0.3 µF 50 kΩ D.U.T. VGS 3 mA + V - DS I AS IG ID Current sampling resistors Fig. 13b - Unclamped Inductive Waveforms Fig. 14b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 SiHP16N50C, SiHB16N50C, SiHF16N50C Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 15 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91401. Document Number: 91401 S10-0811-Rev. A, 12-Apr-10 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1