AW87519
May 2019 V1.1
8.5V High Efficiency High PSRR Low Noise Large Volume 2-in-1
TLTR-AGC 3rd Generation Smart K Audio Amplifier
DESCRIPTION
Triple-Level Triple-Rate AGC algorithm to effectively
eliminate noise, pure sound quality
High efficiency large drive ability BOOST
Highest voltage：8.5V
Overall efficiency up to 80%
Output Power：4.3W@8Ω，5.3W@6Ω
High PSRR：-82dB（217Hz）
Low noise：
18 μV (Class D Receiver THD+N=0.03%)
43 μV (Class K Speaker THD+N=0.04%)
Selectable speaker-guard power level：
0.5W~2W@8ohm, 100mW/step
Speaker & receiver 2-in-1 mode application
Battery tracking AGC selectable, for low voltage
protection
Shutdown current：0.1μA
Super TDD-Noise suppression
Excellent pop-click suppression
Support 1.8V logic I2C control
FCQFN 2.0mmX3.0mmX0.55mm-20L package
AW87519 is specifically designed to improve the musical
output dynamic range, enhance the overall sound quality. It
is a new high efficiency, high PSRR，low noise, constant
large volume, 3rd generation Smart K audio amplifier.
AW87519 integrates AWINIC’s proprietary Triple-Level
Triple-Rate AGC audio algorithm, effectively eliminating
music noise and improving sound quality and volume.
AW87519 integrates high voltage synchronous Boost with
efficiency up to 88% as the class D power stage supply,
significantly improving the dynamic range of music.
AW87519 noise floor is as low as to 43μV at speaker mode,
with 103dB high signal-to-noise-ratio (SNR). The ultra-low
distortion 0.04% and unique Triple-Level Triple-Rate AGC
technology bring high quality music enjoyment.
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FEATURES
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AW87519 supports speaker and receiver 2-in-1 application.
In the receiver mode, its ultra-low noise is 18μV. Class D
receiver also has high PSRR performance to completely
suppress TDD-noise.
AW87519 controls internal registers through the I 2C
interface. Register parameters include boost output voltage,
boost maximum input peak current, PA gain, Triple-Level
Triple-Rate AGC parameters, etc.
APPLICATIONS
C
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Smart phone、Tablet PC
AW87519 built-in over current protection, over temperature
protection and short circuit protection function, effectively
protect the chip. AW87519 features small FCQFN
2.0mmX3.0mmX0.55mm-20L package.
TYPICAL APPLICATION CIRCUIT
VBAT
4
GPIO
I2C Interface
9
{
10
5
I2C Address Select
18
SW
VREG
RSTN
SDA
VBST
17
C9
22nF
6.3V
19
SCL
C5
10 μF
25V
AD
C6
22 μF
25V
See in detail“Boost capacitor selection”
Cin68nF
Ground Shielding
Pseudo-Differential routing
MUX
Receiver
BB
C3
0.1uF
VDD
8
Speaker
Audio
DAC
See in detail“Boost inductor selection”
C2
10uF
3
HPH_L/R
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L 1uH
3.5A(8Ω) / 4A(6Ω)
C1
0.1uF
Cin+
68nF
7
AW87519
INN
VOP
INP
VON
HPH_REF
See in detail“PCB Layout”
GND
6,11~15
Figure 1
BGND
16
20
2
B+
See in detail“Bead、Cap、TVS”
C7
0.1nF
16V
16V
C8
0.1nF
16V
16V
SPK
B-
PGND
1
AW87519 Single-ended Input Mode Application Diagram
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COPYRIGHT ©2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD.
1
AW87519
May 2019 V1.1
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PIN CONFIGURATION AND TOP MARK
Symbol
1
2
PGND
in
3
Description
Class D power ground
VON
Negative audio output terminal
VDD
Power supply
Reset pin, active low reset, the internal 2MΩ pull-down resistor in chip
4
RSTN
5
AD
6
GND
Ground
7
INP
Positive audio input terminal
8
INN
Negative audio input terminal
9
SDA
I2C-bus data input/output
10
SCL
I2C-bus clock input
11
GND
Ground
12~15
TEST1~TEST4
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Number
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PIN DESCRIPTION
AW87519FCR Pin configuration and Top Mark
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Figure 2
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I2C address pin
TEST pins，connect to GND in application
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AW87519
May 2019 V1.1
16
BGND
Boost power ground
17
VREG
Charge pump output pin
18
SW
Boost switch pin
19
VBST
Boost output pin
20
VOP
Positive audio output terminal
SW
VDD
AD
CHARGE
PUMP
n
OVP
BOOST
2
IC
SYSCTRL
AD
BAT
SAFEGUARD
AGC
INP
PEAK
CURRENT
LIMIT
LOW-BAT
DETECT
INPUT
BUFFER
OCP
ULTRA-LOW
EMI
OUTPUT
STAGE
VOP
VON
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PVDD
VOLTAGE
SENSING
GND
BGND
PGND
AW87519 Functional Diagram
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Figure 3
OSC
CLASS K
MODULATOR
INN
TRIPLE-LEVEL
TRIPLE-RATE
AGC
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SDA
BIAS&OT
VREG
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SCL
RSTN
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RSTN
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FUNCTIONAL DIAGRAM
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AW87519
May 2019 V1.1
TYPICAL APPLICATION CIRCUIT
VBAT
L 1uH
3.5A(8Ω) / 4A(6Ω)
C1
0.1uF
See in detail“Boost inductor selection”
C2
10uF
3
C3
0.1uF
18
I2C Interface
9
{
5
I C Address Select
VREG
SDA
10
2
SW
RSTN
VBST
17
C9
22nF
6.3V
19
SCL
C5
10 μF
25V
AD
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4
GPIO
C6
22 μF
25V
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VDD
See in detail“Boost capacitor selection”
Cin68nF
HPH_L/R
8
Speaker
Ground Shielding
Pseudo-Differential routing
MUX
Receiver
BB
Cin+
68nF
7
VOP
INP
20
VON
HPH_REF
See in detail“PCB Layout”
GND
C7
0.1nF
16V
16V
C8
0.1nF
16V
16V
B-
2
SPK
PGND
1
e
6,11~15
BGND
16
See in detail“Bead、Cap、TVS”
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Audio
DAC
AW87519
INN
B+
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AW87519 Single-ended Input Mode Application Diagram(Note 1)
Figure 4
Note1：When single-ended input, audio signal line from audio DAC (HPH_L or HPH_R) can arbitrarily connected to either
of INN or INP input terminal. The other terminal must be connected to reference ground (HPH_REF) through input
capacitor and resistor.
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VBAT
L 1uH
3.5A(8Ω) / 4A(6Ω)
C1
0.1uF
o
C2
10uF
3
C3
0.1uF
VDD
C
GPIO
4
I2C Interface
9
{
10
5
2
ic
I C Address Select
HPH_L/R
in
Receiver
BB
SW
VREG
RSTN
SDA
VBST
C9
22nF
6.3V
19
SCL
C5
10 μF
25V
AD
8
Cin+
68nF
7
AW87519
INN
VOP
INP
VON
HPH_REF
Figure 5
17
C6
22 μF
25V
See in detail“PCB Layout”
GND
6,11~15
BGND
16
20
2
B+
See in detail“Bead、Cap、TVS”
C7
0.1nF
16V
16V
C8
0.1nF
16V
16V
SPK/
RCV
B-
PGND
1
AW87519 Speaker & Receiver 2-in-1 Mode Application Diagram
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Ground Shielding
Pseudo-Differential routing
MUX
18
See in detail“Boost capacitor selection”
Cin68nF
Speaker
Audio
DAC
See in detail“Boost inductor selection”
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AW87519
May 2019 V1.1
ORDERING INFORMATION
Temperature
Package
Marking
Moisture
Sensitivity
Level
Environmental
Information
Delivery Form
AW87519FCR
-40°C～85°C
FCQFN
2.0mmX3.0mm-20L
E2Y6
MSL1
ROHS+HF
6000 units/
Tape and Reel
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Part Number
ABSOLUTE MAXIMUM RATING (Note2)
Range
Supply Voltage VDD
-0.3V to 6V
INN,INP
-0.3V to VDD+0.3V
Boost output voltage PVDD
-0.3V to 12V
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Parameter
SW
-0.3V to PVDD+2V
-0.3V to PVDD+0.3V
Minimum load resistance RL
Package Thermal Resistance θJA
Ambient Temperature Range
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VOP,VON
5Ω
57.9°C/W
-40°C to 85°C
165°C
Storage Temperature Range TSTG
-65°C to 150°C
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Maximum Junction Temperature TJMAX
Lead Temperature（Soldering 10 Seconds）
260°C
C
ESD Rating (Note 3)
±2kV
CDM（charged-device model）
±1.5kV
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HBM（human body model）
Latch-up
+IT：450mA
-IT：-450mA
in
Test Condition：JEDEC STANDARD NO.78E
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NOTE2: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent
damages to the device. In spite of the limits above, functional operation conditions of the device
should within the ranges listed in "recommended operating conditions". Exposure to
absolute-maximum-rated conditions for prolonged periods may affect device reliability.
NOTE3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each
pin. Test method: ESDA/JEDEC JS-001-2017
a
Test method of the charge device model: ESDA/JEDEC JS-002-2014
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AW87519
May 2019 V1.1
ELECTRICAL CHARACTERISTICS
Parameter
UVLO
Test conditions
Power supply voltage
Min
2.8
Under-voltage protection
voltage
2.5
Under-voltage protection
hysteresis voltage
100
RSTN, SCL, SDA, AD
high-level input voltage
1.3
VIL
RSTN, SCL, SDA, AD
low-level input voltage
0
ISD
Shutdown current
TTG
Thermal AGC start
temperature threshold
TTGR
Thermal AGC exit
temperature threshold
TSD
Over temperature
protection threshold
TSDR
Over temperature
protection recovery
threshold
TON
Turn-On time
TST
V
mV
0.1
VDD
V
0.45
V
1
μA
160
°C
130
°C
45
ms
VDD=2.8V to 5.5V
8.5 (Note4)
V
VDD=2.8V to 5.5V
VBST+0.5
V
VDD=2.8V to 5.5V
500
mV
3.5 (Note4)
A
1.6
MHz
Soft-start Switching
frequency
0.4
MHz
The maximum duty cycle
90
%
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OVP voltage
OVP hysteresis voltage
C
BOOST Output voltage
Inductor peak current limit
VDD=2.8V to 5.5V
Soft-start time
No load，COUT=22μF
2
ms
Boost efficiency
VDD=4.2V, Iload=200mA
88
%
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ηCP
V
130
in
DMAX
5.5
℃
Boost operating frequency
FBST
Units
150
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IL_PEAK
Max
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VDD=3.6V, RSTN=0V
BOOST
OVP
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VIH
VBST
Typ
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VDD
RL=8Ω+33μH, f=1kHz（unless otherwise noted）
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Test condition：TA=25°C, VDD=4.2V, PVDD=8.5V,
CLASS K MODE
Output offset voltage
No input
ηT
total efficiency
(BOOST+CLASS D)
VDD=4.2V, Po=2.5W,
RL=8Ω+33μH
IQK
Speaker Quiescent current
VDD=4.2V, input ac grounded,
RL=8Ω+33μH
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VOS
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-30
0
30
80
%
16.5
mA
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6
mV
AW87519
May 2019 V1.1
Test conditions
Min
Rdson
Drain-Source on-state
resistance
High side MOS + Low side MOS
Vinp
Recommended input signal
amplitude
VDD=2.8V to 5.5V
Fosc
Modulation frequency
VDD=2.8V to 5.5V
600
Pagc
TLTR AGC power
RL=8Ω+33μH
0.72
EN
Speaker Output noise
Av=18dB
Fin
W
1.17
W
1kHz
-80
dB
103
dB
dB
94
53
μV
43
24 (Note4)
Speaker Inner input
resistance
Av=24dB
Speaker Inner input
resistance
Av=18dB
Speaker input Cut-off
frequency
Cin=68nF, Av=24dB
Speaker input Cut-off
frequency
Cin=68nF, Av=18dB
130
VDD=4.2V, Po=0.6W,
RL=8Ω+33μH, f=1kHz
0.04
%
THD+N=1%, RL=8Ω+33μH,
VDD=4.2V, PVDD=8.5V,
IL_PEAK=4A
4.3
W
THD+N=10%, RL=8Ω+33μH,
VDD=4.2V, PVDD=8.5V,
IL_PEAK=4A
5.2
W
THD+N=1%, RL=6Ω+33μH,
VDD=4.2V, PVDD=8.5V,
IL_PEAK=4A
5.3
W
THD+N=10%，RL=6Ω+33μH,
VDD=4.2V, PVDD=8.5V,
IL_PEAK=4A
6.3
W
VDD=4.2V, input ac grounded,
RL=8Ω+33μH
6.8
mA
Total harmonic distortion +
noise
in
Speaker Output Power
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VDD=2.8V to 5.5V
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Po
0.88
Speaker gain
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THD+N
kHz
dB
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Rini
1.067
1000
-78
C
Av
(Note4)
Vp
217Hz
20Hz to
20kHz, input
ac grounded,
A-weighting
Av=24dB
0.8 (Note4)
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Signal-to-noise ratio
VDD=4.2V, Po=4.3W,
Av=18dB ,RL=8Ω+33μH,
VDD=4.2V, Po=0.8W,
Av=18dB,RL=8Ω+33μH,
mΩ
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VDD=4.2V,
Vpp_sin=200
mV
Units
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SNR
0.96
Power supply rejection
ratio
Max
250
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PSRR
RL=6Ω+33μH
Typ
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Parameter
dB
9
kΩ
18
260
Hz
2-in-1 Receiver MODE
IQD
D Receiver quiescent
current（overall）
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AW87519
May 2019 V1.1
Parameter
Test conditions
ηD
CLASS D Receiver
efficiency
VDD=4.2V,Po=0.8W,
RL=8Ω+33μH
Av
gain
VDD=2.8V to 5.5V
Rini
CLASS D Receiver Inner
input resistance
Fin
CLASS D Receiver input
cut-off frequency
EN
CLASS D Receiver output
noise
Av=9dB
24
kΩ
Cin=68nF, Av=9dB
98
Hz
CLASS D Receiver Power
supply rejection ratio
VDD=4.2V,
Vp-p_sin=200
mV
Po
CLASS D Receiver Output
Power
THD+N=1%, RL=8Ω+33μH,
VDD=4.2V, GAIN=7.5~9dB
THD+N=1%, RL=8Ω+33μH,
VDD=4.2V, GAIN=10.5dB
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1kHz
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AGC1 Attack Time
TAT2
AGC2 Attack Time
TAT3
AGC3 Attack Time
TRLT
Release time
AMAX
The maximum attenuation
gain
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C
TAT1
VDD=2.8V to 5.5V
μV
21
μV
0.03
%
-82
dB
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217Hz
Battery Tracking AGC
Triple-Level Triple-Rate AGC
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Av=9dB
18
n
20Hz to
20kHz, input
ac grounded,
A-weighting
Av=7.5dB
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dB
PSRR
Battery protection
Hysteresis voltage
Units
7.5 (Note4)
VDD=4.2V,
Po=0.1W,RL=8Ω+33μH,
f=1kHz, CLASS D Receiver
VHYS
Max
%
Total harmonic distortion +
noise
Battery protection
threshold voltage
Typ
90
THD+N
VBSGD
Min
-80
dB
0.5
W
0.85
W
3.4 (Note4)
V
100
mV
0.08 (Note4)
ms/dB
0.64 (Note4)
ms/dB
41 (Note4)
ms/dB
21 (Note4)
ms/dB
-13.5
dB
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Note 4：Registers are adjustable; Refer to the list of registers.
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AW87519
May 2019 V1.1
MEASUREMENT SETUP
AW87519 features switching digital output, as shown in Figure 6. Need to connect a low pass filter to
VOP/VON output respectively to filter out switch modulation frequency, then measure the differential output of
filter to obtain analog output signal.
10nF
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500Ω
30kHz
Low-Pass Fliter
AW87519
VON
INN
500Ω
Cin
AW87519 Test Setup
Low pass filter uses resistance and capacitor values listed in Table 1.
500Ω
10nF
1kΩ
4.7nF
32kHz
34kHz
AW87519 Recommended Values for Low Pass Filter
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Table 1
Low-pass cutoff frequency
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Cfilter
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Rfilter
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Figure 6
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10nF
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VOP
INP
Cin
Output Power Calculation
C
According to the above test methods, the differential analog output signal is obtained at the output of the
low pass filter. The valid values Vo_rms of the differential signal , as shown in Figure 7：
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Vo_rms
Figure 7
Output RMS Value
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The power calculation of Speaker is as follows：
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PL
(VO_rms )2
RL
RL: load impedance of the speaker
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AW87519
May 2019 V1.1
TYPICAL CHARACTERISTICS
Class K Efficiency vs Po
Class K Efficiency vs Po
90
90
80
80
70
70
40
30
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50
60
50
40
30
VDD = 4.2V
PVDD = 8.5V
RL = 8 ohm + 33uH
20
10
VDD = 4.2V
PVDD = 8.5V
RL = 6 ohm + 33uH
20
10
0
0
0
1
2
3
4
5
0
1
Output Power (W)
4
5
6
7
1.2
1.4
6
7
Class D Efficiency vs Po
100
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90
80
80
60
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60
Efficiency (%)
70
70
50
o
40
VDD = 4.2V
Gain = 10.5dB
RL = 8 ohm + 33uH
20
10
0
0
0.2
0.4
0.6
0.8
1
50
40
30
VDD = 4.2V
Gain = 10.5dB
RL = 6 ohm + 33uH
20
C
30
10
0
0
1.2
0.2
0.4
1
ic
2.5
in
VDD = 4.2V
PVDD = 8.5V
RL = 8 ohm + 33uH
VDD = 4.2V
PVDD = 8.5V
RL = 6 ohm + 33uH
2
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I_VDD_supply (A)
1.2
0.8
Class K I_VDD_supply VS Po
I_VDD_supply VS Po
1.5
0.6
Output Power (W)
Output Power (W)
I_VDD_supply (A)
3
e
Class D Efficiency vs Po
Efficiency (%)
2
Output Power (W)
100
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60
n
Efficiency (%)
100
Efficiency (%)
100
0.9
0.6
0.3
1.5
1
0.5
0
0
0
1
2
3
4
5
0
Output Power (W)
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1
2
3
4
5
Output Power (W)
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AW87519
May 2019 V1.1
Class D Gain vs frequency
Class K Gain vs frequency
40
25
VDD = 4.2V
PVDD = 8.5V
Cin = 1uF
RL = 8 ohm + 33uH
35
30
20
Gain = 24dB
Gain = 18dB
15
25
15
0
10
-5
5
-10
20
100
1K
-15
20
10K
100
Frequency (Hz)
Class K PSRR vs frequency
-20
-30
VDD = 5.5V
VDD = 4.2V
VDD = 3.6V
-40
-40
-60
o
-70
-100
100
1K
e
-60
-70
-80
-90
C
-80
VDD = 5.5V
VDD = 4.2V
VDD = 3.6V
-50
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-50
-90
Cin = 1uF
RL = 8 ohm + 33uH
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PSRR (dB)
-10
PVDD = 8.5V
Cin = 1uF
RL = 8 ohm + 33uH
-30
-100
100
10K
1K
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Frequency (Hz)
VDD = 4.5V
VDD = 4.2V
VDD = 3.6V
0.1
0.1
0.001
100
1K
20
10K
100
1K
10K
Frequency (Hz)
Frequency (Hz)
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VDD = 4.5V
VDD = 4.2V
VDD = 3.6V
0.01
0.01
0.001
20
VDD = 4.2V
PVDD = 8.5V
Po = 1W
RL = 6 ohm + 33uH
1
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THD+N (%)
1
Class K THD+N vs frequency
10
THD+N (%)
in
VDD = 4.2V
PVDD = 8.5V
Po = 1W
RL = 8 ohm + 33uH
10K
Frequency (Hz)
Class K THD+N vs frequency
10
10K
Class D PSRR vs frequency
0
PSRR (dB)
-20
1K
Frequency (Hz)
0
-10
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5
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20
0
a
Gain = 9dB
10
Gain (dB)
Gain (dB)
VDD = 4.2V
Cin = 1uF
RL = 8 ohm + 33uH
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AW87519
May 2019 V1.1
Class D THD+N vs frequency
Class D THD+N vs frequency
10
10
Receive mode
VDD = 4.2V
RL = 8 ohm + 33uH
Receive mode
VDD = 4.2V
RL = 6 ohm + 33uH
1
0.01
0.1
l
0.1
Po = 10mW
Po = 100mW
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Po = 10mW
Po = 100mW
THD+N (%)
0.01
0.001
20
0.001
100
1K
10K
20
100
1K
Frequency (Hz)
Frequency (Hz)
Class K THD+N vs Po
10
1
VDD = 4.2V
VDD = 3.6V
n
THD+N (%)
VDD = 4.2V
VDD = 3.6V
1
PVDD = 8.5V
Fin=1kHz
RL = 6 ohm + 33uH
Gain=24dB
fi
d
PVDD = 8.5V
Fin=1kHz
RL = 8 ohm + 33uH
Gain=24dB
0.1
o
THD+N (%)
100
e
Class K THD+N vs Po
100
10
0.001
0.1
0.5
1
2
4
0.1
0.01
C
0.01
0.001
0.1
6 8
0.5
Output Power (W)
ic
10
a
6 8
Fin=1kHz
RL = 6 ohm + 33uH
Gain = 10.5dB
THD+N (%)
VDD = 4.2V
VDD = 3.6V
1
w
THD+N (%)
VDD = 4.2V
VDD = 3.6V
0.1
1
0.1
0.01
0.01
0.2
0.3
0.5
0.7
0.001
0.1
1 1.2
0.2
0.3
0.5
0.7
1 1.2
Output Power (W)
Output Power (W)
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4
Class D THD+N vs Po
Fin=1kHz
RL = 8 ohm + 33uH
Gain = 10.5dB
0.001
0.1
2
100
in
10
1
Output Power (W)
Class D THD+N vs Po
100
10K
n
THD+N (%)
1
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AW87519
May 2019 V1.1
Shutdown sequence
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Start-up sequence
50us/div
e
n
10ms/div
Triple-Level Triple Rate AGC Release Timing
C
o
n
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Triple-Level Triple Rate AGC Attack Timing
200ms/div
in
ic
Po vs Vin
1
w
Output Power (W)
2
0.941
0.862
0.6
0.769
0.5
0.20
0.4
a
100ms/div
0.3
0.659
0.184
AGC_TH = 1.2W
AGC_TH = 1.0W
0.164
AGC_TH = 0.8W
AGC_TH = 0.6W
0.141
0.2
0.1
0.2
0.3
0.4 0.5 0.6
1
Input Level (Vrms)
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AW87519
May 2019 V1.1
WORKING PRINCIPLE
ti
a
l
AW87519 is specifically designed to improve the musical output dynamic range, enhance the overall sound
quality. It is a new high efficiency, high PSRR，low noise, constant large volume, 3rd generation Smart K
audio amplifier. AW87519 integrates AWINIC’s proprietary Triple-Level Triple-Rate AGC audio algorithm,
effectively eliminating music noise and improving sound quality and volume. AW87519 integrates high voltage
synchronous Boost with efficiency up to 88% as the class D power stage supply, significantly improving the
dynamic range of music. AW87519 noise floor is as low as to 43μV at speaker mode, with 103dB high
signal-to-noise-ratio (SNR). The ultra-low distortion 0.04% and unique Triple-Level Triple-Rate AGC
technology bring high quality music enjoyment.
AW87519 supports speaker and receiver 2-in-1 application. In the receiver mode, its ultra-low noise is 18μV.
Class D receiver also has high PSRR performance to completely suppress TDD-noise.
n
AW87519 controls internal registers through the I2C interface. Register parameters include boost output
voltage, boost maximum input peak current, PA gain, Triple-Level Triple-Rate AGC parameters, etc.
e
AW87519 built-in over current protection, over temperature protection and short circuit protection function,
effectively protect the chip. AW87519 features small FCQFN 2.0mmX3.0mmX0.55mm-20L package.
CONSTANT OUTPUT POWER
o
n
fi
d
In the mobile phone audio applications, the AGC function to promote music volume and quality is very
attractive, but as the lithium battery voltage drops, general power amplifier output power will reduce gradually.
So, it is hard to provide high quality music within the battery voltage range. AW87519 uses unique
Triple-Level Triple-Rate technology, within lithium battery voltage range (3.3V~4.35V), to guarantee that
output power is constant, and the output power will not drop along with the decrease of lithium battery voltage.
In the process of using the phone, even if the battery voltage drops, AW87519 can still provide high quality
large volume music enjoyment. The output power of AW87519 can be configured from 0.5W to 2W via I2C,
matching general speakers. Unique Triple-Level Triple-Rate AGC technology can bring high-quality music
enjoyment.
C
Triple-Level Triple-Rate AGC technology
a
w
in
ic
AWINIC proprietary Triple-Level Triple-Rate AGC technology is designed for the protection of the high voltage
power amplifier, which is divided into AGC1, AGC2 and AGC3 power levels, to obtain a large volume while
maintaining excellent sound quality.
In practical applications, speaker can continuously work long hours at rated power, and also can work
short-term at high power. For example, in the standard reliability of the loudspeaker experiment, the powder of
peak power reached around four times of the rated power. For achieving larger volume and better sound
quality, speakers need to work at high power for short periods of time, in order to improve the performance of
the speaker. AW87519 Triple-Level Triple-Rate AGC technology can fit the speaker better and perform better
overall performance. AGC1 prevents output signal clipping by detecting output voltage in a very short time
after clipping, which can effectively restrain the noise clipping; AGC2 can improve the dynamic range of the
music in a relatively short period of time; AGC3 can make the speaker work under rated power, which can
effectively improve the volume and protect the speaker. Triple-Level Triple-Rate AGC can obtain more
excellent overall performance.
Triple-Level Triple-Rate AGC detects the peak output voltage of the power amplifier, when the output peak
voltage is higher than the compression threshold voltage, the amplifier gain decreases in 0.5dB step. When
the output peak voltage is lower than the release threshold voltage, the amplifier gain is recovery to the initial
gain in 0.5dB step. The detailed process can be described as follows:
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14
AW87519
May 2019 V1.1
Vin
AGC1 Compression threshold voltage
Vth_at1
Vth_at2
Vth_at3
Vth_rt
B
C
D
E
F
G
H
e
A
AGC1
compression
AGC2
compression
Figure 8
fi
d
Gain
n
Vout
ti
a
The release threshold voltage
l
AGC2 Compression threshold voltage
AGC3 Compression threshold voltage
AGC3 compression
hold
release
Triple-Level Triple-Rate AGC Operation Principle
n
A: Small input signal, the output voltage is lower than threshold voltage Vth of AGC, AGC don't work.
a
w
in
ic
C
o
B: Input voltage becomes large. It leads to the output voltage clipping, AGC1 starts fast compression, the
attack time is set through the I2C register 0x0Ah [2:1], when the output voltage is higher than Vth_at1, and
gain register began to decrease. Gain decreases when the output signal passes through the zero. It
eliminates the clipping noise as soon as possible.
C: When the output voltage is not clipping and higher than threshold voltage Vth_at2, AGC2 starts work, the
attack time is set through the I2C register 0x09h [4:2], gain register begins to decrease at a certain rate. Gain
register began to decrease. Gain decreases when the output signal passes through the zero. The output
voltage gradually decreases to below the AGC2 attack threshold voltage Vth_at2, which can protect the
speaker and enhance the sound.
D: When the output voltage is lower than the AGC2 attack threshold voltage Vth_at2 and higher than the
AGC3 attack threshold voltage Vth_at3, AGC3 starts work, the attack time is set through the I2C register
0x07h [4:2], and gain register began to decrease at a certain rate. Gain decreases when the output signal
passes through the zero, so the output voltage gradually decreases to below of the AGC3 attack threshold
voltage Vth_at3, matching the speaker to achieve greater volume and better sound quality.
E: Triple-Level Triple-Rate AGC attack time ends, Amplifier output power is close to the speaker rated power.
F: Input voltage decreases, the output voltage becomes lower than the release threshold voltage Vth_rt, at
this point, gain remains the same in the maintain time (10ms~20ms).
G: Gain increases when the time of output voltage lower than the release threshold voltage Vth_rt is longer
than the holding time. The release time can be set through I2C register 0x07h [7:5].
H: Stop release when the output signal is larger than the release threshold or the gain is equal to the initial
value. The output voltage remains constant.
Triple-Level Triple-Rate AGC can switch independently according to different application requirements. Such
as close AGC1 and AGC2, retain only AGC3, this is the single-AGC mode, similar to AW8736 (AGC3 attack
time is set to 1.28ms/dB; release time is set to 41ms/dB); Close AGC2, open AGC1 and AGC3, this is
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15
AW87519
May 2019 V1.1
Multi_level AGC. It can be set similar to AW8738 (AGC1 attack time is set to 80us/dB; AGC3 attack time is set
to 0.64ms/dB; release time is set to 10.24ms/dB).
Zero-Crossing Adjustment Technology
zero-crossing adjustment
Figure 9
fi
d
e
n
ti
a
no zero-crossing adjustment
l
Traditional AGC doesn’t contain zero adjustment technology; AGC gain changes generally at the peak, the
gain variation at the peak would generate a certain transient distortion, such distortions are audibly
imperceptible. Such as individual songs have a slight click.
Zero-adjust Comparison
o
n
As shown above, when there is no zero-adjustment technology, it can be seen the obvious step change at the
peak of large signal, the steps sound slightly perceived in special audio. Gain changes at zero. The steps
disappear by using zero-crossing detection technology. Using zero detection technology can make the music
pure and natural.
C
Low-voltage protection AGC technology
a
w
in
ic
Mobile phone battery voltage will decrease in use, but the current will increase. When the battery voltage is
low, high current maybe cause the battery protection or mobile phone automatically shut down. Awinic
proprietary low voltage protection AGC technology can solve the problems, to prevent high current when the
battery voltage is too low.
AW87519 is built-in low voltage protection AGC technology to real-time detection the battery voltage. Gain
decreases rapidly when the battery voltage is below the safety threshold, so as to decrease the output voltage
and the power supply current, which effectively prevents high current.
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AW87519
May 2019 V1.1
Maximum output amplitude(Vp)
Low-voltage protection
Unprotected(V)
Protection limit(V)
ti
a
l
Lower limit protection(V)
The battery voltage(V)
Low voltage protection
n
Figure 10
e
The protection safety threshold voltage is set to 3.3V~3.6V through the I2C register 0x02h [4:3]. The maximum
protection output voltage is set to 5Vp ~ 6.5Vp through I2C register 0x02h [1:0].
Only when the register 0x02h [2] is set to 1, low voltage protection AGC technology is enabled.
fi
d
Synchronous Boost technology
o
n
AW87519 integrated peak current mode synchronous PWM Boost as Class D power stage supply,
significantly increase the output voltage dynamic range. Reduces the size of external components and saves
PCB space by using 1.6MHz switching frequency. Boost output voltage can be set through the I2C register
0x03h [4:0]; Boost current limit can be set through register 0x04h [4:2].
AW87519 synchronous Boost with soft-start function to prevent overshoot current at powering-on; integrated
the output protection circuit and self-recovery function; integrated Anti-Ring circuit to reduce EMI in DCM
mode; built-in substrate switching shutdown circuit, effectively preventing the input and output leakage current
anti-irrigation.
C
Speaker & Receiver 2-in-1 application
w
in
ic
AW87519 built-in speaker and receiver 2-in-1 application mode, through the register settings, class D-type
2-in-1 receiver mode gain can be adjusted through the I2C register 0x05, adjustable range of 7.5~10.5dB, the
application is very flexible. The 2-in-1 receiver mode uses the signal path of the speaker, with ultra-low
distortion and strong drive capability, and eliminates the need for additional peripheral components, saving
system cost and PCB layout space.
In the typical application case of Figure 5, the input capacitance Cin = 68nF, the gain is 24dB in the speaker
application mode, the input high-pass cutoff frequency is 260Hz; In 7.5dB gain class D-type 2-in-1 receiver
application mode, the output noise is 18μV, the input high-pass cut-off frequency is 78Hz, which is very
suitable for high-definition voice applications. AW87519 can achieve speaker and receiver's 2-in-1 application
without changing any hardware in the case.
RNS(RF TDD Noise Suppression)
TDD Noise Causes
a
GSM cell phones use TDMA (Time Division Multiple Access) slot sharing technology. The time is divided into
periodic frames in TDMA, and each frame is subdivided into a plurality of time slots. In order to transmit
signals to the base station, the signals sent from the base stations to the plurality of mobile terminals are
arranged in a predetermined time slot in the transmission. In this case, each TDMA frame contains 8 time
slots, the entire frame is about 4.615ms long, and each slot time is 0.577ms.
With GSM handset, the RF power amplifier will transmit once every 4.615ms (217Hz), and the signal will
produce intermittent Burst current and strong electromagnetic radiation. Intermittent Burst current will form a
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17
AW87519
May 2019 V1.1
power fluctuation of 217 Hz; High frequency (900MHz and 1800MHz) RF signals form a 217Hz RF envelope
signal. 217Hz power fluctuations will be conducted through the conduction to the audio signal path, 217Hz RF
envelope signal will be coupled through the radiation into the audio signal path, if the protection is not good, it
will produce an audible TDD Noise, which includes the 217Hz noise And a harmonic noise signal of 217 Hz.
ti
a
l
VBAT
Voltage
4.615ms
Figure 11
e
n
RF
Signal
Schematic Diagram of Power Supply Voltage and RF Signal during GSM RF Operation
fi
d
RNS fully inhibit the conduction and radiation interference by the AWINIC unique circuit architecture.
Effectively improve the ability to suppress TDD Noise.
Conduction noise suppression
o
n
When the RF power amplifier is operating, it will draw the current from the battery by 217Hz frequency, Power
supply will be introduced to 217Hz power ripple since the battery has a certain internal resistance, it will be
coupled to the speaker through the audio power amplifier. The ability to suppress power fluctuations depends
on the PSRR of the audio power amplifier.
vout ac
)
vdd ac
C
PSRR 20 log(
a
w
in
ic
Due to the input and output of the fully differential amplifier is perfectly symmetrical, theoretically, the effect of
the power supply fluctuation on the two outputs is exactly the same, and the differential output is completely
unaffected by the power supply fluctuation. In practice, due to process bias and other factors, the amplifier will
have a certain mismatch, PSRR is generally better than -60dB, it shows the output relative to the power
fluctuations can be reduced by 1000 times, such as 500mVp power fluctuations, the differential output of 0.5
MV, which basically can meet the application requirements.
But in practical applications, the power amplifier may encounter conduction of TDD Noise problem even if its
PSRR is -60dB or -80dB, why is this? Because we also need to consider the impact of peripheral power
mismatches of audio power amplifiers
For conventional audio power amplifiers, when the input resistor Rin and the input capacitor Cin mismatch,
will greatly affect the audio power amplifier PSRR indicators, in the case of 24 times the gain, PSRR will be
weakened to -46dB or so if the input resistance and Capacitor with 1% mismatch. PSRR will be weakened to
-28dB or so if the input resistance and input capacitance mismatch with 10% mismatch, when the power
fluctuations, it is easy to produce audible TDD Noise.
In order to enhance the audio power amplifier PSRR in the input resistance and input capacitance mismatch
case, AW87519 features a unique conduction noise suppression circuit, making the power amplifier to
maintain a high PSRR value even in the input resistance, the input capacitance deviation of 10% or more, this
greatly inhibits the generation of conducted noise.
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AW87519
May 2019 V1.1
Radiation noise suppression
VDD
INN
AW87519VON
fi
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VOP
Rin
n
Cin
INP
e
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ti
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Input traces, output traces, horn loops, and even power and ground loops are likely to be subject to RF
radiation interference in the audio signal module, longer input traces and output traces similar to the antenna,
especially vulnerable RF radiation effects.
The reasonable PCB layout can reduce the influence of RF radiation in the design, such as shorten the line
length of input and output as much as possible; audio devices should be shielded and far away from the RF
antenna, maintain the integrity of the device to audio signal pathway; to increase the small bypass capacitor
RF signals in the sensitive nodes. However, in practical applications, PCB layout is difficult to fully consider
the influence of RF radiation on the audio signal path, and some RF energy will still be coupled to the audio
signal path to form audible TDD Noise. Therefore, AW87519 features a unique RF radiation suppression
circuit, a shielding layer inside the chip, effectively prevent high frequency energy into RF chip, to ensure that
the drive single of the amplifier provided to the speaker will not be affected by the antenna RF radiation, thus
avoiding the antenna RF Radiation caused by TDD Noise.
C
o
GND
Figure 12
RF Radiation Coupling Graph
Class D amplifier without filter
w
in
ic
When the traditional class D amplifier is in idle state of no input signal, the output will have the inverse square
wave, it will directly above the load of the speaker, will form a large current power switch on the speaker,
therefore we need to increase the LC filter to restore the analog audio signal at the amplifier output. The LC
filter increase the cost and PCB layout area, while increase the power consumption, reduce the performance
of THD+N.
The AW87519 features a Class D amplifier without a filter, eliminating the need for an output LC filter. In the
idle state of no input signal, the two outputs (VOP, VON) of the amplifier are in-phase square waves and not
generate idle switching currents on the speaker load. When the input signal is added to the input terminal, the
duty ratio of the output is changed. The duty cycle of the VOP becomes larger and the duty cycle of the VON
becomes smaller, and the difference value of the output forms the differential amplified signal on the speaker.
a
EEE
The AW87519 features a unique Enhanced Emission Elimination (EEE) technology, that controls fast
transition on the output, greatly reduces EMI over the full bandwidth, fully meet FCC CLASS B specification
requirements.
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AW87519
May 2019 V1.1
Pop-Click Suppression
The AW87519 features unique timing control circuit, that comprehensively suppresses pop-click noise,
eliminates audible transients on shutdown, wakeup, and power-up/down.
Thermal AGC/ over temperature protection
e
Automatic recovery of overcurrent protection
n
ti
a
l
The AW87519 features the thermal AGC patented technology, can according to the chip temperature,
automatically adjust the gain of the system, reduce the power consumption of the chip, to prevent damage in
case of excessive temperature.
The AW87519 has an automatic temperature detection mechanism, when the chip temperature exceeds the
preset threshold of thermal AGC temperature (150°C), the chip will start the automatic gain control circuit to
decrease the gain of the system, thereby reducing the energy consumption of the chip, thus slow or stop chip
temperature continues to rise. When the chip temperature is restored to normal operating range (below
130°C), the automatic gain control circuit will restore the system gain to the original state. When the chip
operates in a fault condition, the chip temperature is too high, up to a preset temperature protection
temperature threshold (160°C), the system starts overheating protection, the chip will be turned off, restarts to
resume normal work when the chip temperature returns to normal operating range (less than 130°C).
a
w
in
ic
C
o
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AW87519 with automatic recovery of the output overcurrent protection function, when the overcurrent occurs,
AW87519 internal protection circuit will chip off to ensure that the chip is not damaged, when the short-circuit
fault is eliminated, the chip will automatically resume working without restarting.
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AW87519
May 2019 V1.1
Device Address
The I2C device address (7-bit) is decided by the connection of the AD pin. The connection of AD pin
configures the two LSB bits of the following 7-bit binary address A6-A0 of 10110A1A0. The permitted I2C
A1
A0
Connects to
GND
Connects to
SCL
Connects to
SDA
Connects to
VDD
0
0
I2C address
(7-bit)
0x58
0
1
0x59
1
0
0x5A
1
1
0x5B
n
AW87519 Address selection
e
Table 2
fi
d
I2C Timing feature
Parameter
MIN
Sym
1
fSCL
SCL Clock frequency
2
tLOW
SCL Low level Duration
3
tHIGH
SCL High level Duration
4
tRISE
SCL, SDA rise time
5
tFALL
SCL, SDA fall time
6
tSU:STA
Setup time SCL to START state
7
tHD:STA
8
tSU:STO
tSU:DAT
tHD:DAT
UNIT
400
kHz
1.3
μs
0.6
μs
C
o
MAX
0.3
μs
0.3
μs
(Repeat-start) Start condition hold time
0.6
μs
Stop condition setup time
0.6
μs
the Bus idle time START state to STOP state
1.3
μs
SDA setup time
0.1
μs
SDA hold time
10
ns
ic
μs
a
11
TYP
0.6
in
tBUF
w
10
Name
n
No.
9
ti
a
AD pin
l
addresses are 0x58(7bit) through 0x5B(7-bit). The address information is as following table.
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AW87519
May 2019 V1.1
(3)
(2)
tHI GH
tLOW
tRI SE
tFALL
(4)
(5)
SCL
tSU:DAT
tHD:DAT
(10)
(11)
SDA
Figure 13
SCL and SDA timing relationships in the data transmission process
tSU:STO
(7)
(8)
(6)
(9)
tSU:STA
tBUF
SDA
the Timing Relationship between START and STOP State
n
Figure 14
ti
a
tHD:STA
l
SCL
e
General I2C Operation
n
fi
d
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in
a system. The device is addressed by a unique 7-bit address; the same device can send and receive data. In
addition, Communications equipment has distinguish master from slave device: In the communication
process, only the master device can initiate a transfer and terminate data and generate a corresponding clock
signal. The devices using the address access during transmission can be seen as a slave device.
SDA and SCL connect to the power supply through the current source or pull-up resistor. SDA and SCL
default is a high level. All data to start transmission and end of transmission requires the main device to issue
START state and STOP status:
START state：The SCL maintain a high level, SDA from high to low level
ic
C
o
STOP state：The SCL maintain a high level, SDA pulled low to high level
Start and Stop states can be only generated by the master device. In addition, if the device does not produce
STOP state after the data transmission is completed, instead re-generate a START state (Repeated START,
Sr), and it is believed that this bus is still in the process of data transmission. Functionally, Sr state and
START state is the same. As shown in Figure 15.
SCL
START
(S)
STOP
(P)
in
SDA
Figure 15
START and STOP State Generation Process
a
w
In the data transmission process, when the clock line SCL maintains a high level, the data line SDA must
remain the same. Only when the SCL maintain a low level, the data line SDA can be changed, as shown in
Figure 16. Each transmission of information on the SDA is 9 bits as a unit. The first eight bits are the data to
be transmitted, and the first one is the most significant bit (Most Significant Bit, MSB), the ninth bit is an
confirmation bit (Acknowledge, ACK or A ), as shown in Figure 17. When the SDA transmits a low level in
ninth clock pulse, it means the acknowledgment bit is 1, namely the current transmission of 8 bits data are
confirmed, otherwise it means that the data transmission has not been confirmed. Any amount of data can be
transferred between START and STOP state.
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AW87519
May 2019 V1.1
SCL
SDA
Data cable
Remains the same:
At this point the
data is valid
l
The Data Transfer Rules on the I2C Bus
ti
a
Figure 16
Data transmission:
In this case the data
is invalid
The whole process of actual data transmission is shown in Figure 17. When generating a START condition,
the master device sends an 8-bit data, including a 7-bit slave addresses (Slave Address), and followed by a
START or
repeated
START
(S or Sr)
1
2
8
9
R/W
ACK
1
SDA
Figure 17
9
MSB
STOP or
Repeated
START
(P or Sr)
ACK
Data Transmission on the I2C Bus
o
I2C Read/Write Processes
8
n
MSB
2
fi
d
SCL
e
n
"read / write" flag ( R/W ). The flag is used to specify the direction of transmission of subsequent data. The
master device will produce the STOP state to end the process after the data transmission is completed.
However, if the master device intends to continue data transmission, you can directly send a Repeated
START state, without the need to use the STOP state to end transmission.
C
The following describes two kinds of ways of the I2C bus data transmission:
Write Process
in
ic
Writing process refers to the master device write data into the slave device. In this process, the transfer
direction of the data is always unchanged from the master device to the slave device. All acknowledge bits are
transferred by the slave device, in particular, AW87519 as the slave device, the transmission process in
accordance with the following steps, as shown in Figure 18:
Master device generates START state. The START state is produced by pulling the data line SDA to a low
level when the clock SCL signal is a high level.
Master device transmits the 7-bits device address of the slave device, followed by the "read / write" flag (flag
R/W = 0);
a
w
The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is correct;
The master device transmits the 8-bit AW87519 register address to which the first data byte will written；
The slave device asserts an acknowledgment (ACK) bit to confirm the register address is correct;
Master sends 8 bits of data to register which needs to be written;
The slave device asserts an acknowledgment bit (ACK) to confirm whether the data is sent successfully;
If the master device needs to continue transmitting data, it does not need further to send the register address
for AW87519, within AW87519 each send confirmation bit(ACK) regret automatic accumulation register
address then only need to repeat the sixth step and seven step:
The master device generates the STOP state to end the data transmission.
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AW87519
May 2019 V1.1
(1)
(2)
slave device address
R/W
(4)
(5)
A
Register address
‘0’(write)
data
transmission
direction
(6)
(7)
(6r)
(7r)
A write data A write data A
(9)
STOP
Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Register address auto increment - (8)
From the master to the slave device
From slave to master device
Figure 18
Writing Process (Data Transmission Direction Remains the Same)
ti
a
Read Process
l
START
(3)
n
Reading process refers to the slave device reading data back to the master device. In this process, the
direction of data transmission will change. Before and after the change, the master device sends START state
and slave address twice, and sends the opposite "read/write" flag. In particular, AW87519 as the slave device,
the transmission process carried out by following steps listed in Figure 19:
Master device asserts a start condition;
fi
d
e
Master device transmits the 7 bits address of AW87519, and followed by a "read / write" flag ( R/W = 0);
The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is correct;
The master device sends the 8bit address that the AW87519 register needs to read the data;
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or
not;
The master device restarts the data transfer process by continuously generating STOP state and START
state or a separate Repeated START.
C
o
n
Master sends 7-bits address of the slave device and followed by a read / write flag (flag R/W = 1) again.
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or
not.
The master transmits 8 bits of data to register which needs to be read;
The slave device sends an acknowledgment bit (ACK) to confirm whether the data is sent successfully.
AW87519 automatically increment register address once after the slave sent each acknowledge bit (ACK).
The master device generates the STOP state to end the data transmission.
(2)
START
slave device address R/W
(3)
(4)
(5)
(6)
A
Register address
A
Sr
ic
(1)
(7)
slave device address
‘0’(write)
From the master to the slave device
From slave to master device
R/W
A
(9)
(10)
Read data A
(9r)
(10r)
Read data A
(12)
STOP
‘1’(read) Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Sr = repeated START
or Send STOP state before sending START state
Register address auto increment - (11)
in
data
transmission
direction
(8)
Reading Process (Data Transmission Direction Remains the Same)
a
w
Figure 19
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AW87519
May 2019 V1.1
Register List
name
addres
s
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Chip ID
0x00
0
1
0
1
1
0
0
1
SYSCTRL
0x01
EN_SW
EN_CP
EN_BOOST
EN_PA
0
0
BAT_SFGD
_VTH(2) [1]
BAT_SFGD
_VTH(2) [0]
BST_VOUT(4)
[4]
BST_VOUT(4)
[3]
BST_IPEAK[1
]
0
BSTVOUT
0x03
1
1
FORCE_BOO
ST
BSTCP
0x04
0
0
0
BST_IPEAK[2]
0
0
BAT_SFGD_L
EVEL(3) [1]
BST_VOUT(4)
[1]
BAT_SFGD_L
EVEL(3) [0]
BST_VOUT(4)
[0]
l
0x02
0
EN_BAT_SFG
D
BST_VOUT(4)
[2]
BST_IPEAK[0
]
(1)
0
1
ti
a
BATSAFE
RCV_MODE
0x05
0
0
0
PA_GAIN[4]
PA_GAIN[3]
PA_GAIN[2]
PA_GAIN[1]
PA_GAIN[0]
0x06
0
1
0
PD_AGC3
AGC3_Po[3]
AGC3_Po[2]
AGC3_Po[1]
AGC3_Po[0]
AGC3
0x07
AGC3_RT[2]
AGC3_RT[1]
AGC3_RT[0]
AGC3_AT[2]
AGC3_AT[1]
AGC3_AT[0]
1
0
AGC2_Po
0x08
0
0
0
0
AGC2_Po[3]
AGC2_Po[2]
AGC2_Po[1]
AGC2_Po[0]
AGC2
0x09
0
0
0
AGC2_AT[2]
AGC2_AT[1]
AGC2_AT[0]
0
0
0x0A
0
1
0
0
1
AGC1_AT[1]
AGC1_AT[0]
PD_AGC1
(2)
(3)
(4)
register
0x00
0x01
0x02
0x03
0x04
0xC8
Default
0x59
0x70
0x09
e
RCV_MODE: enable 2-in-1 receiver application
BAT_SFGD_VTH: Battery voltage when enter into battery
safe_guard mode
BAT_SFGD_LEVEL: Maxim output level when enter into battery
safe_guard mode
BST_VOUT: Boost output voltage
(1)
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AGC1
n
PAGAIN
AGC3_Po
0x05
0x06
0x05 (RCV_MODE=1)
0x11
0x53
0x10 (RCV_MODE=0)
0x09
0x4E
0x08
0x03
0x4A
AW87519 Register Initial Value
ic
C
Any register address which is more than 0x0A and all reserved bits are reserved for debugging and testing
purposes. Changing their values may affect the normal function of the power amplifier; Reading them will get
any possible values. AW87519’s I2C address is 10110A2A1, as shown in Table 4, in order to avoid conflict
with other I2C devices address, you can connect AD pin to GND，SCL，SDA，VDD to set the value of A2 and
A1, respectively. The following lists specific information about all visible registers, including default values and
programmable ranges.
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
1
0
A2
A1
R/W
w
in
Bit7
Table 4
AW87519 Address Byte
CHIP ID Register (address: 0x00)
Name
R/W
Default
7:0
IDCODE
R
0x59
a
I2C Bit
Description
Chip ID will be returned after reading.
All configuration registers will be reset to default
values after 0xAA is written.
SYSTEM CONTROL (SYSCTRL) Register (address: 0x01)
I2C Bit
Name
R/W
Default
7
EN_SW
R/W
0
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Description
Chip Software Enable
0: Chip Software Disable:
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25
0x0A
0x4B
o
Table 3
0x08
0x0B
0x43
n
0xE8
0x07
AW87519
EN_CP
R/W
1
5
EN_BOOST
R/W
1
4
EN_PA
R/W
1
3
RCV_MODE
R/W
0
2:0
--
--
000
ti
a
6
Shutdown the whole chip except PORN.
1: Chip Software Enable
Chargepump Enable:
0: Disable Chargepump, PVDD=VBAT
1: Enable Chargepump
BOOST enable
0: Disable BOOST，BOOST power down
1: Enable BOOST
PA output Enable
0: Disable PA
1: Enable PA
CLASS D receiver function enable
0：Receiver mode disabled
1：Enable Receiver mode
Reserved and Unused
R/W
--
Default
000
4:3
BAT_SFGD_
VTH
R/W
01
2
EN_BAT_SF
GD
R/W
0
1:0
BAT_SFGD_
LEVEL
R/W
Description
Reserved and Unused
Setting Battery Threshold Voltage for Triggering
Battery Safeguard Mode:
00：threshold voltage is 3.3V
01:threshold voltage is 3.4V
10:threshold voltage is 3.5V
11:threshold voltage is 3.6V
Software control battery safeguard，when
FORCE_BOOST=0, this bit is set to be 0.
0: Software control battery safeguard disable
1: Software control battery safeguard enable
Setting Maximum Output Level when Battery
Safeguard Mode Triggered
00: 5.0Vp
01: 5.5Vp
10: 6.0Vp
11: 6.5Vp
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Name
--
n
BATTERY SAFEGUARD (BATSAFE)Register (address: 0x02)
I2C Bit
7:5
l
May 2019 V1.1
C
01
BOOST OUTPUT VOLTAGE (BSTVOUT) Register (address: 0x03)
Name
--
R/W
--
Default
11
5
FORCE_
BOOST
R/W
1
Description
Reserved and Unused
Boost output voltage enable
0：direct through mode，PVDD=VBAT
1：force boost output voltage
BOOST output voltage set
01001~11111: Unavailable
01000: 8.5V
00111: 8.25V
00110: 8.0V
00101: 7.75V
00100: 7.5V
00011: 7.25V
00010: 7.0V
00001: 6.75V
00000: 6.5V
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I2C Bit
7:6
BST_VOUT
R/W
01000
a
4:0
BOOST CONTROL PARAMETER (BSTCP) Register (address: 0x04)
I2C Bit
Name
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R/W
Default
Description
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AW87519
May 2019 V1.1
--
000
4:2
BST_IPEAK
R/W
100
1:0
--
--
01
Reserved and Unused
BOOST peak current limit
000: 2.5A
001: 2.75A
010: 3.0A
011: 3.25A
100: 3.5A
101: 3.75A
110: 4.0A
111: 4.25A
Reserved and Unused
GAIN CONTROL (Gain) Register (address: 0x05)
For RCV_MODE=1, (Speaker & Receiver 2-in-1Mode):
I C Bit
7:5
Name
--
R/W
--
Default
000
Description
Reserved and Unused
Setting Class D Amplifying Gain
n
2
R/W
00000~00100
00101: 7.5dB
00110: 9.0dB
00111: 10.5dB
00101
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Gain
For RCV_MODE=0,(Speaker Mode):
I2C Bit
7:5
R/W
--
Default
000
Reserved and Unused
Rini=30kΩ
Rini=24kΩ
Rini=28kΩ
Description
Reserved and Unused
Setting Class D Amplifying Gain
n
Name
--
e
Gain
4:0
l
--
ti
a
7:5
Gain
R/W
10000
ic
4:0
C
o
Gain
01000: 12dB
01001: 13.5dB
01010: 15.0dB
01011: 16.5dB
01100: 18.0dB
01101: 19.5dB
01110: 21dB
01111: 22.5dB
10000: 24dB
10001: 25.5dB
10010: 27dB
10011~11111: Unavailable
Rini=36.5kΩ
Rini=30kΩ
Rini=25kΩ
Rini=21.5kΩ
Rini=18kΩ
Rini=15.5kΩ
Rini=12.5kΩ
Rini=11kΩ
Rini=9kΩ
Rini=7.5kΩ
Rini=6.5kΩ
Name
--
R/W
--
Default
010
w
I2C Bit
7:5
in
CLASS D AGC3 OUTPUT POWER (AGC3_Po) Register (address: 0x06)
PD_AGC3
R/W
0
3:0
AGC3_Po
R/W
0011
a
4
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Description
Reserved and Unused
Disable AGC3
0:Enable AGC3
1:Disable AGC3
Setting AGC3 Output Power for Protecting Speaker
and stereo Receiver
0000: 0.5W@8Ω
0.667W@6Ω
0001: 0.6W@8Ω
0.8W@6Ω
0010: 0.7W@8Ω
0.933W@6Ω
0011: 0.8W@8Ω
1.067W@6Ω
0100: 0.9W@8Ω
1.2W@6Ω
0101: 1.0W@8Ω
1.333W@6Ω
0110: 1.1W@8Ω
1.467W@6Ω
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AW87519
May 2019 V1.1
1.6W@6Ω
1.733W@6Ω
1.867W@6Ω
2.0W@6Ω
2.133W@6Ω
2.267W@6Ω
2.4W@6Ω
2.533W@6Ω
2.667W@6Ω
l
0111: 1.2W@8Ω
1000: 1.3W@8Ω
1001: 1.4W@8Ω
1010: 1.5W@8Ω
1011: 1.6W@8Ω
1100: 1.7W@8Ω
1101: 1.8W@8Ω
1110: 1.9W@8Ω
1111: 2.0W@8Ω
R/W
Default
7:5
AGC3_RT
R/W
010
4:2
AGC3_AT
R/W
011
1:0
--
--
10
Description
Setting Release Time of AGC3:
000: 5.12ms/dB
001: 10.24ms/dB
010: 21 ms/dB
011: 41 ms/dB
100: 82 ms/dB
101: 164 ms/dB
110: 328 ms/dB
111: Unavailable
Setting Attack Time of AGC3:
000: 1.28ms/dB
001: 2.56ms/dB
010: 10.24ms/dB
011: 20.48ms/dB
100: 41ms/dB
101: 82ms/dB
110: 164ms/dB
111: 328ms/dB
Reserved and Unused
n
Name
o
n
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I2C Bit
ti
a
CLASS D AGC3 PARAMETER (AGC3) Register (address: 0x07)
CLASS D AGC2 OUTPUT POWER(AGC2_Po) Register (address: 0x08)
Name
R/W
7:4
--
--
Default
C
I2C Bit
0000
Setting AGC2 Output Power:
in
ic
0000: 1.0W@8Ω
0001: 1.2W@8Ω
0010: 1.4W@8Ω
0011: 1.6W@8Ω
0100: 1.8W@8Ω
0101: 2.0W@8Ω
0110: 2.2W@8Ω
0111: 2.4W@8Ω
1000: 2.6W@8Ω
1001: 2.8W@8Ω
1010: 3.0W@8Ω
1011: AGC2 OFF
1100~1111: Unavailable
AGC2_Po
R/W
0011
a
w
3:0
Description
Reserved and Unused
1.333W@6Ω
1.6W@6Ω
1.867W@6Ω
2.133W@6Ω
2.4W@6Ω
2.667W@6Ω
2.933W@6Ω
3.2W@6Ω
3.467W@6Ω
3.733W@6Ω
4W@6Ω
CLASS D AGC2 PARAMETER (AGC2) Register (address: 0x09)
2
I C Bit
7:5
Name
--
R/W
--
Default
000
4:2
AGC2_AT
R/W
010
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Description
Setting Attack Time of AGC2:
000: 0.16ms/dB
001: 0.32ms/ dB
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AW87519
May 2019 V1.1
1:0
--
--
010: 0.64ms/dB
011: 2.56ms/dB
100: 10.24ms/dB
101: 41ms/dB
110: 82ms/dB
111: 164ms/dB
Reserved and Unused
00
Name
--
R/W
--
Default
01001
2:1
AGC1_AT
R/W
01
0
PD_ AGC1
R/W
0
Description
Reserved and Unused
Setting Fastest Level AGC Attack Time:
00: 0.04ms/dB
01: 0.08ms/dB
10: 0.16ms/dB
11: 0.32ms/dB
AGC1 control bit
0: AGC1 Enable
1: AGC1 Disable
a
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in
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C
o
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ti
a
I C Bit
7:3
l
CLASS D AGC1 PARAMETER (AGC1) Register (address: 0x0A)
2
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AW87519
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APPLICATION INFORMATION
EXTERNAL COMPONENTS
BOOST INDUCTOR SELECTION
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Selecting inductor needs to consider Inductance, size, magnetic shielding, saturation current and temperature
current.
a) Inductance
Inductance value is limited by the boost converter's internal loop compensation. In order to ensure phase
margin sufficient under all operating conditions, recommended 1μH inductor.
b) Size
For a certain value of inductor, the smaller the size, the greater the parasitic series resistance of the inductor
DCR, the higher the loss, corresponds to the lower efficiency.
c) Magnetic shielding
Magnetic shielding can effectively prevent the inductance of the electromagnetic radiation interference. It is
much better to choose inductance with magnetic shielding in the application of EMI sensitive environment.
d) Saturation current and temperature rise of current
Inductor saturation current and temperature rise current value are important basis for selecting the inductor.
As the inductor current increases, on the one hand, since the magnetic core begins to saturate, inductance
value will decline; on the other hand, the inductor's parasitic resistance inductance and magnetic core loss
can lead to temperature rise. In general, the current value is defined as the saturation current ISAT when the
inductance value drops to 70%; the current value is defined as temperature rise current IRMS when inductance
temperature rise 40℃.
For particular applications, need to calculate the maximum IL_PEAK and IL_RMS, which is a basis of selecting the
inductor. When VDD = 4.2V, PVDD=8 .5V, RL = 8Ω，amplifier RDSON = 250mΩ, when THD = 1% (the maximum
power without distortion), the output power is calculated as follows:
2
ic
C
2
RL
8
VOUT
8.5
RL RDSON
8 0.25
POUT
4.3 W
2 RL
28
In such a large output power, the overall efficiency of the power amplifier is typically 80%, in order to calculate
the maximum average current IMAX_AVG_VDD and maximum peak current IMAX_PEAK_VDD drawn from VDD:
P
4.3
IMAX _ AVG_VDD OUT
A 1.28A
VDD η 4.2 0.8
in
IMAX _ PEAK_VDD 2 IMAX _ AVG_VDD 2.56A
If inductor DCR is 50mΩ, the inductor power loss at this time is:
2
2
PDCR,LOSS 1.5 IMAX
_ AVG_VDD DCR 1.5 1.28 0.05W 123mW
w
Wherein the coefficient 1.5 is the square of the ratio of the sine wave current RMS value and average value
(there is no consideration of the impact of the inductor ripple, the actual DCR loss will be even greater). If the
a
loss which is resulting from DCR is less than 1% at maximum efficiency (POUT = 2.5W, η = 80%), then:
IAVG_VDD
DCR
POUT
2.5
0.74A
VDD η 4.2 0.8
PDCR ,LOSS
POUT
0.01 2.5
0.01
38m
2
2
1.5 IAVG
1
.
5
I
1
.
5
0.742 0.8
_ VDD
AVG_ VDD
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AW87519
May 2019 V1.1
According to the working principle of the Boost, we can calculate the size of the inductor current
ripple ΔIL:
VDD VOUT VDD
4.2 8.5 4.2
A 1.33A
VOUT f L
8.5 1.6 106 1 10 6
IL _ PEAK IMAX _ PEAK _VDD
ti
a
Thus, the maximum peak inductor current IL_PEAK and maximum effective inductor current IL_RMS is:
ΔIL
1.33
2.56
A 3.23A
2
2
ΔIL2
1.332
2.562
A 2.6 A
12
12
n
2
IL_RMS IMAX
_ PEAK _ VDD
l
ΔIL
n
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From the above calculation results:
1) For typical DCR about 38mΩ inductance, the efficiency loss caused by around1.5%;
2) In practice, the maximum output power of the amplifier is likely to reach 4.3W in an instant, so the
selected inductor saturation current ISAT requires more than the maximum inductor peak current IL_PEAK;
3) In some cases, if the IL_PEAK calculated according to the above method is greater than the set of input
inductor current limit value ILIMIT, shows the power amplifier is restricted by inductance input current limit,
the actual maximum output power is less than the calculated value, the measured value shall prevail, and
ISAT need greater than the set current limiting value ILIMIT, and cannot be less than 2.56A;
4) Take PVDD = 8.5V for example, under different conditions, the typical method of selecting I SAT in the
following table:
RL
(Ω)
ILIMIT
(A)
4.2
8.5
8
4
4.2
8.5
6
4
PO
(W)
IL_PEAK
(A)
Inductor
saturation
current ISAT
minimum value
(A)
80
4.3
3.23
4.2
75
5.3
4
4.2
o
PVDD
(V)
Efficiency(η)
(%)
C
VDD
(V)
a
w
in
ic
5) As the result of the action of AGC，amplifier will not work long hours at maximum power without distortion,
the actual average inductor current is far less than the maximum inductor current effective I L_RMS, so when
selecting the inductor, the inductor temperature rise current is not usually a limiting factor;
6) Inductor Selection example: the inductor package size is 252012, inductance value is 1μH, DCR Typical
value is 47mΩ, the typical saturation current ISAT is 4.2A, the typical temperature rise current IRMS is 2.8A,
suitable for VDD=3.6V, PVDD=8.5V, speaker impedance RL=8Ω, inductor input current limit ILIMIT= 4.2A. If
you choose ISAT or IRMS of the inductance is too small, it is possible to cause the chip don’t work properly,
or the temperature of the inductance is too high.
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Inductance value
size
DCR（Ω）
1uH
2.5×2.0×1.2mm
0.047
ISAT（A） IRMS（A）
4.2
2.8
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AW87519
May 2019 V1.1
Capacitor Selection
BOOST CAPACITOR SELECTION
a)
ti
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l
The output capacitor of chargepump is usually within the range 0.1μF~47μF, It needs to use Class II type (EIA)
multilayer ceramic capacitors (MLCC). Its internal dielectric is ferroelectric material (typically BaTiO3), a high
the dielectric constant in order to achieve smaller size, but at the same Class II type (EIA) multilayer ceramic
capacitors has poor temperature stability and voltage stability as compared to the Class I type (EIA)
capacitance. Capacitor is selected based on the requirements of temperature stability and voltage stability,
considering the capacitance material, capacitor voltage, and capacitor size and capacitance values.
temperature stability
b)
e
n
Class II capacitance have different temperature stability in different materials, usually choose X5R type in
order to ensure enough temperature stability, and X7R type capacitance has better properties, the price is
relatively more expensive. X5R capacitance change within ±15% in temperature range of 55°C to 85°C, X7R
capacitance change within ±15% in temperature range of -55°C~125°C. The output capacitance of the
AW87519’s chargepump recommends X5R ceramic capacitors.
Voltage Stability
a
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in
ic
C
o
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fi
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Class II type capacitor has poor voltage stability ——Capacitance values falling fast along with the DC bias
voltage applied across the capacitor increasing. The rate of decline is related to capacitance material,
capacitors rated voltage, capacitance volume. Take for TDK C series X5R for example, its pressure voltage
value is 16V or 25V, the package size is 0805, 1206 or 0603, the capacitance value is 10μF. The capacitor’s
voltage stability of different types of capacitor is as shown below:
Figure 20
Different Types of Capacitive Voltage Stability
It can be found that the rate of capacitance capacity value descent becomes slow along with "large capacitor
size, capacitance pressure voltage rise”. The larger the package size, the better voltage stability. The higher
the height, the better voltage stability with the same length and width of the capacitance. Voltage stability of
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AW87519
May 2019 V1.1
material
size (mm3)
rated
voltage
(V)
quantity
value@8.5V
10uF
X5R
1.60×0.80×0.80
(0603)
16
4
6uF
10uF
X5R
2.00×1.25×1.25
(0805)
25
3
6.3uF
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value
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smaller package size (0603) capacitor change affected by the pressure value is very small.
In AW87519 typical applications, it is necessary to ensure the output value of the PVDD capacitor
≥6μF when PVDD=8.5V.
Take the following capacitances as the Boost of the output capacitor for example:
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As for the different manufacturers’ capacitors, it’s important to determine the type and quantity of the
capacitors through the capacitor voltage stability data provided by the manufacturer.
Input Capacitor-Cin（input high-pass cutoff frequency）
1
(Hz)
2 π Rintotal Cin
fi
d
fH ( 3dB)
e
The input capacitors and input resistors form a high-pass filter to filter out the DC component of the input
signal. The -3dB frequency points of the high pass filter is shown below：
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The selection of a smaller Cin capacitor in the application helps to filter out 217Hz noise, which comes from
the input coupling, and the smaller capacitor is advantageous to reduce the pop-click noise when the power
amplifier turn on.Better matching of the input capacitors improves performance of the circuit and also helps to
suppress pop-click noise. A capacitor value deviation of 10% or better capacitance is recommended.
Take typical application as an example, the input high-pass cutoff frequency is calculated as below:
o
1
1
(Hz) 260Hz
2 π Rintotal Cin 2 π 9kΩ 68nF
C
fH (3dB)
Class D-type speaker & receiver 2-in-1 application (Gain=9dB), the input high pass frequency is as follows:
1
1
(Hz) 98Hz
2 π Rintotal Cin 2 π 24kΩ 68nF
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fH (3dB)
in
Supply Decoupling Capacitor（CS）
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A good decoupling capacitor can improve the efficiency and the best performance of the power amplifier. At
the same time, in order to get good high frequency transient performance, the ESR value of the capacitor
should be as small as possible. In AW87519 applications, low ESR (equivalent-series-resistance) X7R or X5R
ceramic capacitors are recommended. Generally, 10μF ceramic capacitors are used to bypass the VDD to the
ground, and the decoupling capacitor should be placed as close to the VDD chip as possible in the layout. If
you want to filter out low-frequency noise better, you need to add a 10μF or greater decoupling capacitor
depending on your application. Meanwhile, a 33pF~0.1μF ceramic capacitor is placed on the pin of the power
supply to filter the high frequency interference on the power supply. The capacitor should be placed as close
as possible to the pin3 and inductor.
Output beads, capacitors, TVS
Using EEE technology, in the class K mode, the AW87519 can also meet the FCC CLASS B specification
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AW87519
May 2019 V1.1
requirements. It is recommended to Use ferrite chip beads and capacitors if device near the EMI sensitive
circuits, there are long leads from amplifier to speaker, placed as close as possible to the output pin.
Waveform
before Bead
Waveform after
Bead
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Bead
0.1nF
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VOP
16V
Bead
VON
Ferrite Chip Bead and Capacitor
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Figure 21
16V
n
0.1nF
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Amplifier output is a square wave signal. The voltage across the capacitor will be much larger than the PVDD
voltage after increasing the bead capacitor. It suggested the use of rated voltage above 16V capacitor. At the
same time a square wave signal at the output capacitor switching current form, the static power consumption
increases, so the output capacitance should not be too much which is recommended 0.1nF ceramic capacitor
rated voltage of 16V. If you want to get better EMI suppression performance, can use 1nF, rated voltage 16V
capacitor, but quiescent current will increase.
Power amplifier output PWM signals of high voltage to PVDD voltage, voltage to 8.5 V, will produce some
ringing after bead capacitor, resulting in higher peak voltage. Recommended choose the operating voltage of
16V TVS.
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AW87519
May 2019 V1.1
PCB AND DEVICE LAYOUT CONSIDERATION
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EXTERNAL COMPONENTS PLACEMENT
Figure 22
AW87519 External Components Placement
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LAYOUT CONSIDERATIONS
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in
This device is a power a power amplifier chip. To obtain the optimal performance, PCB layout should be
considered carefully. The suggested Layout is illustrated in the following diagram:
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35
AW87519
Figure 23
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May 2019 V1.1
AW87519 Board Layout
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In order to obtain excellent performance of AW87519, PCB layout must be carefully considered. The design
consideration should follow the following principles:
1. In AW87519 peripheral device layout, you first need to guarantee the chargepump output capacitance
close to VBST pin.
2. All the filter capacitors of the audio PA (including CVDD, CVBST and CVREG) should be placed close to
the pins of the chip.
3. Please place the VREG capacitor close to the VBST capacitor. The parasitic inductance of the CVREG
capacitor should be less than 3nH. Minimize inductance as much as possible.
4. Traces of SW pin should support currents up to device over-current limit (peak current 3.5A).
5. Try to provide a separate short and thick power line to AW87519, the copper width is recommended to be
larger than 0.75mm. The decoupling capacitors should be placed as close as possible to boost power
supply pin.
6. The input capacitors should be close to AW87519 INN and INP input pin, the input line should be parallel
to suppress noise coupling.
7. The beads and capacitor should be placed near to AW87519 VON and VOP pin. The output line from
AW87519 to speaker should be as short and thick as possible. The width is recommended to be larger
than 0.5mm.
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AW87519
May 2019 V1.1
TAPE & REEL DESCRIPTION
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
K0
W
l
B0
Cavity
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D1
A0
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A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D1：Reel Diameter
D0：Reel Width
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D0
Pin 1
Q3
Q4
Q1
Q2
Q1
Q2
o
Q2
Q3
Q4
Q3
Q4
Q1
Q2
Q3
Q4
Sprocket Holes
User Direction of Feed
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Q1
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QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
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Pocket Quadrants
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AW87519
May 2019 V1.1
PACKAGE DESCRIPTION
2.000±0.100
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3.000±0.100
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PIN1 Corner
0.152 Ref.
0.550±0.050
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0.000~0.050
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0.400 TYP d
10
C
7
6
SYMM
℄
in
0.400 TYP
b
1
16
20
0.150 REF
17
SYMM
℄
19X(0.300±0.050)
a
Note: a=b=c=d=e=f=0.120mm
a
w
0.250±0.050
20X(0.200±0.050)
c
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f
11
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AW87519
May 2019 V1.1
LAND PATTERN
20X0.20
20X0.40
20
17
1
16
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8X 0.12 REF
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8X 0.12 REF
0.40 TYP
n
3.20
SYMM
fi
d
e
℄
6
11
7
SYMM
o
0.40 TYP
n
10
℄
C
2.20
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0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK DEFINED
a
NON-SOLDER MASK DEFINED
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METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
w
in
0.05 MAX
ALL AROUND
Unit：mm
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39
AW87519
May 2019 V1.1
VERSION INFORMATION
V1.0
2019-01-28
AW87519FCR datasheet V1.0
V1.1
2019-05-24
1. Modify PCB and Device Layout
2. Modify package description and Land pattern
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Date
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Description
Version
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COPYRIGHT ©2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD.
40
AW87519
May 2019 V1.1
DISCLAIMER
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC
Technology Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed
or implied, as to the accuracy or completeness of such information and shall have no liability for the
consequences of use of such information.
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AWINIC Technology reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions, at any time and without notice.
Customers shall obtain the latest relevant information before placing orders and shall verify that such
information is current and complete. This document supersedes and replaces all information supplied
prior to the publication hereof.
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AWINIC Technology products are not designed, authorized or warranted to be suitable for use in
medical, military, aircraft, space or life support equipment, nor in applications where failure or
malfunction of an AWINIC Technology product can reasonably be expected to result in personal injury,
death or severe property or environmental damage. AWINIC Technology accepts no liability for inclusion
and/or use of AWINIC Technology products in such equipment or applications and therefore such
inclusion and/or use is at the customer’s own risk.
n
Applications that are described herein for any of these products are for illustrative purposes only.
AWINIC Technology makes no representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time
of order acknowledgement.
o
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
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C
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if
reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations,
and notices. AWINIC is not responsible or liable for such altered documentation. Information of third
parties may be subject to additional restrictions.
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Resale of AWINIC components or services with statements different from or beyond the parameters
stated by AWINIC for that component or service voids all express and any implied warranties for the
associated AWINIC component or service and is an unfair and deceptive business practice. AWINIC is
not responsible or liable for any such statements.
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