IP4856CX25/CZ

IP4856CX25/C SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection Rev. 3 — 13 December 2019 Product data sheet 1. General description The device is an SD 3.0-compliant 6-bit bidirectional dual voltage level translator. It is designed to interface between a memory card operating at 1.8 V or 2.9 V signal levels and a host with a fixed nominal supply voltage of 1.7 V to 3.6 V. The device supports SD 3.0, SDR104, SDR50, DDR50, SDR25, SDR12 and SD 2.0 high-speed (50 MHz) and default-speed (25 MHz) modes. The device has an integrated voltage selectable low dropout regulator to supply the card-side I/Os, built-in EMI filters and robust ESD protections (IEC 61000-4-2, level 4). 2. Features and benefits • • • • • • • • • • Supports up to 208 MHz clock rate Feedback channel for clock synchronization SD 3.0 specification-compliant voltage translation to support SDR104, SDR50, DDR50, SDR25, SDR12, high-speed and default-speed modes 100 mA low dropout voltage regulator to supply the card-side I/Os Low power consumption by push-pull output stage with break-before-make architecture Integrated pull-up and pull-down resistors: no external resistors required Integrated EMI filters suppress higher harmonics of digital I/Os Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side Level shifting buffers keep ESD stress away from the host (zero-clamping concept) 25-ball WLCSP; pitch 0.4 mm 3. Applications • • • • • • Smartphone Mobile handsets Digital cameras Tablet PCs Laptop computers SD, MMC or microSD card readers 4. Ordering information Table 1. Ordering information Type number Package IP4856CX25/C Name Description WLCSP25 wafer level chip-size package with back side coating; 25 bumps (5 x 5); typical size: 2.05 mm x 2.05 mm x 0.51 mm IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 5. Marking Table 2. Marking code Type number Marking code IP4856CX25/C 856 pin A1 marker aaa-029856 Fig. 1. Marking description IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 2 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 6. Block diagram VSUPPLY VCCB DC/DC VSUPPLY VCCA VSD_REF IP4856CX25 SEL LDO + CONTROL LOGIC ENABLE CLK_IN CLK_FB CLK_SD CMD_DIR CMD_H HOST/ BASE BAND EMI 2 kV ESD PROTECTION DIR_0 CMD_SD EMI FILTER AND RESISTOR NETWORK DATA0_H 8 kV ESD PROTECTION DIR_1_3 DATA0_SD DATA1_H DATA1_SD DATA2_H DATA2_SD DATA3_H DATA3_SD WP CD MEMORY CARD WP ESD CD aaa-012881 Fig. 2. Block diagram IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 3 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 7. Functional diagram VSUPPLY SEL CARD SIDE 1.8 V OR 2.9 V R21 VSD_REF R38 CLK_IN CLK_FB VOLTAGE SELECT + INTERNAL REFERENCE VOLTAGE REGULATOR VLDO R31 R1 R32 R10 DIR_CMD CMD_H R2 R11 R3 DATA0_SD R34 R12 DIR_1_3 DATA1_H CMD_SD R33 DIR_0 DATA0_H CLK_SD R4 DATA1_SD R35 R13 R5 DATA2_H DATA2_SD R36 R6 DATA3_H DATA3_SD R37 R7 VCCA R14 ENABLE R20 R15 CD R30 WP GND aaa-004565 Fig. 3. Functional diagram IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 4 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 8. Pinning information 8.1. Pinning bump A1 index area 1 2 3 4 5 A B C D E aaa-015216 transparent top view, solder balls facing down Fig. 4. Pin configuration WLCSP25 Table 3. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol A1 DATA2_H A2 DIR_CMD A3 DIR_0 A4 VSUPPLY A5 DATA2_SD B1 DATA3_H B2 SEL B3 VCCA B4 VLDO B5 DATA3_SD C1 CLK_IN C2 ENABLE C3 GND C4 VSD_REF C5 CLK_SD D1 DATA0_H D2 CMD_H D3 CD D4 CMD_SD D5 DATA0_SD E1 DATA1_H E2 CLK_FB E3 DIR_1_3 E4 WP E5 DATA1_SD 8.2. Pin description Table 4. Pin description Symbol[1] Pin Type[2] Description IP4856CX25_C Product data sheet DATA2_H A1 I/O data 2 input or output on host side DIR_CMD A2 I direction control input for command DIR_0 A3 I direction control input for data 0 VSUPPLY A4 S supply voltage (from battery or regulator) DATA2_SD A5 I/O data 2 input or output on memory card side DATA3_H B1 I/O data 3 input or output on host side SEL B2 I card side I/O voltage level select VCCA B3 S supply voltage from host side VLDO B4 O internal supply decoupling DATA3_SD B5 I/O data 3 input or output on memory card side CLK_IN C1 I clock signal input on host side ENABLE C2 I device enable input GND C3 S supply ground All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 5 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection Symbol[1] Pin Type[2] Description VSD_REF C4 I reference voltage for the internal voltage regulator CLK_SD C5 O clock signal output on memory card side DATA0_H D1 I/O data 0 input or output on host side CMD_H D2 I/O command input or output on host side CD D3 O card detect switch biasing output CMD_SD D4 I/O command input or output on memory card side DATA0_SD D5 I/O data 0 input or output on memory card side DATA1_H E1 I/O data 1 input or output on host side CLK_FB E2 O clock feedback output on host side DIR_1_3 E3 I direction control input for data 1, data 2, data 3 WP E4 O write protect switch biasing output DATA1_SD E5 I/O data 1 input or output on memory card side [1] [2] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards. I = input, O = output, I/O = input and output, S = power supply. 9. Functional description 9.1. Level translator The bidirectional level translator shifts the data between the I/O supply levels of the host and the memory card. Dedicated direction control signals determine if a command and data signals are transferred from the memory card to the host (card read mode) or from the host to the memory card (card write mode). The voltage translator has to support several clock and data transfer rates at the signaling levels specified in the SD 3.0 standard specification. IP4856CX25_C Product data sheet Table 5. Supported modes Bus speed mode Signal level (V) Clock rate (MHz) Data rate (MB/s) Default-speed 3.3 25 12.5 High-speed 3.3 50 25 SDR12 1.8 25 12.5 SDR25 1.8 50 25 SDR50 1.8 100 50 SDR104 1.8 208 104 DDR 1.8 50 50 All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 6 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 9.2. Enable and direction control The pin ENABLE enables/disables the internal Low DropOut (LDO) regulator and is used to put the host-side and card-side I/O drivers into high-ohmic (3-state) mode. Table 6. I/O function control signal truth table Control Host side Pin Level[1] Pin Memory card side Function Pin Function Pin ENABLE = HIGH and VCCA ≥ 1.62 V DIR_CMD DIR_0 DIR_1_3 H CMD_H input CMD_SD output L CMD_H output CMD_SD input H DATA0_H input DATA0_SD output L DATA0_H output DATA0_SD input H DATA1_H input DATA1_SD output L DATA2_H DATA2_SD DATA3_H DATA3_SD DATA1_H output DATA1_SD DATA2_H DATA2_SD DATA3_H DATA3_SD input - - CLK_IN input CLK_SD output - - CLK_FB output - - Pin ENABLE = LOW or VCCA ≤ 0.8 V DIR_CMD X CMD_H high-ohmic CMD_SD high-ohmic DIR_0 X DATA0_H high-ohmic DATA0_SD high-ohmic DIR_1_3 X DATA1_H high-ohmic DATA1_SD high-ohmic Product data sheet DATA2_SD DATA3_H DATA3_SD - - CLK_IN input CLK_SD high-ohmic - - CLK_IN high-ohmic - - [1] IP4856CX25_C DATA2_H H = HIGH; L = LOW; X = don´t care All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 7 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 9.3. Integrated voltage regulator The low dropout voltage regulator delivers supply voltage for the voltage translators and the cardside input/output stages. It has to support 1.8 V and 3 V signaling modes as stipulated in the SD 3.0 specification. The switching time between the two output voltage modes is compliant with SD 3.0 specification. Depending on the signaling level at pin SEL, the regulator delivers 1.8 V (SEL = HIGH) or 2.9 V (SEL = LOW, VSD_REF < 1 V). For card supply voltage, see Section 9.4. Table 7. SD card side voltage level control signal truth table Input Output SEL[1] VSD_REF[1] VLDO Pin[2] Function H X 1.8 V DATA0_SD to DATA3_SD, CLK_SD low supply voltage level (1.8 V typical) L 1.5 V VSD_REF DATA0_SD to DATA3_SD, CLK_SD supply voltage level based on VSD_REF [1] [2] H = HIGH; L = LOW; X = don´t care. Host-side pins are not influenced by SEL. An external capacitor is needed between the regulator output pin VLDO and ground for proper operation of the integrated voltage regulator. See Table 9 for recommended capacitance and equivalent series resistance. It is recommended to place the capacitor close to the VLDO pin and maintain short connections to both, to the VLDO and to the ground. 9.4. Memory card voltage tracking (reference select) The device can track the memory card supply via pin VSD_REF. This allows achieving optimum interoperability by perfectly matching input/output levels between voltage translator and memory card in the 3 V signaling mode. Therefore, the voltage regulator aims to follow the reference voltage provided at input VSD_REF directly. If tracking of the memory card supply is not desired, connect pin VSD_REF to ground so the voltage regulator refers to an integrated voltage reference. For 1.8 V (SEL = HIGH) signaling, the voltage regulator is referred to the internal reference which is independent of the voltage at VSD_REF. 9.5. Feedback clock channel The clock is transmitted from the host to the memory card side. The voltage translator and the Printed-Circuit Board (PCB) tracks introduce some amount of delay. It reduces timing margin for data read back from memory card, especially at higher data rates. Therefore, a feedback path is provided to compensate the delay. The reasoning behind this approach is the fact that the clock is always delivered by the host, while the data in the timing critical read mode comes from the card. 9.6. EMI filter All input/output driver stages are equipped with EMI filters to reduce interferences towards sensitive mobile communication. 9.7. ESD protection The device has robust ESD protections on all memory card pins as well as on the VSD_REF and VSUPPLY pins. The architecture prevents any stress for the host: the voltage translator discharges any stress to supply ground. Pins Write Protect (WP) and Card Detection (CD) might be pulled down by the memory card which has to be detected by the host. Both signals must be HIGH if no card is inserted. Therefore the pins are equipped with International Electrotechnical Commission (IEC) system-level ESD protections and pull-up resistors connected to the host supply VCCA. IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 8 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 10. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage 4 ms transient; on pin VSUPPLY -0.5 4.6 V 4 ms transient; on pin VCCA -0.5 4.6 V VI input voltage 4 ms transient at I/O pins -0.5 4.6 V Ptot total power dissipation Tamb = -40 °C to 85 °C - 1000 mW Tstg storage temperature -55 150 °C Tamb ambient temperature -40 85 °C VESD electrostatic discharge voltage IEC 61000-4-2, level 4; all memory card-side pins, [1] -8 VSUPPLY, VSD_REF, WP and CD to ground; contact discharge 8 kV IEC 61000-4-2, level 4; all memory card-side [1] -15 pins, VSUPPLY, VSD_REF, WP and CD to ground; air discharge 15 kV JESD78B: -0.5 x VCC < VI < 1.5 x VCC; Tj < 125 °C 100 mA Ilu(IO) [1] input/output latch-up current -100 All system level test are performed with the application-specific capacitors connected to the supply pins VSUPPLY, VLDO and VCCA. IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 9 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 11. Recommended operating conditions Table 9. Operating conditions Symbol Parameter Conditions VCC on pin VSUPPLY supply voltage Typ Max Unit [1] 2.8 - 3.6 V 1.7 - VSUPPLY V [2] -0.3 - VCCA + 0.3 V memory card side -0.3 - VO(reg) + 0.3 V recommended capacitor at pin VLDO - 1.0 - µF recommended capacitor at pin VSUPPLY - 0.1 - µF recommended capacitor at pin VCCA - 0.1 - µF at pin VLDO 0 - 50 mΩ on pin VCCA VI input voltage Cext external capacitance ESR [1] [2] host side equivalent series resistance Min By minimum value the device is still fully functional, but the voltage on pin VLDO might drop below the recommended memory card supply voltage. The voltage must not exceed 3.6 V. Table 10. Integrated resistors Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Rpd pull-down resistance R7 272 470 668 kΩ R30 70 100 130 Ω R20; R21; R38 200 350 500 kΩ R10 10.5 15 19.5 kΩ R11 to R13 49 70 91 kΩ R14 and R15 70 100 130 kΩ Rpu pull-up resistance Rs [1] series resistance card side; R1 to R6 [1] 12 15 18 Ω host side; R31 to R37 [1] 18 22.5 27 Ω Guaranteed by design and characterization IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 10 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 12. Static characteristics Table 11. Static characteristics At recommended operating conditions; Tamb = -40 °C to 85 °C; voltages are referenced to GND (ground = 0 V); Cext = 1 µF at pin VLDO; unless otherwise specified. Symbol Parameter Conditions Min Typ [1] Max Unit SEL = LOW; VSD_REF < 1 V; VSUPPLY ≥ 2.9 V 2.7 2.9 3.3 V SEL = LOW; VSD_REF < 1.5 V; VSUPPLY ≥ VSD_REF VSD_REF 0.15 VSD_REF VSD_REF + 0.15 V SEL = HIGH; VSUPPLY ≥ 2.5 V 1.7 1.85 2.0 V SEL = LOW; VSUPPLY ≥ 2.9 V; IO = 50 mA - - 150 mV - - 100 mA Supply voltage regulator for card-side I/O pin: VLDO VO(reg) regulator output voltage Vdo(reg) regulator dropout voltage IO(reg) regulator output current Host-side input signals: CMD_H, DATA0_H to DATA3_H and CLK_IN VIH HIGH-level input voltage 0.625 x VCCA - VCCA + 0.3 V VIL LOW-level input voltage -0.3 - 0.35 x VCCA V ILI input leakage current - 1.0 nA VCCA = 1.8 V; ENABLE = LOW [2] - Host-side control signals VIH HIGH-level input voltage - VCCA + 0.3 V LOW-level input voltage SEL, ENABLE, DIR_0, DIR_1_3 and DIR_CMD 0.625 x VCCA VIL -0.3 - 0.35 x VCCA V VIH HIGH-level input voltage VSD_REF 1.5 - 3.63 V VIL LOW-level input voltage -0.3 - 1.0 V Host-side output signals: CLK_FB, CMD_H and DATA0_H to DATA3_H VOH HIGH-level output voltage IO = 2 mA; VI = VIH (card side) 0.85 x VCCA - - V VOL LOW-level output voltage - - 0.125 x VCCA V IO = -2 mA; VI = VIL (card side) Card-side input signals: CMD_SD and DATA0_SD to DATA3_SD VIH VIL SEL = LOW (2.9 V interface) 0.625 x VO(reg) - VO(reg) + 0.3 V SEL = HIGH (1.8 V interface) 0.625 x VO(reg) - VO(reg) + 0.3 V SEL = LOW (2.9 V interface) -0.3 - 0.35 x VO(reg) V SEL = HIGH (1.8 V interface) -0.3 - 0.35 x VO(reg) V HIGH-level output voltage IO = 4 mA; VI = VIH (host side); SEL = LOW (2.9 V interface) 0.85 x VO(reg) - VO(reg) + 0.3 V IO = 2 mA; VI = VIH (host side); SEL = HIGH (1.8 V interface) 0.85 x VO(reg) - 2.0 V IO = -4 mA; VI = VIL (host side); SEL = LOW (2.9 V interface) -0.3 - 0.125 x VO(reg) V IO = -2 mA; VI = VIL (host side); SEL = HIGH (1.8 V interface) -0.3 - 0.125 x VO(reg) V HIGH-level input voltage LOW-level input voltage Card-side output signal CMD_SD, DATA0_SD to DATA3_SD and CLK_SD VOH VOL Low-level output voltage Bus signal equivalent capacitance Cch channel capacitance IP4856CX25_C Product data sheet VI = 0 V; fi = 1 MHz; VSUPPLY = 3.5 V; VCCA = 1.8 V; host side [3] - 3.5 5 pF VI = 0 V; fi = 1 MHz; VSUPPLY = 3.5 V; VCCA = 1.8 V; card side [3] - 5 10 pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 11 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection Symbol Parameter Conditions Min Typ [1] Max Unit ENABLE = HIGH (active mode); all inputs = HIGH; DIR = LOW; SEL = LOW (2.9 V interface) - - 100 µA ENABLE = HIGH (active mode); all inputs = HIGH; DIR = LOW; SEL = HIGH (1.8 V interface) - - 100 µA ENABLE = LOW (inactive mode) - - 1 µA Current consumption ICC(stat) ICC(stb) [1] [2] [3] static supply current standby supply current Typical values are measured at Tamb = 25 °C. Guaranteed by design and characterization. EMI filter line capacitance per data channel from I/O driver to pin; Cch is guaranteed by design. 13. Dynamic characteristics 13.1. Voltage regulator Table 12. Voltage regulator Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tstartup(reg) regulator start-up time VCCA = 1.8 V; VSUPPLY = 3.5 V; Cext = 1 µF; Fig. 6 - - 100 µs tf(o) output fall time VO(reg) = 2.9 V to 1.8 V; SEL = LOW to HIGH; Fig. 5 - - 1 ms tr(o) output rise time VO(reg) = 1.8 V to 2.9 V; SEL = HIGH to LOW; Fig. 5 - - 100 µs Voltage regulator output pin: VLDO 2.9 V 2.9 V CLK_SD 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 0V 5 ms (min.) 2.9 V 2.9 V CMD 0V 2.9 V 2.9 V DATA[3:0] 0V SEL 0V 50 % tf(o) 2.9 V VLDO 1.8 V Fig. 5. 50 % 0V tr(o) 1.8 V 150 mV 1.8 V 2.9 V 97 % aaa-004566 Regulator mode change timing IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 12 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection VI 50 % ENABLE GND tstartup(reg) VO(reg) 97 % regulator output 0V 001aah981 Measuring points: ENABLE signal at 0.5 VCCA and regulator output signal at 0.97 VO(reg). Fig. 6. Regulator start-up time 13.2. Level translator Table 13. Level translator dynamic characteristics At recommended operating conditions; VCCA = 1.8 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Host-side transition times tr rise time SEL = HIGH (1.8 V interface) [1] - 0.4 1.0 ns tf fall time SEL = HIGH (1.8 V interface) [1] - 0.4 1.0 ns Card-side transition times tr rise time SEL = HIGH (1.8 V interface) [2] 0.4 0.9 1.4 ns tf fall time SEL = HIGH (1.8 V interface) [2] 0.4 0.9 1.4 ns - 2.4 3.5 ns - 4.8 7.0 ns - 2.4 3.5 ns Host-side to card-side propagation delay DATAx_H to DATAx_SD, CMD_H to CMD_SD and CLK_IN to CLK_SD tpd propagation delay SEL = HIGH (1.8 V interface) Host-side to host-side propagation delay CLK_IN to CLK_FB tpd propagation delay SEL = HIGH (1.8 V interface) Card-side to host-side propagation delay DATAx_SD to DATAx_H and CMD_SD to CMD_H tpd [1] [2] propagation delay SEL = HIGH (1.8 V interface) Transition between VOL = 0.35 x VCCA and VOH = 0.65 x VCCA. Transition between VOL = 0.45 V and VOH = 1.4 V. VCC 20 % tt 70 % VIH VIL GND 10 % Fig. 7. tt 90 % aaa-004569 Output rise and fall times IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 13 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection VCC VIH VIH CLK_IN VIL VIL GND output delay time VCC VOH DATA[3:0]_SD VOH GND Fig. 8. aaa-012908 Output delay timing 13.3. ESD characteristics of pin write protect and card detect Table 14. ESD characteristics of pin write protect and card detect At recommended operating conditions; VCCA = 1.8 V; Tamb = 25 °C; unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit - 8 - V ESD protection pins: WP and CD VBR breakdown voltage TLP; I = 1 mA rdyn dynamic resistance positive transient [1] - 0.5 - Ω negative transient [1] - 0.5 - Ω [1] IP4856CX25_C Product data sheet TLP according to ANSI/ESD STM5.5.1/IEC 62615 Zo = 50 Ω; pulse with = 100 ns; rise time = 200 ps: averaging window = 50 ns to 80 ns. All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 14 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 14. Test information pulse width VI 70 % negative input 50 % 0V VI tf(o) tr(o) tr(o) tf(o) 70 % positive input 0V 50 % 20 % 50 % 50 % 20 % pulse width VSUPPLY VCC PULSE GENERATOR Rsource VI DUT 50 Ω VO Rterm CL RL aaa-004707 Definitions test circuit: Rsource = source resistance of pulse generator. Rterm = termination resistance should be equal to output impedance Zo of pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. Fig. 9. Load circuitry for measuring switching time IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 15 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 15. Package outline WLCSP25: wafer level chip-size package with back side coating; 25 bumps (5 x 5) D A2 bump A1 index area E A A1 detail X e1 e b E e D e1 C B A European projection 1 2 3 4 5 X wlcsp25_5x5_c_po Fig. 10. Package outline IP4856CX25/C (WLCSP25 with back side coating) Table 15. Dimensions for Figure 9 Symbol Min Typ Max Unit A 0.47 0.51 0.55 mm A1 0.18 0.20 0.22 mm A2 0.03 0.04 0.05 mm b 0.23 0.25 0.27 mm D 2.01 2.05 2.09 mm E 2.01 2.05 2.09 mm e - 0.4 - mm e1 - 1.6 - mm IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 16 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 16. Design and assembly recommendations 16.1. PCB design guidelines For optimum performance, use a Non-Solder Mask PCB Design (NSMD), also known as a copperdefinied design, incorporating laser-drilled micro-vias connecting the ground pads to a buried ground-plane layer. This results in the lowest possible ground inductance and provides the best high frequency and ESD performance. For this case, refer to Table 16 for the recommended PCB design parameters. Table 16. Recommended PCB design parameters Parameter Value or specification PCB pad diameter 250 µm Micro-via diameter 100 µm (0.004 inch) Solder mask aperture diameter 325 µm Copper thickness 20 µm to 40 µm Copper finish AuNi or OSP PCB material FR4 16.2. PCB assembly guidelines for Pb-free soldering Table 17. Assembly recommendations Parameter Value or specification Solder screen aperture diameter 290 µm Solder screen thickness 100 µm (0.004 inch) Solder paste: Pb-free SnAg (3 % to 4 % Cu (0.5 % to 0.9 %) Solder to flux ratio 50 : 50 Solder reflow profile see Fig. 11 T (°C) Treflow(peak) 250 230 cooling rate 217 preheat t1 t5 t (s) t2 t3 t4 001aai943 The device can withstand at least three reflows with this profile. Fig. 11. Pb-free solder reflow profile IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 17 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection Table 18. Reflow soldering process characteristics Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions treflow(peak) peak reflow temperature Min Typ Max Unit 230 - 260 °C t1 time 1 soak time 60 - 180 s t2 time 2 time during T ≥ 250 °C - - 30 s t3 time 3 time during T ≥ 230 °C 10 - 50 s t4 time 4 time during T ≥ 217 °C 30 - 150 s t5 time 5 dT/dt rate of change of temperature - - 540 s cooling rate - - -6 °C/s preheat 2.5 - 4.0 °C/s 17. Abbreviations Table 19. Abbreviations Acronym Description IP4856CX25_C Product data sheet DUT Device Under Test EMI ElectroMagnetic Interface ESD ElectroStatic Discharge FR4 Flame Retard 4 MMC MultiMedia Card NSMD Non-Solder Mask PCB Design OSP Organic Solderability Preservation PCB Printed-Circuit Board RoHS Restriction of Hazardous Substances SD Secure Digital WLCSP Wafer-Level Chip-Scale Package All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 18 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 18. Revision history Table 20. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes IP4856CX25_C v.3 20191213 Product data sheet - Modifications: • • • IP4856CX25_C v.2 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Added figure "Marking description" IP4856CX25_C v.2 20141015 Product data sheet - IP4856CX25 v.1 IP4856CX25 v.1 20140602 Preliminary data sheet - - IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 19 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection 19. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal IP4856CX25_C Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 20 / 21 IP4856CX25/C Nexperia SD 3.0-compliant memory card integrated dual level translator with EMI filter and ESD protection Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Marking.......................................................................... 2 6. Block diagram...............................................................3 7. Functional diagram.......................................................4 8. Pinning information......................................................5 8.1. Pinning.........................................................................5 8.2. Pin description............................................................. 5 9. Functional description................................................. 6 9.1. Level translator............................................................ 6 9.2. Enable and direction control........................................ 7 9.3. Integrated voltage regulator.........................................8 9.4. Memory card voltage tracking (reference select)......... 8 9.5. Feedback clock channel.............................................. 8 9.6. EMI filter...................................................................... 8 9.7. ESD protection............................................................ 8 10. Limiting values........................................................... 9 11. Recommended operating conditions...................... 10 12. Static characteristics................................................11 13. Dynamic characteristics.......................................... 12 13.1. Voltage regulator..................................................... 12 13.2. Level translator........................................................ 13 13.3. ESD characteristics of pin write protect and card detect.................................................................................. 14 14. Test information........................................................15 15. Package outline........................................................ 16 16. Design and assembly recommendations............... 17 16.1. PCB design guidelines............................................ 17 16.2. PCB assembly guidelines for Pb-free soldering....... 17 17. Abbreviations............................................................ 18 18. Revision history........................................................19 19. Legal information......................................................20 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 13 December 2019 IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 13 December 2019 © Nexperia B.V. 2019. All rights reserved 21 / 21