PSMN1R0-25YLDX

PSMN1R0-25YLD N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 23 June 2020 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising Nexperia’s unique “SchottkyPlus” technology delivers high efficiency, low spiking performance usually associated with MOSFETS with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits • • • • • • • • • Avalanche rated, 100% tested at IAS = 190 A Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching frequencies Superfast switching with soft-recovery Low spiking and ringing for low EMI designs Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at 25 °C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package; no glue, no wire bonds, qualified to 175 °C Wave solderable; exposed leads for optimal visual solder inspection 3. Applications • • • • • • • On-board DC:DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control Power OR-ing 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 25 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 240 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 160 W Tj junction temperature -55 - 175 °C - 0.89 1 mΩ [1] Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.19 1.43 mΩ Dynamic characteristics QGD gate-drain charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 8 - nC QG(tot) total gate charge ID = 25 A; VDS = 12 V; VGS = 10 V; Fig. 12; Fig. 13 - 71.8 - nC - - 1762 mJ - 36.7 - nC Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy ID = 25 A; Vsup ≤ 25 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 4.34 ms [2] [3] Source-drain diode Qr [1] [2] [3] [4] recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; [4] VDS = 12 V; Fig. 16 240A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB thermal design and operating temperature. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. includes capacitive recovery 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN1R0-25YLD Name Description Version LFPAK56; Power-SO8 plastic, single-ended surface-mounted package; 4 terminals SOT669 7. Marking Table 4. Marking codes Type number Marking code PSMN1R0-25YLD 1D025L PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 2 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 25 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 160 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 240 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 216 A tp ≤ 10 µs; Fig. 3 - 1226 A [1] IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage HBM 1700 - V Source-drain diode IS source current Tmb = 25 °C - 133 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1226 A Avalanche ruggedness EDS(AL)S non-repetitive drainID = 25 A; Vsup ≤ 25 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 4.34 ms [2] [3] - 1762 mJ IAS non-repetitive avalanche Vsup = 25 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω [4] - 190 A [1] [2] [3] [4] 240A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB thermal design and operating temperature. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. Protected by 100% test. PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 3 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 03na19 120 Pder (%) aaa-022183 400 ID (A) 300 80 (1) 200 40 100 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 25 50 75 100 125 150 175 Tmb (°C) 200 VGS ≥ 10 V (1) 240A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Normalized total power dissipation as a function of mounting base temperature Fig. 2. ID (A) 0 Continuous drain current as a function of mounting base temperature aaa-022213 104 Limit RDSon = VDS / ID 103 tp = 10 us 102 100 us DC 10 1 ms 10 ms 100 ms 1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 4 junction to mounting base - 0.68 0.94 K/W Rth(j-a) thermal resistance from Fig. 5 junction to ambient Fig. 6 - 50 - K/W - 125 - K/W PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 4 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 1 Zth(j-mb) (K/W) aaa-022204 δ = 0.5 0.2 10-1 0.1 0.05 0.02 single shot P 10-2 δ= Fig. 4. 10-5 10-4 10-3 10-2 T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration aaa-005751 aaa-005750 Fig. 5. T t tp 10-3 10-6 tp PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper Fig. 6. PCB layout for thermal resistance junction to ambient minimum footprint; FR4 Board; 2oz copper 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 25 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 22.5 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C 1.2 1.75 2.2 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 175 °C - -5 - mV/K IDSS drain leakage current VDS = 20 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 20 V; VGS = 0 V; Tj = 125 °C - 29.7 - µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA IGSS gate leakage current PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 5 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 0.89 1 mΩ VGS = 10 V; ID = 25 A; Tj = 175 °C; Fig. 10; Fig. 11 - - 1.7 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.19 1.43 mΩ VGS = 4.5 V; ID = 25 A; Tj = 175 °C; Fig. 10; Fig. 11 - - 2.43 mΩ f = 1 MHz - 1.14 - Ω ID = 25 A; VDS = 12 V; VGS = 10 V; Fig. 12; Fig. 13 - 71.8 - nC ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 33.2 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 39.7 - nC ID = 25 A; VDS = 12 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 12.9 - nC - 7.8 - nC RG gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gatesource charge QGS(th-pl) post-threshold gatesource charge - 5.1 - nC QGD gate-drain charge - 8 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 12 V; Fig. 12; Fig. 13 - 2.7 - V Ciss input capacitance 5308 - pF output capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 14 - Coss - 1979 - pF Crss reverse transfer capacitance - 342 - pF td(on) turn-on delay time - 30.3 - ns tr rise time - 36 - ns td(off) turn-off delay time - 34 - ns tf fall time - 24.5 - ns Qoss output charge VGS = 0 V; VDS = 12 V; f = 1 MHz; Tj = 25 °C - 36.4 - nC VDS = 12 V; RL = 0.6 Ω; VGS = 4.5 V; RG(ext) = 5 Ω Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.79 1.2 V trr reverse recovery time - 36.9 - ns Qr recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 12 V; Fig. 16 [1] - 36.7 - nC ta reverse recovery rise time - 19.2 - ns tb reverse recovery fall time - 17.7 - ns S softness factor - 0.9 - [1] includes capacitive recovery PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 6 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology ID (A) aaa-022205 80 3.5 V 4.5 V 10 V 64 2.8 V 16 48 12 32 8 2.6 V 16 0 Fig. 7. aaa-022206 20 RDSon (mΩ) VGS =3 V 4 0 0.5 1 1.5 2 VDS (V) 0 2.5 0 2 4 6 8 10 12 14 VGS (V) 16 Tj = 25 °C Tj = 25 °C; ID = 25A Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values Drain-source on-state resistance as a function of gate-source voltage; typical values aaa-022297 200 ID (A) aaa-022207 25 RDSon (mΩ) 2.8 V 20 150 15 100 10 50 175°C 0 0 0.5 1 1.5 2 2.5 3 3.5 VGS (V) 0 4 Product data sheet 0 16 32 48 64 ID (A) 80 Tj = 25 °C Transfer characteristics; drain current as a function of gate-source voltage; typical values PSMN1R0-25YLD 3V 4.5 V 3.5 V VDS = 12 V Fig. 9. VGS = 10 V 5 Tj = 25°C Fig. 10. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 7 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology a aaa-021697 2 VGS (V) 10 V 1.6 1.2 aaa-022208 10 8 6 VGS = 4.5 V 20 V 0.8 12 V 4 VDS = 5 V 0.4 2 0 -60 -30 0 30 60 90 120 150 Tj (°C) 0 180 0 10 20 30 40 50 60 70 QG (nC) 80 Tj = 25 °C; ID = 25 A Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature Fig. 12. Gate-source voltage as a function of gate charge; typical values aaa-022209 104 VDS C (pF) ID Ciss Coss 103 VGS(pl) Crss VGS(th) VGS QGS2 QGS1 QGS 102 QGD QG(tot) 003aaa508 10 10-1 Fig. 13. Gate charge waveform definitions 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 8 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology IS (A) 003aal160 aaa-022210 103 ID (A) 102 trr ta tb 0 10 0.25 IRM 1 175°C 10-1 0 0.2 Tj = 25°C 0.4 0.6 0.8 IRM 1 VSD (V) t (s) 1.2 VGS = 0 V Fig. 16. Reverse recovery timing definition Fig. 15. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 9 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) mm A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 10 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 12. Soldering Footprint information for reflow soldering SOT669 4.7 4.2 0.9 (3×) 0.25 (2×) 0.25 (2×) 0.6 (4×) 3.45 0.6 (3×) 2 3.5 2.55 0.25 (2×) SR opening = Cu + 0.075 1.1 2.15 3.3 SP opening = Cu - 0.050 0.7 (4×) 1.27 3.81 solder lands solder paste 125 µm stencil solder resist occupied area Dimensions in mm sot669_fr Fig. 18. Reflow soldering footprint for LFPAK56; Power-SO8 (SOT669) PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 11 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Wave soldering footprint information for LFPAK56 package SOT669 4.826 1.78 1.72 2.1 1.4 0.6 (x4) 1.27 0.635 solder lands Dimensions in mm Issue date 15-04-13 15-04-16 sot669_fw Fig. 19. Wave soldering footprint for LFPAK56; Power-SO8 (SOT669) PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 12 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal PSMN1R0-25YLD Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 13 / 14 PSMN1R0-25YLD Nexperia N-channel 25 V, 1.0 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 3 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline........................................................ 10 12. Soldering................................................................... 11 13. Legal information......................................................13 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 23 June 2020 PSMN1R0-25YLD Product data sheet All information provided in this document is subject to legal disclaimers. 23 June 2020 © Nexperia B.V. 2020. All rights reserved 14 / 14