AW87329 Datasheet
May 2017 V1.0
High Efficiency Low Noise Large Volume TLTR-AGC 3rd Generation
Smart K Audio Amplifier
FEATURES
DESCRIPTION
Triple-Level Triple-Rate AGC algorithm to
effectively eliminate noise, pure sound quality
Original high efficient, large drive 2times high
voltage DO- Chargepump, efficiency up to 90%
Highest voltage：8.5V
Hardware compatible with AW87319CSR
Low noise：
9 μV (Class AB RCV THD+N=0.4%)
16 μV (Class D RCV THD+N=0.02%)
38 μV (Speaker THD+N=0.02%)
Selectable speaker-guard power level：
0.5W~1.5W@8ohm, 100mW/step
Output Power：3W@8Ω 3.5W@6Ω
Speaker & receiver 2-in-1 mode application
Shutdown current：0.1uA
Super TDD-Noise suppression
Excellent pop-click suppression
Support 1.8V logic I2C Control
High PSRR：-75dB（217Hz）
Small 2.58mm*2.11mm CSP-18 package
AW87329 is specifically designed to improve the
musical output dynamic range, enhance the overall sound
quality, which is a new high efficiency, low noise, constant
large volume, 3rd generation Smart K audio amplifiers.
AW87329 integrates Awinic’s proprietary Triple-Level
Triple-Rate AGC audio algorithm, effectively eliminating
music noise and improving sound quality and volume.
AW87329 integrated efficiency up to 90% of High voltage
DO-Chargepump technology, significantly improving the
dynamic range of the music output. AW87329 noise floor
is as low as to 38μV, with 102dB high signal-to-noise-ratio
(SNR). The ultra-low distortion 0.02% and unique
Triple-Level Triple-Rate AGC technology bring high
quality music enjoyment.
AW87329 supports speaker and receiver 2-in-1
applications, AB/D Receiver optional, ultra-low noise is
9uV.
AW87329 controls internal registers through the I 2C
interface. Register parameters include charge pump
output voltage, power amplifier gain, Triple-Level
Triple-Rate AGC parameters, etc.
APPLICATIONS
Smart phone、Tablet PC
AW87329 built-in over current protection, over
temperature protection and short circuit protection
function, effectively protect the chip. AW87329 features
small 2.58mm*2.11mm CSP-18 package.
APPLICATION DIAGRAM
VBAT
C3
10uF
10V
C2
0.1uF
10V
D3
GPIO
I2C Interface
D4
VDD
E3
{
E4
D2
I2C Address Select
Cin47nF
Cin+
47nF
E2
E1
C4
4.7uF
10V
B3
CP
RSTN
A4
CN
PVDD
SDA
C0
10uF
25V
SCL
AW87329
INN
VOP
INP
AD2
C3
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C1
10uF
25V
AD1
VON
Figure 1
A2,B2,C2
GND
BGND
D1
B4
PGND
B1
A1 B+
SPK
C+
0.1nF
16V
12V
C0.1nF
16V
12V
C1 B-
AW87329 Single-ended input mode Application Diagram
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1
AW87329 Datasheet
May 2017 V1.0
VBAT
C3
10uF
10V
C2
0.1uF
10V
I2C Interface
D4
VDD
D3
GPIO
E3
{
E4
D2
I2C Address Select
Cin47nF
E2
Speaker
Audio
DAC
Cin+
47nF
MUX
Receiver
C4
4.7uF
10V
E1
B3
CP
A4
CN
RSTN
PVDD
SDA
C0
10uF
25V
SCL
C1
10uF
25V
AD1
AW87329
INN
VOP
INP
BB
VON
AD2
C3
Figure 2
A2,B2,C2
GND
BGND
D1
B4
A1 B+
SPK
C+
0.1nF
16V
12V
C0.1nF
16V
12V
C1 B-
PGND
B1
AW87329 Speaker & Receiver 2-in-1 Mode Application Diagram
All trademarks are the property of their respective owners.
PIN CONFIGURATION ANG TOP MARK
AW87329 CSR MARKING
AW87329 CSR TOP VIEW
1
2
3
4
A
C
D
AWINIC
87329
XXXX
B
E
87329 – AW87329 CSR
XXXX – Production tracking code
Figure 3
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AW87329 pin diagram top view and device marking
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2
AW87329 Datasheet
May 2017 V1.0
PIN DESCRIPTION
Number
Symbol
Description
A1
VOP
A2,B2,C2
PVDD
A4
CN
B1
PGND
B3
CP
B4
BGND
C1
VON
Negative audio output terminal
C3
AD2
I2C address pin2
D1
GND
Ground
D2
AD1
I2C address pin1
D3
RSTN
D4
VDD
Power supply
E1
INP
Positive audio input terminal
E2
INN
Negative audio input terminal
E3
SDA
I2C-bus data input/output
E4
SCL
I2C-bus clock input
Positive audio output terminal
Charge Pump output voltage
Negative input Charge Pump Flying Capacitor
Amplifier power ground
Positive input Charge Pump Flying Capacitor
Charge Pump power ground
Reset pin, Low voltage effective, The 300KΩ pull-down resistor in chip
ORDERING INFORMATION
Product Type
Operation
temperature
range
AW87329CSR
-40°C～85°C
MSL type and
soldering
peak
temperature
Package
Device
Marking
Delivery Form
AW87329
Tape and Reel
6000 pcs
（Note1）
Level1, 260°C
CSP-18
AW87329
Shipment
R : Tape & Reel
Package type
CS : CSP18
Note1: MSL, Moisture Sensitivity Level
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3
AW87329 Datasheet
May 2017 V1.0
FUNCTIONAL DIAGRAM
CP
VDD
RSTN
RSTN
BIAS&OT
OVP
SYSCTRL
Current
Limit
CN
DO-Chargepump
SCL
SDA
AD1
AD2
2
IC
AD
OCP
OSC
AW87329
INP
INPUT
BUFFER
INN
VON
Voltage
Sensing
GND
Figure 4
VOP
Ultra Low
EMI
output
stage
Class-K
Modulator
Triple-LevelTriple-Rate
AGC
PVDD
BGND
PGND
AW87329 functional diagram
ABSOLUTE MAXIMUM RATING(Note1)
Parameter
Range
Supply Voltage VDD
INN,INP
-0.3V to 6V
-0.3V to VDD+0.3V
-0.3V to VDD+0.3V
Minimum load resistance RL
5Ω
Package Thermal Resistance θJA
60°C/W
Ambient Temperature Range
-40°C to 85°C
Maximum Junction Temperature TJMAX
165°C
Storage Temperature Range TSTG
-65°C to 150°C
Lead Temperature（Soldering 10 Seconds）
260°C
ESD Rating (Note 2)
HBM（human body model）
±2kV
MM（machine model）
±400V
CDM（charged-device model）
±2kV
Latch-up
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4
AW87329 Datasheet
May 2017 V1.0
Test Condition：JEDEC STANDARD NO.78B DECEMBER 2008
+IT：450mA
-IT：-450mA
Note 1：Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
Note 2：The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method:
MIL-STD-883G Method 3015.7
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AW87329 Datasheet
May 2017 V1.0
ELECTRICAL CHARACTERISTICS
Test condition：TA=25°C, VDD=3.6V, PVDD OVP=8V,
Parameter
VDD
UVLO
RL=8Ω+33μH, f=1kHz（unless otherwise noted）
Test conditions
Power supply voltage
Min
Typ
2.8
Max
Units
5.5
V
Under-voltage protection voltage
2.5
V
Under-voltage
hysteresis voltage
100
mV
protection
VIH
RSTN, SCL, SDA, AD1, AD2
high-level input voltage
1.3
VDD
V
VIL
RSTN, SCL, SDA, AD1, AD2
low-level input voltage
0
0.35
V
ISD
Shutdown current
1
μA
TTG
Thermal AGC start temperature
threshold
150
℃
TTGR
Thermal AGC exit temperature
threshold
130
℃
TSD
Over
temperature
threshold
protection
160
°C
TSDR
Over
temperature
recovery threshold
protection
130
°C
TON
Turn-On time
TOFF
Turn-Off time
VDD=3.6V, RSTN=0V
0.1
40
100
ms
400
μs
DO-Chargepump
PVDD
The maximum Output voltage
VDD=2.8V to 4V
OVP voltage
VDD >4V
OVP hysteresis voltage
VDD >4V
2*VDD
V
（ Note1）
V
8
OVP
FCP
Charge
frequency
ηCP
Charge pump efficiency
VDD=4.2V, Iload=200mA
TST
Softstart Time
Free load, COUT=4.7μF
ISHORT
pump
operating
50
VDD=2.8V to 5.5V
1.2
1.6
mV
2.0
90
Current limit when PVDD short to
ground
MHz
%
1
2
3
ms
200
300
400
mA
-30
0
30
mV
Class K MODE
VOS
Output offset voltage
No input
η
total efficiency（CP+Class D）
VDD=4.2V, Po=2.5W, RL=8Ω+33μH,
PVDD OVP=8.5V
80
%
Iq
Speaker
Quiescent
（overall）
VDD=3.6V, input ac grounded,
RL=8Ω+33μH
14
mA
Vinp
Recommended
amplitude
Fosc
Modulation frequency
current
input
signal
VDD=2.8V to 5.5V
VDD=2.8V to 5.5V
600
Pagc
TLTR AGC power
PSRR
Power supply rejection ratio
VDD=4.2V,
Vp-p_sin=200mV
Signal-to-noise ratio
VDD=4.2V, PVDD OVP=8.5V, Po=3W,
Av=8V/V , THD+N=1%,RL=8Ω+33μH,
SNR
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0.72
800
（ Note1）
0.8
1
Vp
1000
kHz
0.88
W
217Hz
-75
dB
1kHz
-72
dB
102
dB
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6
AW87329 Datasheet
May 2017 V1.0
Parameter
SNR
EN
Test conditions
Signal-to-noise ratio
Typ
VDD=4.2V, PVDD OVP=8.5V,
Po=0.8W, Av=8V/V, RL=8Ω+33μH
94
Av=16 V/V
48
Speaker Output noise
Av=8 V/V
Av
Min
20Hz to 20kHz, input
ac grounded,
A-weighting
dB
μV
24（Note1）
Speaker gain
VDD=2.8V to 5.5V
Speaker Inner input resistance
Av=16 V/V
9
Speaker Inner input resistance
Av=8 V/V
18
Speaker input Cut-off frequency
Cin=47nF, Av=16 V/V
376
Speaker input Cut-off frequency
Cin=47nF, Av=8 V/V
188
Speaker input Cut-off frequency
Cin=68nF, Av=16 V/V
260
Speaker input Cut-off frequency
Cin=68nF, Av=8 V/V
130
Fin
Po
Units
38
Rini
THD+N
Max
dB
kΩ
Hz
Total harmonic distortion + noise
VDD=4.2V, Po=0.6W,
RL=8Ω+33μH, f=1kHz, PVDD
OVP=8.5V
THD+N=1%, RL=8Ω+33μH, VDD=4.2V,
PVDD OVP=8.5V
0.02
%
3.01
W
THD+N=10%, RL=8Ω+33μH,
VDD=4.2V, PVDD OVP=8.5V
3.64
W
THD+N=1%, RL=6Ω+33μH, VDD=4.2V,
PVDD OVP=8.5V
3.51
W
THD+N=10%, RL=6Ω+33μH,
VDD=4.2V, PVDD OVP=8.5V
4.26
W
D Receiver quiescent current
（overall）
VDD=3.6V, input ac grounded,
RL=8Ω+33μH
5.8
mA
AB Receiver quiescent current
（overall）
VDD=3.6V, input ac grounded,
RL=8Ω+33μH
4.3
mA
D Receiver efficiency
VDD=4.2V,Po=0.8W, RL=8Ω+33μH
87
%
AB Receiver efficiency
VDD=4.2V,Po=0.8W, RL=8Ω+33μH
67
%
gain
VDD=2.8V to 5.5V
0（Note1）
dB
D Receiver Inner input resistance
Av=1 V/V
96
kΩ
AB
Receiver
resistance
Av=1 V/V
48
kΩ
Cin=47nF, Av=1 V/V
35
Hz
Cin=47nF, Av=1 V/V
70
Hz
D Receiver output noise
Av=1V/V
16
μV
AB Receiver output noise
Av=1V/V
9
μV
VDD=4.2V, Po=0.1W,RL=8Ω+33μH,
f=1kHz, D Receiver
0.02
%
VDD=4.2V, Po=0.1W,RL=8Ω+33μH,
f=1kHz, AB Receiver
0.4
%
Speaker Output Power
2-in-1 Receiver MODE
Iq
η
Av
Rini
Inner
input
D
Receiver
frequency
input
cut-off
AB
Receiver
frequency
input
cut-off
Fin
EN
THD+N
Total harmonic distortion + noise
D
Receiver
rejection ratio
Power
AB Receiver
rejection ratio
Power
supply
20Hz to 20kHz, input
ac grounded,
A-weighting
VDD=4.2V,
Vp-p_sin=200mV
217Hz
-78
dB
1kHz
-76
dB
VDD=4.2V,
Vp-p_sin=200mV
217Hz
-69
dB
1kHz
-68
dB
PSRR
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supply
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7
AW87329 Datasheet
May 2017 V1.0
Parameter
Test conditions
D Receiver Output Power
Po
AB Receiver Output Power
Min
Typ
Max
Units
THD+N=1%, RL=8Ω+33μH, VDD=4.2V
0.95
W
THD+N=10%, RL=8Ω+33μH,
VDD=4.2V
1.19
W
THD+N=1%, RL=8Ω+33μH, VDD=4.2V
0.875
W
THD+N=10%, RL=8Ω+33μH,
VDD=4.2V
1.15
W
Triple-Level Triple-Rate AGC
0.08
TAT1
AGC1 Attack Time
（ Note1）
TAT2
AGC2 Attack Time
（ Note1）
ms/dB
TAT3
AGC3 Attack Time
41（Note1）
ms/dB
（ Note1）
ms/dB
0.64
TRLT
Release time
21
AMAX
The maximum attenuation gain
-13.5
ms/dB
dB
Note 1：Registers are adjustable; Refer to the list of registers.
MEASUREMENT SETUP
AW87329 features switching digital output, as shown in Figure 5. Need to connect a low pass filter to
VOP/VON output respectively to filter out switch modulation frequency, then measure the differential
output of filter to obtain analog output signal.
10nF
500Ω
VOP
INP
Cin
30kHz
Low-Pass Fliter
AW87329
VON
INN
500Ω
Cin
10nF
Figure 5
AW87329 test setup
Low pass filter uses resistance and capacitor values listed in Table 1.
Rfilter
Cfilter
Low-pass cutoff frequency
500Ω
10nF
32kHz
1kΩ
4.7nF
34kHz
Table 1
AW87329 recommended values for low pass filter
Output Power Calculation
According to the above test methods, the differential analog output signal is obtained at the output of
the low pass filter. The valid values Vo_rms of the differential signal , as shown in Figure 6：
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AW87329 Datasheet
May 2017 V1.0
Vo_rms
Figure 6
Output RMS value
The power calculation of Speaker is as follows：
PL
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(VO_rms )2
RL
RL: load impedance of the speaker
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9
AW87329 Datasheet
May 2017 V1.0
TYPICAL CHARACTERISTICS
Class K Efficiency vs Po
100
90
90
80
80
70
70
Efficiency( % )
Efficiency( % )
Class K Efficiency vs Po
100
60
OVP=8.5V
VDD=4.2V
f=1kHz
50
40
30
60
OVP=8.5V
VDD=4.2V
f=1kHz
50
40
30
20
20
RL=8Ω+33μH
RL=6Ω+33μH
10
10
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.5
1
90
90
80
80
70
70
60
VDD=4.2V
f=1kHz
RL=8Ω+33μH
40
2.5
3
3.5
4
1.4
1.6
60
50
VDD=4.2V
f=1kHz
RL=6Ω+33μH
40
30
30
20
20
10
10
0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
1.6
0.2
0.4
Class AB Efficiency vs Po
0.8
1.0
1.2
Class AB Efficiency vs Po
100
90
90
80
80
70
70
Efficiency( % )
100
60
50
VDD=4.2V
f=1kHz
RL=8Ω+33μH
40
0.6
Po ( W )
Po ( W )
Efficiency( % )
2
Class D Efficiency vs Po
100
Efficiency( % )
Efficiency( % )
Class D Efficiency vs Po
100
50
1.5
Po ( W )
Po ( W )
60
50
VDD=4.2V
f=1kHz
RL=6Ω+33μH
40
30
30
20
20
10
10
0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
1.6
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0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Po ( W )
Po ( W )
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AW87329 Datasheet
May 2017 V1.0
Class K I_VDD_supply vs Po
Class K I_VDD_supply vs Po
2000
2000
1800
1800
OVP=8.5V
VDD=4.2V
f=1kHz
1600
I_VDD_supply (mA )
I_VDD_supply (mA )
1400
OVP=8.5V
VDD=4.2V
f=1kHz
1600
1200
1000
800
600
400
1400
1200
1000
800
600
400
RL=8Ω+33μH
200
RL=6Ω+33μH
200
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
Po ( W )
Class K Gain vs frequency
36
24
21
OVP=8V
VDD=3.6V
Cin=1μF
RL=8Ω+33μH
Gain=24dB
21
18
Gain=9dB
Gain=0dB
9
6
3
12
0
9
-3
6
-6
3
-9
0
-12
100
4
12
15
50
3.5
15
24
20
3
VDD=4.2V
Cin=1μF
RL=8Ω+33μH
18
Gain=18dB
Gain (dB )
Gain (dB )
27
2.5
Class D Gain vs frequency
33
30
2
Po ( W )
1K
10K
20
20K
50
100
1K
frequency ( Hz )
10K
20K
frequency ( Hz )
Po vs Vin
Class AB Gain vs frequency
2
24
21
Gain=9 dB
VDD=4.2V
Cin=1μF
RL=8Ω+33μH
18
Gain=0 dB
1
OVP=8V
VDD=4.2V
f=1kHz
RL=8Ω+33μH
12
Po (W)
Gain (dB )
15
9
6
0.5
0.291
1.352
AGC3 on
0.266
3
1.236
0.237
1.111
0
0.205
0.953
-3
-6
-9
0.1
0.1
-12
20
50
100
1K
10K
20K
frequency ( Hz )
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0.5
1
2
Vin ( Vp )
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AW87329 Datasheet
May 2017 V1.0
Class D THD+N vs frequency
Class D THD+N vs frequency
10
10
Receiver mode
VDD=4.2V
Cin=1μF
RL=8Ω+33μH
Gain=0dB
Po=100mW
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.001
20
Receiver mode
VDD=4.2V
Cin=1μF
RL=6Ω+33μH
Gain=0dB
Po=10mW
0.01
50
100
10K
1K
0.001
20
20K
50
100
THD+N (%)
THD+N (%)
Receiver mode
VDD=4.2V
Cin=1μF
RL=6Ω+33μH
Gain=0dB
1
0.1
0.1
0.01
0.01
Po=10mW
Po=10mW
Po=100mW
Po=100mW
50
100
10K
1K
0.001
20
20K
50
100
10K
1K
20K
frequency( Hz )
frequency( Hz )
Class K THD+N vs Po
Class K THD+N vs Po
100
100
OVP=8.5V
f=1kHz
RL=8Ω+33μH
OVP=8.5V
f=1kHz
RL=6Ω+33μH
10
THD+N (%)
10
THD+N (%)
20K
Class AB THD+N vs frequency
10
Receiver mode
VDD=4.2V
Cin=1μF
RL=8Ω+33μH
Gain=0dB
0.001
20
10K
1K
frequency ( Hz )
Class AB THD+N vs frequency
1
Po=100mW
0.1
frequency ( Hz )
10
Po=10mW
VDD=3.6V
VDD=4.2V
1
0.1
VDD=3.6V
VDD=4.2V
1
0.1
0.01
0.01
0.3
0.4
0.5
0.8
1
2
3
4
5
0.3
Po( W )
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0.4
0.5
0.8
1
2
3
4
5
6
Po( W )
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12
AW87329 Datasheet
May 2017 V1.0
Class K THD+N vs frequency
Class K THD+N vs frequency
10
10
VDD=4.2V
VDD=5.5V
1
THD+N (%)
THD+N (%)
1
Po=1W
OVP=8.5V
Cin=1μF
RL=6Ω+33μH
VDD=3.6V
Po=1W
OVP=8.5V
Cin=1μF
RL=8Ω+33μH
0.1
VDD=3.6V
VDD=4.2V
VDD=5.5V
0.1
0.01
0.01
0.001
20
50
100
10K
1K
0.001
20
20K
50
100
Class D PSRR vs frequency
Class K PSRR vs frequency
0
-10
-10
VDD=3.6V
OVP=8V
Cin=1μF
RL=8Ω+33μH
-20
VDD=4.2V
VDD=3.6V
Cin=1μF
RL=8Ω+33μH
-20
VDD=4.2V
VDD=5.5V
-30
PSRR (dB)
-30
PSRR (dB)
20K
frequency ( Hz )
0
-40
-50
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
20
100
1K
20
10K 20K
100
1K
10K 20K
frequency ( Hz )
frequency ( Hz )
Class D THD+N vs Po
Class AB PSRR vs frequency
100
0
-10
f=1kHz
RL=8Ω+33μH
VDD=3.6V
Cin=1μF
RL=8Ω+33μH
-20
VDD=4.2V
10
THD+N (%)
-30
PSRR (dB)
10K
1K
frequency ( Hz )
-40
VDD=3.6V
VDD=4.2V
1
-50
-60
0.1
-70
-80
0.01
0.07
-90
20
100
1K
10K 20K
frequency ( Hz )
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0.1
0.2
0.3
0.4 0.5
Po( W )
0.8
1
1.5
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AW87329 Datasheet
May 2017 V1.0
Class D THD+N vs Po
Start-up sequence
100
f=1kHz
RL=6Ω+33μH
SCL
THD+N (%)
10
VDD=3.6V
VDD=4.2V
SDA
1
0.1
VOP&VON
0.01
0.07
10ms/div
0.1
0.2
0.3
0.4
Po( W )
0.8
0.5
1
2
Shuntdown sequence
Triple-Level Triple-Rate AGC Attack Timing
SCL
Vin
SDA
VOP-VON
VOP&VON
50us/div
200ms/div
Triple-Level Triple-Rate AGC Release Timing
Vin
VOP-VON
100ms/div
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AW87329 Datasheet
May 2017 V1.0
WORKING PRINCIPLE
AW87329 is specifically designed to improve the musical output dynamic range, enhance the overall
sound quality, which is a new high efficiency, low noise, constant large volume, 3rd generation Smart K
audio amplifiers. AW87329 integrates Awinic’s proprietary Triple-Level Triple-Rate AGC audio algorithm,
effectively eliminating music noise and improving sound quality and volume. AW87329 integrated
efficiency up to 90% of High voltage DO-Chargepump technology, significantly improving the dynamic
range of the music output.AW87329 noise floor is as low as to 38μV, with 102dB high signal-to-noise-ratio
(SNR). The ultra-low distortion 0.02% and unique Triple-Level Triple-Rate AGC technology bring high
quality music enjoyment.
AW87329 supports speaker and receiver 2-in-1 applications, AB/D Receiver optional, ultra-low noise is
9uV.
AW87329 controls internal registers through the I2C interface. Register parameters include charge
pump output voltage, power amplifier gain, Triple-Level Triple-Rate AGC parameters etc.
AW87329 built-in over current protection, over temperature protection and short circuit protection
function, effectively protect the chip. AW87329 features small 2.58mm*2.11mm CSP-18 package.
CONSTANT OUTPUT POWER
In the mobile phone audio applications, the AGC function to promote music volume and quality is very
attractive, but as the lithium battery voltage drops, general power amplifier output power will reduce
gradually. So, it is hard to provide high quality music within the battery voltage range. AW87329 uses
unique Triple-Level Triple-Rate technology, within lithium battery voltage range (3.3V~4.35V), to
guarantee that output power is constant, and the output power will not drop along with the decrease of
lithium battery voltage. In the process of using the phone. Even if the battery voltage drops, AW87329 can
still provide high quality large volume music enjoyment. The output power of AW87329 can be configured
from 0.5W to 1.5W via I2C, matching general speakers. Unique Triple-Level Triple-Rate AGC technology
can bring high-quality music enjoyment.
Triple-Level Triple-Rate AGC technology
Awinic proprietary Triple-Level Triple-Rate AGC technology is designed for the protection of the high
voltage power amplifier, which is divided into AGC1, AGC2 and AGC3 power levels, to obtain a large
volume while maintaining excellent sound quality.
In practical applications, speaker can continuously work long hours at rated power, and also can work
short-term at high power. For example, in the standard reliability of the loudspeaker experiment, the
powder of peak power reached around four times of the rated power. For achieving larger volume and
better sound quality, speakers need to work at high power for short periods of time, in order to improve
the performance of the speaker. AW87329 Triple-Level Triple-Rate AGC technology can fit the speaker
better and perform better overall performance. AGC1 prevents output signal clipping by detecting output
voltage in a very short time after clipping, which can effectively restrain the noise clipping; AGC2 can
improve the dynamic range of the music in a relatively short period of time; AGC3 can make the speaker
work under rated power, which can effectively improve the volume and protect the speaker. Triple-Level
Triple-Rate AGC can obtain more excellent overall performance.
Triple-Level Triple-Rate AGC detects the peak output voltage of the power amplifier, when the output
peak voltage is higher than the compression threshold voltage, the amplifier gain decreases in 0.5dB step.
When the output peak voltage is lower than the release threshold voltage, the amplifier gain is recovery to
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AW87329 Datasheet
May 2017 V1.0
the initial gain in 0.5dB step. The detailed process can be described as follows:
Vin
AGC1 Compression threshold voltage
Vth_at1
Vth_at2
Vth_at3
Vth_rt
AGC2 Compression threshold voltage
AGC3 Compression threshold voltage
The release threshold voltage
Vout
Gain
A
B
C
AGC1
compression
AGC2
compression
Figure 7
D
E
AGC3 compression
F
hold
G
H
release
Triple-Level Triple-Rate AGC Operation Principle
A: Small input signal, the output voltage is lower than threshold voltage Vth of AGC, AGC don't work.
B: Input voltage becomes large. It leads to the output voltage clipping, AGC1 starts fast compression,
the attack time is set through the I2C register 0x0Ah [3:2], when the output voltage is higher than Vth_at1,
and gain register began to decrease. Gain decreases when the output signal passes through the zero. It
eliminates the clipping noise as soon as possible.
C: When the output voltage is not clipping and higher than threshold voltage Vth_at2, AGC2 starts work,
the attack time is set through the I2C register 0x09h [4:2], gain register begins to decrease at a certain
rate. Gain register began to decrease. Gain decreases when the output signal passes through the zero.
The output voltage gradually decreases to below the AGC2 attack threshold voltage Vth_at2, which can
protect the speaker and enhance the sound.
D: When the output voltage is lower than the AGC2 attack threshold voltage Vth_at2 and higher than
the AGC3 attack threshold voltage Vth_at3, AGC3 starts work, the attack time is set through the I2C
register 0x07h [4:2], and gain register began to decrease at a certain rate. Gain decreases when the
output signal passes through the zero, so the output voltage gradually decreases to below of the AGC3
attack threshold voltage Vth_at3, matching the speaker to achieve greater volume and better sound
quality.
E: Triple-Level Triple-Rate AGC attack time ends, Amplifier output power is close to the speaker rated
power.
F: Input voltage decreases, the output voltage becomes lower than the release threshold voltage Vth_rt,
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AW87329 Datasheet
May 2017 V1.0
at this point, gain remains the same in the maintain time (10ms~20ms).
G: Gain increases when the time of output voltage lower than the release threshold voltage Vth_rt is
longer than the holding time. The release time can be set through I2C register 0x07h [7:5].
H: Stop release when the output signal is larger than the release threshold or the gain is equal to the
initial value. The output voltage remains constant.
Triple-Level Triple-Rate AGC can switch independently according to different application requirements.
Such as close AGC1 and AGC2, retain only AGC3, this is the single-AGC mode, similar to AW8736
(AGC3 attack time is set to 1.28ms/dB; release time is set to 41ms/dB); Close AGC2, open AGC1 and
AGC3, this is Multi_level AGC. It can be set similar to AW8738 (AGC1 attack time is set to 80us/dB;
AGC3 attack time is set to 0.64ms/dB; release time is set to 10.24ms/dB).
Zero-Crossing Adjustment Technology
Traditional AGC doesn’t contain zero adjustment technology; AGC gain changes generally at the peak,
the gain variation at the peak would generate a certain transient distortion, such distortions are audibly
imperceptible. Such as individual songs have a slight click.
no zero-crossing adjustment
Figure 8
zero-crossing adjustment
Zero-adjust Comparison
As shown above, when there is no zero-adjustment technology, it can be seen the obvious step change
at the peak of large signal, the steps sound slightly perceived in special audio. Gain changes at zero. The
steps disappear by using zero-crossing detection technology. Using zero detection technology can make
the music pure and natural.
DO-Chargepump
AW87329 features DO-chargepump boost technology, with high efficiency and high drive capability,
operating frequency 1.6MHz, built-in soft start circuit, current limiting control loop and overvoltage control
loop to ensure circuit stable and reliable work.
High efficiency
AW87329 features DO-chargepump architecture, the boost output voltage PVDD is twice the input
voltage VDD, ideal efficiency up to 100%. The efficiency of the DO-chargepump is the ratio of the output
power to input power:
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AW87329 Datasheet
May 2017 V1.0
POUT
*100%
PIN
For example, in an ideal M times the DO-chargepump, the input current IIN is M times of IOUT, the
efficiency formula is:
POUT
V *I
V
*100% OUT OUT *100% OUT *100%
PIN
VIN * M * I OUT
M *VIN
Where M is the operating mode variable of the charge pump, VIN is the output voltage of charge pump,
IOUT is the load current. For the DO-chargepump, the output voltage is twice the input voltage, can
greatly improve the power efficiency, taking into account the charge pump internal switching losses and
IC quiescent current loss, the actual efficiency is as high as 90%.
AW87329 DO-chargepump can be set to pass-through mode and 2times chargepump mode via the
register 0x01h[2] to supply power to the Class D output stage.
Charge pump structure
The basic diagram of the charge pump shows in Figure 9, the charge-pump in AW87329 has four
switches, the output voltage PVDD can reach twice the input voltage through the four switches of the
timing control.
S1
VDD
+
CIN
10uF
CP
PVDD
COUT
10uF
CF
4.7uF
S2
S3
Figure 9
S4
Charge pump schematic diagram
The charge pump works with two phases, in Φ1, as shown in the Figure 10：S1, S2 on, VDD charges
the capacitor CF.
S1
VDD
+
CIN
10uF
CP
S4
PVDD
COUT
10uF
CF
4.7uF
S2
S3
Charge phase
Figure 10
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Φ1： Flying capacitor charging
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AW87329 Datasheet
May 2017 V1.0
In Φ2, as shown in the Figure 11：S1 and S2 off, S3 and S4 on, since the voltage across the capacitor
can not be mutated, the capacitors CF are superimposed on VDD, causing the PVDD to rise to a higher
voltage.
S1
VDD
+
CIN
10uF
CP
S4
PVDD
COUT
10uF
CF
4.7uF
S2
S3
Disharge phase
Figure 11
Φ2：Flying capacitor charge is transferred to COUT
Soft start
In order to limit the inrush current of the power supply during the start of the charge pump, the charge
pump has a soft function. The current limit is 300mA during start-up. Soft start time is 2ms.
Current limiting control
DO-chargepump architecture integrates the current limiting control loop, in normal operation, the
current limiting control loop controls the maximum output current capability of the charge pump when the
load is too heavy or the charge pump flows through a large current.
Overvoltage protection(OVP) control
The output voltage PVDD is twice the input voltage VDD in DO-chargepump structure, providing high
voltage rail for internal power amplifier circuits, allowing the amplifier in the lithium battery voltage range
to provide greater output dynamic range, in order to achieve high volume, high-quality class K audio
amplifier playback effect. DO-chargepump integrated over-voltage protection control loop, the input
voltage VDD is greater than 4V, the output voltage PVDD is not a multiple of VDD, but by the over-voltage
control loop is PVDD stable at 8.0V, the hysteresis voltage is about 50mV.
Speaker & Receiver 2-in-1 application
AW87329 built-in speaker and receiver two-in-one application mode, through the register settings,
there are class AB-type two-in-one receiver mode and class D-type two-in-one receiver mode can be
selected, the gain can be adjusted through the I2C register 0x05, adjustable range of 0~10.5dB, the
application is very flexible. The two-in-one receiver mode uses the signal path of the speaker, with
ultra-low distortion and strong drive capability, and eliminates the need for additional peripheral
components, saving system cost and PCB layout space.
In the typical application case of Figure 2, the input capacitance Cin = 47nF, the gain is 16V/V in the
speaker application mode, the input high-pass cutoff frequency is 376.5Hz; In 1V/V gain class D-type
two-in-one receiver application mode, The output noise is 16uV, the input high-pass cut-off frequency is
35Hz; In 1V/V gain class AB-type two-in-one receiver application mode, the output noise is as low as 9uV,
the input high-pass cut-off frequency is 70Hz, which is very suitable for high-definition voice applications.
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AW87329 Datasheet
May 2017 V1.0
AW87329 can achieve speaker and receiver's two-in-one application without changing any hardware in
the case.
High Power Receiver Stereo Applications
AW87329 built-in high-power receiver stereo application mode, makes full use of the receiver, not only
takes the voice calls into account and uses the receiver as speaker, but also combines the Awinic’s
propriety TLTR-AGC technology, significantly enhancing the stereo sound quality and volume, enhancing
the dynamic music, therefore, high power receiver stereo application has gradually become a mainstream
application in smart phone.
In the high-power receiver stereo application mode, when the register 0x02h [4] is set to 1, the use of
high-power receiver stereo mode. Gain adjustable range is 0~ 27dB by adjusting the I2C register 0x05h [4:
0], AGC3 power adjustable range is 0.1W~1.5W@8ohm receiver, 0.025W~0.375W@32ohm receiver
through adjusting the I2C register 0x06h [3:0]. AW87329 can flexibly match a variety of high-power
Receiver, combined with TLTR AGC technology, significantly enhance the stereo sound quality and
volume, and enhance music dynamic listening.
LINEOUT_L+
Audio
Source
EQ
PGA
LINEOUT_L-
AW87329
TLTR-AGC
BB or CODEC
High power
RCV
LINEOUT_R+
EQ
PGA
LINEOUT_R-
AW87329
CP & TLTR-AGC
SPK
Figure 12
AW87329 High Power Receiver Stereo Mode Application
RNS(RF TDD Noise Suppression)
TDD Noise Causes
GSM cell phones use TDMA (Time Division Multiple Access) slot sharing technology. The time is
divided into periodic frames in TDMA, and each frame is subdivided into a plurality of time slots. In order
to transmit signals to the base station, the signals sent from the base stations to the plurality of mobile
terminals are arranged in a predetermined time slot in the transmission. In this case, each TDMA frame
contains 8 time slots, the entire frame is about 4.615ms long, and each slot time is 0.577ms.
With GSM handset, the RF power amplifier will transmit once every 4.615ms (217Hz), and the signal
will produce intermittent Burst current and strong electromagnetic radiation. Intermittent Burst current will
form a power fluctuation of 217 Hz; High frequency (900MHz and 1800MHz) RF signals form a 217Hz RF
envelope signal. 217Hz power fluctuations will be conducted through the conduction to the audio signal
path, 217Hz RF envelope signal will be coupled through the radiation into the audio signal path, if the
protection is not good, it will produce an audible TDD Noise, which includes the 217Hz noise And a
harmonic noise signal of 217 Hz.
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AW87329 Datasheet
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VBAT
Voltage
4.615ms
RF
Signal
Figure 13
Schematic diagram of power supply voltage and RF signal during GSM RF operation
RNS fully inhibit the conduction and radiation interference by the AWINIC unique circuit architecture.
Effectively improve the ability to suppress TDD Noise.
Conduction noise suppression
When the RF power amplifier is operating, it will draw the current from the battery by 217Hz frequency,
Power supply will be introduced to 217Hz power ripple since the battery has a certain internal resistance,
it will be coupled to the speaker through the audio power amplifier. The ability to suppress power
fluctuations depends on the PSRR of the audio power amplifier.
PSRR 20 log(
vout ac
)
vdd ac
Due to the input and output of the fully differential amplifier is perfectly symmetrical, theoretically, the
effect of the power supply fluctuation on the two outputs is exactly the same, and the differential output is
completely unaffected by the power supply fluctuation. In practice, due to process bias and other factors,
the amplifier will have a certain mismatch, PSRR is generally better than -60dB, it shows the output
relative to the power fluctuations can be reduced by 1000 times, such as 500mVp power fluctuations, the
differential output of 0.5 MV, which basically can meet the application requirements.
But in practical applications, the power amplifier may encounter conduction of TDD Noise problem
even if its PSRR is -60dB or -80dB, why is this? Because we also need to consider the impact of
peripheral power mismatches of audio power amplifiers
For conventional audio power amplifiers, when the input resistor Rin and the input capacitor Cin
mismatch, will greatly affect the audio power amplifier PSRR indicators, in the case of 24 times the gain,
PSRR will be weakened to -46dB or so if the input resistance and Capacitor with 1% mismatch. PSRR will
be weakened to -28dB or so if the input resistance and input capacitance mismatch with 10% mismatch,
when the power fluctuations, it is easy to produce audible TDD Noise.
In order to enhance the audio power amplifier PSRR in the input resistance and input capacitance
mismatch case, AW87329 features a unique conduction noise suppression circuit, making the power
amplifier to maintain a high PSRR value even in the input resistance, the input capacitance deviation of
10% or more, This greatly inhibits the generation of conducted noise.
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AW87329 Datasheet
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Radiation noise suppression
Input traces, output traces, horn loops, and even power and ground loops are likely to be subject to RF
radiation interference in the audio signal module, longer input traces and output traces similar to the
antenna, especially vulnerable RF radiation effects.
The reasonable PCB layout can reduce the influence of RF radiation in the design, such as shorten the
line length of input and output as much as possible; audio devices should be shielded and far away from
the RF antenna, maintain the integrity of the device to audio signal pathway; to increase the small bypass
capacitor RF signals in the sensitive nodes. However, in practical applications, PCB layout is difficult to
fully consider the influence of RF radiation on the audio signal path, and some RF energy will still be
coupled to the audio signal path to form audible TDD Noise. Therefore, AW87329 features a unique RF
radiation suppression circuit, a shielding layer inside the chip, effectively prevent high frequency energy
into RF chip, to ensure that the drive single of the amplifier provided to the speaker will not be affected by
the antenna RF radiation, thus avoiding the antenna RF Radiation caused by TDD Noise.
VDD
Cin
INP
VOP
INN
AW87329VON
Rin
GND
Figure 14
RF radiation coupling graph
Class D amplifier without filter
When the traditional class D amplifier is in idle state of no input signal, the output will have the inverse
square wave, it will directly above the load of the speaker, will form a large current power switch on the
speaker, therefore we need to increase the LC filter to restore the analog audio signal at the amplifier
output. The LC filter increase the cost and PCB layout area, while increase the power consumption,
reduce the performance of THD+N.
The AW87329 features a Class D amplifier without a filter, eliminating the need for an output LC filter.
In the idle state of no input signal, the two outputs (VOP, VON) of the amplifier are in-phase square waves
and not generate idle switching currents on the speaker load. When the input signal is added to the input
terminal, the duty ratio of the output is changed. The duty cycle of the VOP becomes larger and the duty
cycle of the VON becomes smaller, and the difference value of the output forms the differential amplified
signal on the speaker.
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AW87329 Datasheet
May 2017 V1.0
EEE
The AW87329 features a unique Enhanced Emission Elimination (EEE) technology, that controls fast
transition on the output, greatly reduces EMI over the full bandwidth, fully meet FCC CLASS B
specification requirements.
Pop-Click Suppression
The AW87329 features unique timing control circuit, that comprehensively suppresses pop-click noise,
eliminates audible transients on shutdown, wakeup, and power-up/down.
Thermal AGC/ over temperature protection
The AW87329 features the thermal AGC patented technology, can according to the chip temperature,
automatically adjust the gain of the system, reduce the power consumption of the chip, to prevent
damage in case of excessive temperature.
The AW87329 has an automatic temperature detection mechanism, when the chip temperature
exceeds the preset threshold of thermal AGC temperature (150°C), the chip will start the automatic gain
control circuit to decrease the gain of the system, thereby reducing the energy consumption of the chip,
thus slow or stop chip temperature continues to rise. When the chip temperature is restored to normal
operating range (below 130°C), the automatic gain control circuit will restore the system gain to the
original state. When the chip operates in a fault condition, the chip temperature is too high, up to a preset
temperature protection temperature threshold (160°C), the system starts overheating protection, the chip
will be turned off, restarts to resume normal work when the chip temperature returns to normal operating
range (less than 130°C).
Automatic recovery of overcurrent protection
AW87329 with automatic recovery of the output overcurrent protection function, when the overcurrent
occurs, AW87329 internal protection circuit will chip off to ensure that the chip is not damaged, when the
short-circuit fault is eliminated, the chip will automatically resume working without restarting.
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I2C Timing feature
Parameter
MIN
TYP
MAX
UNIT
400
kHz
No.
Sym
Name
1
fSCL
SCL Clock frequency
2
tLOW
SCL Low level Duration
1.3
μs
3
tHIGH
SCL High level Duration
0.6
μs
4
tRISE
SCL, SDA rise time
0.3
μs
5
tFALL
SCL, SDA fall time
0.3
μs
6
tSU:STA
Setup time SCL to START state
0.6
μs
7
tHD:STA
(Repeat-start) Start condition hold time
0.6
μs
8
tSU:STO
Stop condition setup time
0.6
μs
9
tBUF
the Bus idle time START state to STOP state
1.3
μs
10
tSU:DAT
SDA setup time
0.1
μs
11
tHD:DAT
SDA hold time
10
ns
(3)
(2)
tHI GH
tLOW
tRI SE
tFALL
(4)
(5)
SCL
tSU:DAT
tHD:DAT
(10)
(11)
SDA
Figure 15
SCL and SDA timing relationships in the data transmission process
SCL
tHD:STA
tSU:STO
(7)
(8)
(6)
(9)
tSU:STA
tBUF
SDA
Figure 16
The timing relationship between START and STOP state
General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated
circuits in a system. The device is addressed by a unique 7-bit address; the same device can send and
receive data. In addition, Communications equipment has distinguish master from slave device: In the
communication process, only the master device can initiate a transfer and terminate data and generate a
corresponding clock signal. The devices using the address access during transmission can be seen as a
slave device.
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SDA and SCL connect to the power supply through the current source or pull-up resistor. SDA and SCL
default is a high level. All data to start transmission and end of transmission requires the main device to
issue START state and STOP status:
START state：The SCL maintain a high level, SDA from high to low level
STOP state：The SCL maintain a high level, SDA pulled low to high level
Start and Stop states can be only generated by the master device. In addition, if the device does not
produce STOP state after the data transmission is completed, instead re-generate a START state
(Repeated START, Sr), and it is believed that this bus is still in the process of data transmission.
Functionally, Sr state and START state is the same. As shown in Figure 17.
SCL
START
(S)
STOP
(P)
SDA
Figure 17
START and STOP state generation process
In the data transmission process, when the clock line SCL maintains a high level, the data line SDA
must remain the same. Only when the SCL maintain a low level, the data line SDA can be changed, as
shown in Figure 18. Each transmission of information on the SDA is 9 bits as a unit. The first eight bits are
the data to be transmitted, and the first one is the most significant bit (Most Significant Bit, MSB), the ninth
bit is an confirmation bit (Acknowledge, ACK or A ), as shown in Figure 19. When the SDA transmits a low
level in ninth clock pulse, it means the acknowledgment bit is 1, namely the current transmission of 8 bits
data are confirmed, otherwise it means that the data transmission has not been confirmed. Any amount of
data can be transferred between START and STOP state.
SCL
SDA
Data cable
Remains the same:
At this point the
data is valid
Figure 18
Data transmission:
In this case the data
is invalid
The data transfer rules on the I2C bus
The whole process of actual data transmission is shown in Figure 19. When generating a START
condition, the master device sends an 8-bit data, including a 7-bit slave addresses (Slave Address), and
followed by a "read / write" flag ( R/W ). The flag is used to specify the direction of transmission of
subsequent data. The master device will produce the STOP state to end the process after the data
transmission is completed. However, if the master device intends to continue data transmission, you can
directly send a Repeated START state, without the need to use the STOP state to end transmission.
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SCL
START or
repeated
START
(S or Sr)
1
2
8
9
1
R/W
ACK
MSB
2
8
9
STOP or
Repeated
START
(P or Sr)
SDA
MSB
Figure 19
ACK
Data transmission on the I2C bus
I2C Read/Write Processes
The following describes two kinds of ways of the I2C bus data transmission:
Write Process
Writing process refers to the master device write data into the slave device. In this process, the transfer
direction of the data is always unchanged from the master device to the slave device. All acknowledge
bits are transferred by the slave device, in particular, AW87329 as the slave device, the transmission
process in accordance with the following steps, as shown in Figure 20:
Master device generates START state. The START state is produced by pulling the data line SDA to a
low level when the clock SCL signal is a high level.
Master device transmits the 7-bits device address of the slave device, followed by the "read / write" flag
(flag R/W = 0);
The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is
correct;
The master device transmits the 8-bit AW87329 register address to which the first data byte will
written；
The slave device asserts an acknowledgment (ACK) bit to confirm the register address is correct;
Master sends 8 bits of data to register which needs to be written;
The slave device asserts an acknowledgment bit (ACK) to confirm whether the data is sent
successfully;
If the master device needs to continue transmitting data, it does not need further to send the register
address for AW87329, within AW87329 each send confirmation bit(ACK) regret automatic accumulation
register address then only need to repeat the sixth step and seven step:
The master device generates the STOP state to end the data transmission.
(1)
START
(2)
slave device address
R/W
(3)
(4)
A
Register address
‘0’(write)
data
transmission
direction
(5)
(6)
(7)
(6r)
(7r)
A write data A write data A
(9)
STOP
Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Register address auto increment - (8)
From the master to the slave device
From slave to master device
Figure 20
Writing process (data transmission direction remains the same)
Read Process
Reading process refers to the slave device reading data back to the master device. In this process, the
direction of data transmission will change. Before and after the change, the master device sends START
state and slave address twice, and sends the opposite "read/write" flag. In particular, AW87329 as the
slave device, the transmission process carried out by following steps listed in Figure 21:
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26
Master device asserts a start condition;
Master device transmits the 7 bits address of AW87329, and followed by a "read / write" flag ( R/W = 0);
The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is
correct;
The master device sends the 8bit address that the AW87329 register needs to read the data;
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is
correct or not;
The master device restarts the data transfer process by continuously generating STOP state and
START state or a separate Repeated START.
Master sends 7-bits address of the slave device and followed by a read / write flag (flag R/W = 1)
again.
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is
correct or not.
The master transmits 8 bits of data to register which needs to be read;
The slave device sends an acknowledgment bit (ACK) to confirm whether the data is sent successfully.
AW87329 automatically increment register address once after the slave sent each acknowledge bit
(ACK).
The master device generates the STOP state to end the data transmission.
(1)
(2)
(3)
(4)
(5)
(6)
START
slave device address R/W
A
Register address
A
Sr
(7)
‘0’(write)
data
transmission
direction
From the master to the slave device
From slave to master device
Figure 21
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(8)
slave device address
R/W
A
(9)
(10)
Read data A
(9r)
(10r)
Read data A
(12)
STOP
‘1’(read) Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Sr = repeated START
or Send STOP state before sending START state
Register address auto increment - (11)
Reading process (data transmission direction remains the same)
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Register List
name
addr
ess
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Chip ID
SYSCTRL
MODECTRL
CPOVP
CPP
0x00
0x01
0x02
0x03
0x04
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
Gain
0x05
0
0
0
AGC3_Po
AGC3
AGC2_Po
AGC2
AGC1
0x06
0x07
0x08
0x09
0x0A
0
AGC3_RT[2]
0
0
1
0
AGC3_RT[1]
0
0
0
0
AGC3_RT[0]
0
0
0
1
0
0
0
0
Class_D_Gain
[4]
0
AGC3_AT[2]
0
AGC2_AT[2]
1
1
EN_SW
RCV_MODE(2)
CP_OVP(4) [3]
0
Class_D_Gain
[3]
AGC3_Po[3]
AGC3_AT[1]
AGC2_Po[3]
AGC2_AT[1]
AGC1_AT[1]
0
EN_CP
EN_ABRCV(3)
CP_OVP(4) [2]
1
Class_D_Gain
[2]
AGC3_Po[2]
AGC3_AT[0]
AGC2_Po[2]
AGC2_AT[2]
AGC1_AT[0]
0
EN_PA
1
CP_OVP(4) [1]
0
Class_D_Gain
[1]
AGC3_Po[1]
1
AGC2_Po[1]
0
1
1
0
1
CP_OVP(4) [0]
1
Class_D_Gain
[0]
AGC3_Po[0]
0
AGC2_Po[0]
0
PD_AGC1
RCV_MODE: enable 2-in-1 receiver application
EN_ABRCV: enable 2-in-1 class AB receiver application
CP_OVP: chargepump OVP voltage
(1)
(2)
(3)
register
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x07
0x52
0x06
0x08
96
0x00 (RCV_MODE=1)
Default
0x39
0x06
0xA3
0x06
0x05
0x10 (RCV_MODE=0)
Table 2
AW87329 Register Default value
Any register address which is more than 0x0A and all reserved bits are reserved for debugging and
testing purposes. Changing values may affect the normal function of the power amplifier; Reading them
will get any possible values. AW87329’s I2C address is 10110A2A1, as shown in Table 3, in order to
avoid conflict with other I2C devices address, you can pull up or pull-down AW87329 of AD2 and AD1 pins
to set the value of A2 and A1, respectively. The following lists specific information about all visible
registers, including default values and programmable ranges.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
1
0
A2
A1
R/W
Table 3
AW87329 address byte
CHIP ID Register (address: 0x00)
2
I C Bit
Name
R/W
Default
7:0
IDCODE
R
0x39
Description
Chip ID will be returned after reading.
All configuration registers will be reset to default
values after 0xAA is written.
SYSTEM CONTROL (SYSCTRL) Register (address: 0x01)
I2C Bit
7:4
Name
--
R/W
--
Default
0000
3
EN_SW
R/W
0
2
EN_CP
R/W
1
1
EN_PA
R/W
1
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Description
Reserved and Unused
Chip Software Enable
0: Chip Software Disable:
Shutdown the whole chip except PORN.
1: Chip Software Enable
Charge Pump Enable:
This bit must be unchanged when EN_SW=1.
0: Disable Charge Pump, PVDD=VBAT
1: Enable Charge Pump
PA output Enable
0: Disable PA
1: Enable PA
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0
--
--
0
Reserved and Unused
MODE CONTROL (MODECTRL) Register (address: 0x02)
I2C Bit
7:4
Name
--
R/W
--
Default
1010
3
RCV_MODE
R/W
0
2
EN_ABRCV
R/W
0
1:0
--
--
11
Description
Reserved and Unused
Speak & Receiver 2-in-1 application
0: Speak & Receiver 2-in-1 application Disable
1: Speak & Receiver 2-in-1 application Enable
2-in-1 Class AB Receiver application
0: 2-in-1 Class D Receiver application Enable
1: 2-in-1 Class AB Receiver application Enable
Reserved and Unused
CHARGEPUMP OUTPUT VOLTAGE (CPOVP) Register (address: 0x03)
I2C Bit
7:4
Name
--
R/W
--
Default
0000
3:0
CP_OVP
R/W
0110
Description
Reserved and Unused
Setting Charge pump OVP Voltage
1001~1111: Unavailable
1000: 8.5V
0111: 8.25V
0110: 8.0V
0101: 7.75V
0100: 7.5V
0011: 7.25V
0010: 7.0V
0001: 6.75V
0000: 6.5V
CHAREPUMP PARAMETER (CPP) Register (address: 0x04)
I2C Bit
7:0
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Name
--
R/W
--
Default
00000101
Description
Reserved and Unused
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GAIN CONTROL (Gain) Register (address: 0x05)
For RCV_MODE=1 (Speaker & Receiver 2-in-1Mode):
I2C Bit
7:5
4:0
Name
--
R/W
--
Class_D_Gain
R/W
Default
000
0000
Description
Reserved and Unused
Setting Class D Amplifying Gain
Gain
EN_ABRCV=0
EN_ABRCV=1
00000: 0dB
00001: 1.5dB
00010: 3dB
00011: 4.5dB
00100: 6.0dB
00101: 7.5dB
00110: 9.0dB
00111: 10.5dB
Rini=96kΩ
Rini=80kΩ
Rini=68kΩ
Rini=56kΩ
Rini=48kΩ
Rini=60kΩ
Rini=48kΩ
Rini=56kΩ
Rini=48kΩ
Rini=48kΩ
Rini=48kΩ
Rini=48kΩ
Rini=48kΩ
Rini=48kΩ
Rini=48kΩ
Rini=48kΩ
For RCV_MODE=0 (Speaker Mode):
I2C Bit
7:5
Name
--
R/W
--
Default
000
Description
Reserved and Unused
Setting Class D Amplifying Gain
Gain
4:0
Class_D_Gain
R/W
10000
01000: 12dB
Rini=36.5kΩ
01001: 13.5dB
Rini=30kΩ
01010: 15.0dB
Rini=25kΩ
01011: 16.5dB
Rini=21.5kΩ
01100: 18.0dB
Rini=18kΩ
01101: 19.5dB
Rini=15.5kΩ
01110: 21dB
Rini=12.5kΩ
01111: 22.5dB
Rini=11kΩ
10000: 24dB
Rini=9kΩ
10001: 25.5dB
Rini=7.5kΩ
10010: 27dB
Rini=6.5kΩ
10011~11111: Unavailable
CLASS D AGC3 OUTPUT POWER (AGC3_Po) Register (address: 0x06)
I2C Bit
7:4
Name
--
R/W
--
Default
0000
3:0
AGC3_Po
R/W
0111
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Description
Reserved and Unused
Setting AGC3 Output Power for Protecting Speaker
and stereo Receiver
0000~0011: Unavailable
0100: 0.5W@8Ω
0.125W@32Ω
0101: 0.6W@8Ω
0.15W@32Ω
0110: 0.7W@8Ω
0.175W@32Ω
0111: 0.8W@8Ω
0.2W@32Ω
1000: 0.9W@8Ω
0.225W@32Ω
1001: 1.0W@8Ω
0.25W@32Ω
1010: 1.1W@8Ω
0.275W@32Ω
1011: 1.2W@8Ω
0.3W@32Ω
1100: 1.3W@8Ω
0.325W@32Ω
1101: 1.4W@8Ω
0.35W@32Ω
1110: 1.5W@8Ω
0.375W@32Ω
1111: AGC3 Disable
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CLASS D AGC3 PARAMETER (AGC3) Register (address: 0x07)
I2C Bit
Name
R/W
Default
7:5
AGC3_RT
R/W
010
4:2
AGC3_AT
R/W
100
1:0
--
--
10
Description
Setting Release Time of AGC3:
000: 5.12ms/dB
001: 10.24ms/dB
010: 21 ms/dB
011: 41 ms/dB
100: 82 ms/dB
101: 164 ms/dB
110: 328 ms/dB
111: Unavailable
Setting Attack Time of AGC3:
000: 0.64ms/dB
001: 1.28ms/dB
010: 2.56ms/dB
011: 10.24ms/dB
100: 41ms/dB
101: 82ms/dB
110: 164ms/dB
111: 328ms/dB
Reserved and Unused
CLASS D AGC2 OUTPUT POWER(AGC2_Po) Register (address: 0x08)
I2C Bit
7:4
Name
--
R/W
--
Default
0000
3:0
AGC2_Po
R/W
0110
Description
Reserved and Unused
Setting AGC2 Output Power:
0000: 0.4W@8Ω
0.1W@32Ω
0001: 0.6W@8Ω
0.15W@32Ω
0010: 0.8W@8Ω
0.2W@32Ω
0011: 1.0W@8Ω
0.25W@32Ω
0100: 1.2W@8Ω
0.3W@32Ω
0101: 1.4W@8Ω
0.35W@32Ω
0110: 1.6W@8Ω
0.4W@32Ω
0111: 1.8W@8Ω
0.45W@32Ω
1000: 2.0W@8Ω
0.5W@32Ω
1001: AGC2 Disable
1010~1111: Unavailable
CLASS D AGC2 PARAMETER (AGC2) Register (address: 0x09)
I2C Bit
7:5
Name
--
R/W
--
Default
00
4:2
AGC2_AT
R/W
010
1:0
--
--
00
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Description
Setting Attack Time of AGC2:
000: 0.16ms/dB
001: 0.32ms/ dB
010: 0.64ms/dB
011: 2.56ms/dB
100: 10.24ms/dB
101: 41ms/dB
110: 82ms/dB
111: 164ms/dB
Reserved and Unused
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CLASS D AGC1 PARAMETER (AGC1) Register (address: 0x0A)
I2C Bit
7:4
Name
--
R/W
--
Default
1001
3:2
AGC1_AT
R/W
01
1
--
--
1
0
PD_ AGC1
R/W
0
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Description
Reserved and Unused
Setting Fastest Level AGC Attack Time:
00: 0.04ms/dB
01: 0.08ms/dB
10: 0.16ms/dB
11: 0.32ms/dB
Reserved and Unused
AGC1 control bit
0: AGC1 Enable
1: AGC1 Disable
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APPLICATION INFORMATION
Capacitor Selection
The output capacitor of charge pump is usually within the range 0.1μF~47uF, It needs to use Class II
type (EIA) multilayer ceramic capacitors (MLCC). Its internal dielectric is ferroelectric material (typically
BaTiO3), a high the dielectric constant in order to achieve smaller size, but at the same Class II type (EIA)
multilayer ceramic capacitors has poor temperature stability and voltage stability as compared to the
Class I type (EIA) capacitance. Capacitor is selected based on the requirements of temperature stability
and voltage stability, considering the capacitance material, capacitor voltage, and capacitor size and
capacitance values.
a)
temperature stability
Class II capacitance have different temperature stability in different materials, usually choose X5R type
in order to ensure enough temperature stability, and X7R type capacitance has better properties, the
price is relatively more expensive. X5R capacitance change within ±15% in temperature range of 55°C to
85°C, X7R capacitance change within ±15% in temperature range of -55°C~125°C. The output
capacitance of the AW87329’s charge pump recommends X5R ceramic capacitors.
b)
Voltage Stability
Class II type capacitor has poor voltage stability ——Capacitance values falling fast along with the DC
bias voltage applied across the capacitor increasing. The rate of decline is related to capacitance material,
capacitors rated voltage, capacitance volume. Take for TDK C series X5R for example, its pressure
voltage value is 16V or 25V, the package size is 0805, 1206 or 0603, the capacitance value is 10uF. The
capacitor’s voltage stability of different types of capacitor is as shown below:
Capacitor Variation v.s. DC Voltage
10
0603,X5R,16V,10uF,0.80mm
0603,X5R,25V,10uF,0.80mm
0805,X5R,16V,10uF,0.85mm
0805,X5R,16V,10uF,1.25mm
0805,X5R,25V,10uF,0.85mm
0805,X5R,25V,10uF,1.25mm
1206,X5R,16V,10uF,0.85mm
1206,X5R,16V,10uF,1.60mm
1206,X5R,25V,10uF,0.85mm
1206,X5R,25V,10uF,1.60mm
0
-10
C-Change (%)
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
5
10
15
20
25
VDC (V)
Figure 22
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Different types of capacitive voltage stability
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Among them, the space remaining value of different types of capacitors at VDC = 8.5 V as shown
below：
Cap@VDC=8.5V
9
7.68uF
6.47uF
6.35uF
VDC=8.5V
2.84uF
2.70uF
1206,X5R,25V,10uF,1.60mm
1206,X5R,25V,10uF,0.85mm
1206,X5R,16V,10uF,1.60mm
1206,X5R,16V,10uF,0.85mm
0805,X5R,25V,10uF,1.25mm
0805,X5R,25V,10uF,0.85mm
0805,X5R,16V,10uF,1.25mm
0805,X5R,16V,10uF,0.85mm
0603,X5R,25V,10uF,0.80mm
0603,X5R,16V,10uF,0.80mm
2.34uF
2.20uF
1.93uF
1.74uF
1.72uF
8
0
Figure 23
1
2
3
4
5
C (uF)
6
7
8
9
10
The space remaining value of different types of capacitors at V DC = 8.5 V
It can be found that the rate of capacitance capacity value descent becomes slow along with "large
capacitor size, capacitance pressure voltage rise”. The larger the package size, the better voltage stability.
the higher the height, the better voltage stability with the same length and width of the capacitance.
Voltage stability of smaller package size (0603) capacitor change affected by the pressure value is very
small.
In AW87329 typical applications, it is necessary to ensure the output value of the PVDD
capacitor ≥3μF when PVDD=8.5V.
Input Capacitor-Cin（input high-pass cutoff frequency）
The input capacitors and input resistors form a high-pass filter to filter out the DC component of the
input signal. The -3dB frequency points of the high pass filter is shown below：
fH ( 3dB)
1
(Hz)
2 π Rintotal Cin
The selection of a smaller Cin capacitor in the application helps to filter out 217Hz noise, which comes
from the input coupling, and the smaller capacitor is advantageous to reduce the pop-click noise when the
power amplifier turn on.Better matching of the input capacitors improves performance of the circuit and
also helps to suppress pop-click noise. A capacitor value deviation of 10% or better capacitance is
recommended.
Take typical application as an example, the input high-pass cutoff frequency is calculated as below:
fH (3dB)
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1
1
(Hz) 376Hz
2 π R intotal Cin
2 π 9kΩ 47nF
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34
Class D-type speaker & receiver two-in-one application (Gain=1), the input high pass frequency is as
follows:
fH (3dB)
1
1
(Hz) 36Hz
2 π R intotal Cin
2 π 96kΩ 47nF
Class AB-type speaker & receiver two-in-one (Gain=1), the input high pass frequency is as follows:
fH (3dB)
1
1
(Hz) 70Hz
2 π R intotal Cin
2 π 48kΩ 47nF
Supply Decoupling Capacitor（CS）
A good decoupling capacitor can improve the efficiency and the best performance of the power
amplifier. At the same time, in order to get good high frequency transient performance, the ESR value of
the capacitor should be as small as possible. In AW87329 applications, low ESR
(equivalent-series-resistance) X7R or X5R ceramic capacitors are recommended. Generally, 10μF
ceramic capacitors are used to bypass the VDD to the ground, and the decoupling capacitor should be
placed as close to the VDD chip as possible in the layout. If you want to filter out low-frequency noise
better, you need to add a 10μF or greater decoupling capacitor depending on your application. Meanwhile,
a 33pF~0.1μF ceramic capacitor is placed on the pin of the power supply to filter the high frequency
interference on the power supply. The capacitor should be placed as close as possible to the D4 pin and
inductor.
Charge pump Flying capacitor (CF)
The Flying capacitor is used to transfer energy between the power supply and the charge pump load,
the value of the Flying capacitor directly affects the load regulation rate and the output drive capability of
the charge pump. Flying capacitor is too small, will affect the charge pump load adjustment rate and
output drive capability, thereby affecting the power output of the amplifier, and the larger the Flying
capacitor, the better the load regulation ability, driving ability is also stronger. Recommended use of
4.7μF, low ESR X7R, X5R ceramic capacitors, it is recommended to use more than 10V pressure
capacitor.
Output capacitance of charge pump（COUT）
The output capacitance of the charge pump and the ESR directly affect the ripple of the output, thus
affecting the performance of the power amplifier. Recommended use of 10μF, low ESR X7R or X5R
ceramic capacitors, you need to select the 25V voltage resistance capacitor.
Output beads, capacitors, TVS
Using EEE technology, in the class K mode, the AW87329 can also meet the FCC CLASS B
specification requirements. It is recommended to Use ferrite chip beads and capacitors if device near the
EMI sensitive circuits and/or there are long leads from amplifier to speaker, placed as close as possible to
the output pin.
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Waveform
before Bead
Waveform after
Bead
Bead
VOP
0.1nF
12V
Bead
VON
0.1nF
Figure 24
12V
Ferrite Chip Bead and capacitor
Amplifier output is a square wave signal. The voltage across the capacitor will be much larger than the
PVDD voltage after increasing the bead capacitor. It suggested the use of rated voltage above 16V
capacitor. At the same time a square wave signal at the output capacitor switching current form, the static
power consumption increases, so the output capacitance should not be too much which is recommended
0.1nF ceramic capacitor rated voltage of 16V. If you want to get better EMI suppression performance, can
use 1nF, rated voltage 16V capacitor, but quiescent current will increase.
Power amplifier output PWM signals of high voltage to PVDD voltage, voltage to 8.5 V, will produce
some ringing after bead capacitor, resulting in higher peak voltage. Recommended choose the operating
voltage of 12V TVS.
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PCB AND DEVICE LAYOUT CONSIDERATION
EXTERNAL COMPONENTS PLACEMENT
Figure 25
AW87329 External Components Placement
LAYOUT CONSIDERATIONS
This device is a power a power amplifier chip. To obtain the optimal performance, PCB layout should
be considered carefully. The suggested Layout is illustrated in the following diagram:
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Figure 26
AW87329 Board Layout
In order to obtain excellent performance of AW87329, PCB layout must be carefully considered. The
design consideration should follow the following principles:
1. In AW87329 peripheral device layout, you first need to guarantee the charge pump output
capacitance close to PVDD pin.
2. Try to provide a separate short and thick power line to AW87329, the copper width is recommended
to be larger than 0.75mm. The decoupling capacitors should be placed as close as possible to boost
power supply pin.
3. The input capacitors should be close to AW87329 INN and INP input pin, the input line should be
parallel to suppress noise coupling.
4. The beads and capacitor should be placed near to AW87329 VON and VOP pin. The output line from
AW87329 to speaker should be as short and thick as possible. The width is recommended to be
larger than 0.5mm.
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PACKAGE DESCRIPTION
TOP VIEW
BOTTOM VIEW
D
0.2875
0.2725
E
e2
e3
AWINIC
87329
XXXX
0.268±0.020
0.2725
Pin1
Pin1
0.2875
1
e1
SIDE VIEW
Symbol
A1
A
A1
A2
A2
A3
NOM
0.595
0.195
A
A3
D
E
e1
0.360
0.040
2.545
2.075
0
e2
e3
0.250
0.500
Tolerance
±0.055
±0.020
±0.025
±0.010
±0.025
±0.025
NA
NA
NA
Unit: mm
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Tape Description
PIN1
Unit: mm
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40
Reel Description
Note：
1. Surface resistivity: 105 to 1011 ohms/sq.
Unit: mm
2. The colour of reel is deep blue.
3. Restriction criterion of hazardous substance for packing material
follow GP-M001.
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41
VERSION INFORMATION
Version
Date
V1.0
2017-05-13
Description
AW87329CSR datasheet V1.0
DECLARATION：AWINIC Technology cannot assume responsibility for use of any circuitry other than
circuitry entirely embodied in an AWINIC Technologies product. No intellectual property or circuit patent
licenses are implied. AWINIC Technology reserves the right to change the circuitry and specifications
without notice at any time.
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42
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