74LV03D,118

74LV03 Quad 2-input NAND gate Rev. 4 — 31 August 2017 1 Product data sheet General description The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT03. The 74LV03 provides the 2-input NAND function. The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e., when one input is LOW, the output may be pulled to any voltage between GND and VO(max). This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. 2 Features and benefits • • • • • • • Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V @ VCC = 3.3 V, Tamb = 25 °C Typical VOHV (output VOH undershoot) > 2 V @ VCC = 3.3 V, Tamb = 25 °C Level shifter capability ESD protection: – HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3 Ordering information Table 1. Ordering information Type number 74LV03D Package Temperature range Name Description Version -40 °C to + 125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV03 Nexperia Quad 2-input NAND gate 4 Functional diagram 1 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 12 4A 13 4B 2 4 5 9 10 12 4Y 11 13 mna212 Figure 1. Logic symbol 5 & 3 & 6 & 8 Y A & 11 B aaa-008083 GND 001aab715 Figure 2. IEC logic symbol Figure 3. Logic diagram (one gate) Pinning information 5.1 Pinning 74LV03 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y aaa-027324 Figure 4. Pin configuration SO14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74LV03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 12 74LV03 Nexperia Quad 2-input NAND gate 6 Functional description Table 3. Function table [1] Output Input nA nB nY L L Z L H Z H L Z H H L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions Min Max Unit -0.5 +7.0 V VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA [1] - ±50 mA - ±25 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current VO = -0.5 V to (VCC + 0.5 V) ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C - 500 mW Ptot [1] [2] total power dissipation Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 8 mW/K above 70 °C. 74LV03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 12 74LV03 Nexperia Quad 2-input NAND gate 8 Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max 1.0 3.3 5.5 V [1] Unit VCC supply voltage VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V VCC = 3.6 V to 5.5 V - - 50 ns/V [1] 9 The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOL II HIGH-level input voltage LOW-level input voltage LOW-level output voltage input leakage current 74LV03 Product data sheet Conditions -40 °C to +85 °C Min Typ VCC = 1.2 V 0.9 VCC = 2.0 V [1] -40 °C to +125 °C Unit Max Min Max - - 0.9 - V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V IO = 100 μA; VCC = 1.2 V - 0 - - - V IO = 100 μA; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 4.5 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V IO = 12 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V - - 1.0 - 1.0 μA VI = VIH or VIL VI = VCC or GND; VCC = 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 12 74LV03 Nexperia Quad 2-input NAND gate Symbol Parameter Conditions -40 °C to +85 °C Min IOZ OFF-state output current per input pin; VCC = 2.0 V to 3.6 V; VI = VIL; VO = VCC or GND; other inputs at VCC or GND per input pin; VCC = 2.0 V to 3.6 V; VI = VIL; VO = 6.0 V; other inputs at VCC or GND [2] Typ [1] -40 °C to +125 °C Unit Max Min Max - - ±5.0 - ±10 μA - - ±10.0 - ±20 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20.0 - 40 μA ΔICC additional supply current per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 μA CI input capacitance - 3.5 - - - pF [1] [2] Typical values are measured at Tamb = 25 °C. The maximum operating output voltage (VO(max)) is 6.0 V. 10 Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 6. Symbol Parameter Conditions -40 °C to +85 °C Min tpd propagation delay nA, nB to nY; see Figure 5 Max Min Max VCC = 1.2 V - 50 - - - ns VCC = 2.0 V - 17 26 - 31 ns VCC = 2.7 V - 13 19 - 23 ns - 8 - - - ns - 10 16 - 19 ns - - 13 - 16 ns - 4 - - - pF VCC = 3.0 V to 3.6 V [3] VCC = 4.5 V to 5.5 V [1] [2] [3] [4] -40 °C to +125 °C Unit [2] VCC = 3.3 V; CL = 15 pF CPD Typ [1] power dissipation CL = 0 pF; RL = ∞ Ω; capacitance VI = GND to VCC [4] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLZ and tPZL. Typical values are measured at nominal supply voltage (VCC = 3.3 V). CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching 2 Σ(CL × VCC × fo) = sum of the outputs. 74LV03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 12 74LV03 Nexperia Quad 2-input NAND gate 10.1 Waveforms and test circuit VI nA, nB input VM GND t PZL t PLZ VCC nY output VM VOL VX mnb132 Measurement points are given in Table 8 VOL is a typical voltage output level that occurs with the output load. Figure 5. Inputs nA and nB to output nY propagation delay times Table 8. Measurement points Supply voltage Input Output VCC VM VX VM ≤ 2.7 V 0.5 × VCC VOL + 0.1 V 0.5 × VCC 2.7 V to 3.6 V 1.5 V VOL + 0.3 V 1.5 V ≥ 4.5 V 0.5 × VCC VOL + 0.1 V 0.5 × VCC 74LV03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 6 / 12 74LV03 Nexperia Quad 2-input NAND gate VI negative pulse tW 90 % VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9 Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Figure 6. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLZ, tPZL ≤ 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩ 2 × VCC 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 1 kΩ 2 × VCC ≥ 4.5 V VCC ≤ 2.5 ns 50 pF 1 kΩ 2 × VCC 74LV03 Product data sheet VEXT Load All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 7 / 12 74LV03 Nexperia Quad 2-input NAND gate 11 Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 7. Package outline SOT108-1 (SO14) 74LV03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 12 74LV03 Nexperia Quad 2-input NAND gate 12 Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV03 v.4 20170831 Product data sheet - 74LV03 v.3 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74LV03 v.3 20030303 Modifications: • Deleted DIL, SSOP and TSSOP package ordering and package outlines (discontinued options). • Corrected power dissipation formula. 74LV03 v.2 19980420 Product specification ECN 853-1963 19257 74LV03 v.1 74LV03 v.1 19970328 Product specification - - 74LV03 Product data sheet Product data sheet ECN 853-1963 29494 All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 74LV03 v.2 © Nexperia B.V. 2017. All rights reserved. 9 / 12 74LV03 Nexperia Quad 2-input NAND gate 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74LV03 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74LV03 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 31 August 2017 © Nexperia B.V. 2017. All rights reserved. 11 / 12 74LV03 Nexperia Quad 2-input NAND gate Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 2 Pinning ............................................................... 2 Pin description ................................................... 2 Functional description ........................................3 Limiting values .................................................... 3 Recommended operating conditions ................ 4 Static characteristics .......................................... 4 Dynamic characteristics .....................................5 Waveforms and test circuit ................................ 6 Package outline ...................................................8 Abbreviations ...................................................... 9 Revision history .................................................. 9 Legal information .............................................. 10 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 31 August 2017 Document identifier: 74LV03