MC74HCT259ADTG

MC74HCT259A 8-Bit Addressable Latch 1-of-8 Decoder with LSTTL Inputs High−Performance Silicon−Gate CMOS The MC74HCT259A is identical in pinout to the LS259. The device inputs are compatible with standard CMOS and LSTTL outputs. The HCT259A has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non−addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one−of−eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode all outputs are LOW and unaffected by the address and data inputs. When operating the HCT259A as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. Features • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices These are Pb−Free Devices http://onsemi.com MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 16 1 HCT259AG AWLYWW 1 16 HCT 259A ALYWG G TSSOP−16 DT SUFFIX CASE 948F 16 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT A0 1 16 VCC A1 2 15 RESET A2 3 14 ENABLE Q0 4 13 DATA IN Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 GND 8 9 Q4 MODE SELECTION TABLE Enable Reset Mode L H L H H H L L Addressable Latch Memory 8−Line Demultiplexer Reset ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2011 April, 2011 − Rev. 3 1 Publication Order Number: MC74HCT259A/D MC74HCT259A ADDRESS INPUTS 4 Q0 5 Q1 6 Q2 7 Q3 9 Q4 10 Q5 11 Q6 12 Q7 1 A0 2 A1 3 A2 DATA IN 13 15 RESET 14 ENABLE LATCH SELECTION TABLE Address Inputs NONINVERTING OUTPUTS PIN 16 = VCC PIN 8 = GND C B A Latch Addressed L L L L H H H H L L H H L L H H L H L H L H L H Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Figure 1. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) −0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature −65 to + 150 °C VESD ILatchup SOIC Package TSSOP Package ESD Withstand Voltage V Human Body Model (Note 1) Machine Model (Note 2) >2000 >200 Latchup Performance Above VDD and Below GND at 125°C (Note 3) mA ±100 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA / JESD22−A114−A. 2. Tested to EIA / JESD22−A115−A. 3. Tested to EIA / JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 2) Max Unit 4.5 5.5 V 0 VCC V −55 +125 °C 0 500 ns http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HCT259A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V − 55 to 25°C v 85°C v 125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC − 0.1 V |Iout| v 20 mA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC − 0.1 V |Iout| v 20 mA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V 4.5 3.98 3.84 3.70 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL 4.5 0.26 0.33 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 5.5 4 40 160 mA DICC Additional Quiescent Supply Current |Iout| v 5.2 mA V Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs Iout = 0mA http://onsemi.com 3 5.5 ≥ −55°C 25 to 125°C 2.9 2.4 mA MC74HCT259A AC ELECTRICAL CHARACTERISTICS (VCC = 4.5 to 5.5 V, CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter −55 to 25°C v 85°C v 125°C Unit tPLH, tPHL Maximum Propagation Delay, Data to Output (Figures 2 and 7) 32 32 42 ns tPLH, tPHL Maximum Propagation Delay, Address Select to Output (Figures 3 and 7) 32 40 45 ns tPLH, tPHL Maximum Propagation Delay, Enable to Output (Figures 4 and 7) 32 40 45 ns tPHL Maximum Propagation Delay, Reset to Output (Figures 5 and 7) 22 26 32 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 2 and 7) 15 19 22 ns Maximum Input Capacitance 10 10 10 pF Cin Typical @ 25°C, VCC = 5.0 V CPD 30 Power Dissipation Capacitance (Per Package) pF TIMING REQUIREMENTS (VCC = 4.5 to 5.5 V, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter −55 to 25°C v 85°C v 125°C Unit tsu Minimum Setup Time, Address or Data to Enable (Figure 6) 15 19 22 ns th Minimum Hold Time, Enable to Address or Data (Figure 6) 1 1 1 ns tw Minimum Pulse Width, Reset or Enable (Figure 4 or 5) 15 19 22 ns http://onsemi.com 4 MC74HCT259A SWITCHING WAVEFORMS 3.0V DATA IN GND 3.0V 1.3 V tf tr DATA IN 3.0 V 90% 1.3 V 10% 3.0V GND 1.3 V GND tPHL tPLH 90% 1.3 V 10% OUTPUT Q GND ADDRESS SELECT tPHL tPLH 50% 50% OUTPUT Q tTLH tTHL Figure 2. Figure 3. 3.0 V 3.0V DATA IN tw tw 1.3 V 1.3 V DATA IN GND GND tw VCC ENABLE tPHL tPLH 1.3 V RESET GND GND tPHL 50% OUTPUT Q 3.0V 1.3 V 50% OUTPUT Q Figure 4. Figure 5. TEST POINT DATA IN OR ADDRESS SELECT ENABLE OUTPUT 3.0V 1.3 V th(L) th(H) tsu tsu GND DEVICE UNDER TEST CL* 3.0V 1.3 V GND *Includes all probe and jig capacitance Figure 6. Figure 7. Test Circuit http://onsemi.com 5 MC74HCT259A DATA INPUT 13 D D D D 4 5 6 7 Q0 Q1 Q2 Q3 A0 ADDRESS INPUTS 3 TO 8 DECODER A1 D A2 D ENABLE 10 Q4 Q5 14 D D RESET 9 11 12 Q6 Q7 15 Figure 8. Expanded Logic Diagram ORDERING INFORMATION Package Shipping† MC74HCT259ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HCT259ADR2G SOIC−16 (Pb−Free) 2500 Tape & Reel TSSOP−16* 2500 Tape & Reel Device MC74HCT259ADTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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