Analog Multiplexers/
Demultiplexers with
Injection Current Effect
Control with LSTTL
Compatible Inputs
Automotive Customized
www.onsemi.com
MC74HCT4851A,
MC74HCT4852A
MARKING
DIAGRAMS
This device is pin compatible to standard HC405x and MC1405xB
analog mux/demux devices, but feature injection current effect
control. This makes them especially suited for usage in automotive
applications where voltages in excess of normal logic voltage are
common.
The injection current effect control allows signals at disabled analog
input channels to exceed the supply voltage range without affecting
the signal of the enabled analog channel. This eliminates the need for
external diode/ resistor networks typically used to keep the analog
channel signals within the supply voltage range.
The devices utilize low power silicon gate CMOS technology. The
Channel Select and Enable inputs are compatible with standard CMOS
or LSTTL outputs.
16
SOIC−16
D SUFFIX
CASE 751B
16
1
1
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
16
1
•
Injection Current Cross−Coupling Less than 1mV/mA (See Figure 6)
Pin Compatible to HC405x and MC1405xB Devices
Power Supply Range (VCC − GND) = 4.5 to 5.5 V
In Compliance With the Requirements of JEDEC Standard No. 7 A
Chip Complexity: 154 FETs or 36 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
HCT485xA
AWLYWWG
1
16
Features
•
•
•
•
•
•
HCT485xAG
AWLYWW
TSSOP−16
DT SUFFIX
CASE 948F
16
1
X
A
WL, L
YY, Y
WW, W
G or G
HCT4
85xA
ALYWG
G
1
= 1 or 2
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2021 − Rev. 10
1
Publication Order Number:
MC74HCT4851A/D
MC74HCT4851A, MC74HCT4852A
FUNCTION TABLE − MC74HCT4851A
Control Inputs
13
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
DEMULTIPLEXER
OUTPUTS X4 1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = VCC
PIN 8 = GND
3
X
Select
B
A
Enable
C
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
COMMON
OUTPUT/
INPUT
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
H
L
H
L
H
L
H
X
VCC
X2
X1
X0
X3
A
B
C
16
15
14
13
12
11
10
9
6
7
Figure 1. MC74HCT4851A Logic Diagram
Single−Pole, 8−Position Plus Common Off
1
2
3
4
5
X4
X6
X
X7
X5
Enable NC
8
GND
Figure 2. MC74HCT4851A 16−Lead Pinout (Top View)
FUNCTION TABLE − MC74HCT4852A
Control Inputs
12
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
ENABLE
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
1
5
2
Y SWITCH
3
B
L
L
L
L
H
L
L
H
H
X
Select
A
ON Channels
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
X1
X2
X3
NONE
X = Don’t Care
Y
4
10
9
Enable
PIN 16 = VCC
PIN 8 = GND
VCC
X2
X1
X
X0
X3
A
B
16
15
14
13
12
11
10
9
6
7
8
GND
6
Figure 3. MC74HCT4852A Logic Diagram
Double−Pole, 4−Position Plus Common Off
1
2
3
4
5
Y0
Y2
Y
Y3
Y1
Enable NC
Figure 4. MC74HCT4852A 16−Lead Pinout (Top View)
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2
MC74HCT4851A, MC74HCT4852A
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
Positive DC Supply Voltage
(Referenced to GND)
–0.5 to + 7.0
V
Vin
DC Input Voltage (Any Pin)
(Referenced to GND)
–0.5 to VCC + 0.5
V
$25
mA
500
450
mW
–65 to + 150
°C
I
Parameter
DC Current, Into or Out of Any Pin
PD
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
Tstg
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
°C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
VCC
Positive DC Supply Voltage
(Referenced to GND)
4.5
5.5
V
Vin
DC Input Voltage (Any Pin)
(Referenced to GND)
GND
VCC
V
Static or Dynamic Voltage Across Switch
0.0
1.2
V
TA
Operating Temperature Range, All Package Types
– 55
+ 125
°C
tr, tf
Input Rise/Fall Time
(Channel Select or Enable Inputs)
0
0
0
1000
500
400
ns
VIO*
Parameter
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol
Parameter
Condition
VCC
V
Guaranteed Limit
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec
4.5
to
5.5
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec
4.5
to
5.5
0.8
0.8
0.8
V
Iin
Maximum Input Leakage Current on Digital Pins
(Enable/A/B/C)
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin(digital) = VCC or GND
Vin(analog) = GND
5.5
2.0
20
40
mA
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3
MC74HCT4851A, MC74HCT4852A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Condition
VCC
−55 to 25°C
Maximum “ON” Resistance
Vin = VIL or VIH; VIS = VCC to
GND (Note 1); IS ≤ 2.0 mA
(Note 2)
4.5
5.5
550
400
650
500
750
600
W
Delta “ON” Resistance
Vin = VIL or VIH; VIS = VCC/2
(Note 1); IS ≤ 2.0 mA (Note 2)
4.5
5.5
80
60
100
80
120
100
W
Ioff
Maximum Off−Channel Leakage Current,
Any One Channel
Common Channel
Vin = VCC or GND
5.5
±0.1
±0.1
±0.1
±0.1
±0.1
±0.1
Ion
Maximum On−Channel Leakage
Channel−to−Channel
Vin = VCC or GND
5.5
±0.1
±0.1
±0.1
VCC
−55 to 25°C
≤85°C
≤125°C
Unit
Maximum Propagation Delay, Analog Input to Analog Output
5.0
40
45
50
ns
Maximum Propagation Delay, Enable or Channel−Select to Analog Output
5.0
80
90
100
ns
10
35
40
10
35
40
10
35
40
pF
Symbol
Ron
DRon
Parameter
≤85°C
≤125°C
Unit
mA
mA
1. VIS is the input voltage of an analog I/O pin.
2. IS is the currebnt flowing in or out of analog I/O pin.
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%)
Parameter
Symbol
tPHL,
tPLH
tPHL,
tPHZ,PZH
tPLH,
tPLZ,PZL
Cin
Maximum Input Capacitance
(All Switches Off)
(All Switches Off)
CPD
Power Dissipation Capacitance
Digital Pins
Any Single Analog Pin
Common Analog Pin
Typical
5.0
20
pF
INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = −55°C to +125°C)
Symbol
VDout
Parameter
Condition
Maximum Shift of Output Voltage of Enabled Analog Channel
Iin* ≤ 1 mA, RS ≤ 3,9 kW
Iin* ≤ 10 mA, RS ≤ 3,9 kW
Iin* ≤ 1 mA, RS ≤ 20 kW
Iin* ≤ 10 mA, RS ≤ 20 kW
* Iin = Total current injected into all disabled channels.
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4
Typ
Max
Unit
0.1
1.0
0.5
5.0
1.0
5.0
2.0
20
mV
MC74HCT4851A, MC74HCT4852A
Figure 5. Typical On Resistance VCC = 4.5V
External DC P.S.
VCC = 5 V
Vin2 / Iin2 meas. here.
Current Source
HP4155C
Smu #2
Vin1 = 4.9 V (Smu3)
Iin1 measure here
Vm1 connected here.
4
16
13
3
X7
RS
X0
X
Vout
Vm2 connected here.
6
NOTES: Rs = 3.9 KW or 20 KW.
NOTES: Vm1 & Vm2 are internal
NOTES:
HP4155C Voltmeters.
8
GND or VSS
Figure 6. Injection Current Coupling Specification
www.onsemi.com
5
MC74HCT4851A, MC74HCT4852A
5V
6V
5V
VCC
VCC
HCT4051A
Sensor
Microcontroller
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D - Input
Figure 7. Actual Technology
Requires 32 passive components and one extra 6V regulator
to suppress injection current into a standard HCT4051 multiplexer
5V
VCC
VCC
HCT4851A
Sensor
Microcontroller
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D - Input
Figure 8. MC74HCT4851A Solution
Solution by applying the HCT4851A multiplexer
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6
MC74HCT4851A, MC74HCT4852A
PLOTTER
VCC
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
16
VEE
VCC
OFF
-
+
VCC
VCC
A
COMMON O/I
OFF
NC
DEVICE
UNDER TEST
ANALOG IN
VIH
COMMON OUT
6
8
GND
Figure 10. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 9. On Resistance Test Set−Up
VCC
16
VEE
ANALOG I/O
VCC
A
VEE
16
A
OFF
VCC
OFF
VIH
VCC
VCC
ON
COMMON O/I
VCC
N/C
ANALOG I/O
VIL
6
COMMON O/I
OFF
6
8
8
Figure 11. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
Figure 12. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
VCC
VCC
CHANNEL
SELECT
(VI)
ON/OFF
VM
COMMON O/I
ANALOG I/O
OFF/ON
GND
tPLH
ANALOG
OUT
16
VCC
TEST
POINT
CL*
tPHL
6
50%
8
CHANNEL SELECT
VI = GND to 3.0 V
VM = 1.3 V
*Includes all probe and jig capacitance
Figure 13. Propagation Delays, Channel Select
to Analog Out
Figure 14. Propagation Delay, Test Set−Up Channel
Select to Analog Out
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7
MC74HCT4851A, MC74HCT4852A
VCC
16
VCC
ANALOG
IN
(VI)
COMMON O/I
ANALOG I/O
ON
50%
TEST
POINT
CL*
GND
tPLH
tPHL
ANALOG
OUT
6
8
50%
VI = GND to 3.0 V
VM = 1.3 V
*Includes all probe and jig capacitance
Figure 15. Propagation Delays, Analog In
to Analog Out
Figure 16. Propagation Delay, Test Set−Up
Analog In to Analog Out
tr
tf
90%
VM
10%
ENABLE
(VI)
tPZL
ANALOG
OUT
2
GND
tPLZ
16
HIGH
IMPEDANCE
10%
1
10kW
ANALOG I/O
TEST
POINT
ON/OFF
2
CL*
VOL
tPHZ
ENABLE
VOH
90%
ANALOG
OUT
VCC
VCC
50%
tPZH
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
1
VCC
50%
6
8
HIGH
IMPEDANCE
VI = GND to 3.0 V
VM = 1.3 V
Figure 17. Propagation Delays, Enable to
Analog Out
Figure 18. Propagation Delay, Test Set−Up
Enable to Analog Out
VCC
VCC
A
16
COMMON O/I
NC
ANALOG I/O
VCC
6
11
8
CHANNEL SELECT
Figure 19. Power Dissipation Capacitance,
Test Set−Up
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8
MC74HCT4851A, MC74HCT4852A
Gate = VCC
(Disabled)
Disabled Analog Mux Input
Vin > VCC + 0.7V
P+
Common Analog Output
Vout > VCC
P+
+
+
+
N - Substrate (on VCC potential)
Figure 20. Diagram of Bipolar Coupling Mechanism
Appears if Vin exceeds VCC, driving injection current into the substrate
A
B
C
ENABLE
11
10
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
14
INJECTION
CURRENT
CONTROL
15
INJECTION
CURRENT
CONTROL
12
INJECTION
CURRENT
CONTROL
1
INJECTION
CURRENT
CONTROL
5
INJECTION
CURRENT
CONTROL
2
INJECTION
CURRENT
CONTROL
4
INJECTION
CURRENT
CONTROL
3
X0
X1
X2
X3
9
6
Figure 21. Function Diagram, HCT4851A
www.onsemi.com
9
X4
X5
X6
X7
X
MC74HCT4851A, MC74HCT4852A
A
B
ENABLE
10
9
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
14
INJECTION
CURRENT
CONTROL
15
13
INJECTION
CURRENT
CONTROL
12
INJECTION
CURRENT
CONTROL
3
INJECTION
CURRENT
CONTROL
1
INJECTION
CURRENT
CONTROL
5
INJECTION
CURRENT
CONTROL
2
INJECTION
CURRENT
CONTROL
4
INJECTION
CURRENT
CONTROL
3
X0
X1
X2
X3
X
Y0
Y1
6
Figure 22. Function Diagram, HCT4852A
www.onsemi.com
10
Y2
Y3
Y
MC74HCT4851A, MC74HCT4852A
ORDERING INFORMATION
Device
MC74HCT4851ADG
MC74HCT4851ADR2G
Package
Shipping†
SOIC−16
(Pb−Free)
48 Units / Rail
2500 Units / Tape & Reel
NLV74HCT4851ADRG*
2500 Units / Tape & Reel
MC74HCT4851AADR2G
2500 Units / Tape & Reel
NLV74HCT4851AADR2G*
(Contact ON Semiconductor)
2500 Units / Tape & Reel
MC74HCT4851ADTG
M74HCT4851ADTR2G
TSSOP−16
(Pb−Free)
NLVHCT4851ADTR2G*
M74HCT4851ADWR2G
MC74HCT4852ADG
MC74HCT4852ADR2G
MC74HCT4852ADTG
M74HCT4852ADTR2G
48 Units / Rail
2500 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC−16 WIDE
(Pb−Free)
1000 Units / Tape & Reel
SOIC−16
(Pb−Free)
48 Units / Rail
TSSOP−16
(Pb−Free)
NLVHCT4852ADTR2G*
2500 Units / Tape & Reel
48 Units / Rail
2500 Units / Tape & Reel
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G
ISSUE E
1
SCALE 1:1
DATE 08 OCT 2021
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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