MC74HCT4053ADTG

MC74HCT4051A, MC74HCT4052A, MC74HCT4053A Analog Multiplexers / Demultiplexers with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT4051A, MC74HCT4052A and MC74HCT4053A utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HCT4051A, HCT4052A and HCT4053A are identical in pinout to the metal −gate MC14051AB, MC14052AB and MC14053AB. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel−Select and Enable inputs are compatible with standard CMOS and LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal−gate CMOS analog switches. For a multiplexer/demultiplexer with injection current protection, see HC4851A and HCT4851A. Features 16 SOIC−16 WIDE DW SUFFIX CASE 751G 1 1 SOIC−16 D SUFFIX CASE 751B 16 HCT405xAG AWLYWW 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F 1 x = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location) HCT40 5xA ALYWG G HCT405xA AWLYWWG http://onsemi.com MARKING DIAGRAMS 16 16 1 • • • • • • • • • • Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal−Gate Counterparts Low Noise In Compliance with the Requirements of JEDEC Standard No. 7A Chip Complexity: HCT4051A − 184 FETs or 46 Equivalent Gates HCT4052A − 168 FETs or 42 Equivalent Gates HCT4053A − 156 FETs or 39 Equivalent Gates These are Pb−Free Devices ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. © Semiconductor Components Industries, LLC, 2010 January, 2010 − Rev. 0 1 Publication Order Number: MC74HCT4051A/D MC74HCT4051A, MC74HCT4052A, MC74HCT4053A FUNCTION TABLE − MC74HCT4051A Control Inputs X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 13 Enable 3 C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE X = Don’t Care COMMON X OUTPUT/ INPUT L L L L L L L L H VCC 16 X2 15 X1 14 X0 13 X3 12 A 11 B 10 C 9 Figure 1. Logic Diagram − MC74HCT4051A Single−Pole, 8−Position Plus Common Off 1 X4 2 X6 3 X 4 X7 5 X5 6 7 8 GND Enable VEE Figure 2. Pinout: MC74HCT4051A (Top View) FUNCTION TABLE − MC74HCT4052A Control Inputs Enable X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B 1 5 2 4 10 9 6 12 13 B L L H H X Select A L H L H X ON Channels Y0 Y1 Y2 Y3 NONE X0 X1 X2 X3 X SWITCH X COMMON OUTPUTS/INPUTS ANALOG INPUTS/OUTPUTS L L L L H X = Don’t Care VCC 16 X2 15 Y SWITCH 3 Y X1 14 X 13 X0 12 X3 11 A 10 B 9 CHANNEL‐SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND ENABLE Figure 3. Logic Diagram − MC74HCT4052A Double−Pole, 4−Position Plus Common Off 1 Y0 2 Y2 3 Y 4 Y3 5 Y1 6 7 Enable VEE 8 GND Figure 4. Pinout: MC74HCT4052A (Top View) http://onsemi.com 2 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A FUNCTION TABLE − MC74HCT4053A Control Inputs Enable 12 C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X0 13 X1 Y0 1 Y1 Z0 3 Z1 CHANNEL‐SELECT INPUTS A 10 B 9 C 6 ENABLE 11 5 2 X SWITCH 14 X ANALOG INPUTS/OUTPUTS Y SWITCH 15 Y COMMON OUTPUTS/INPUTS L L L L L L L L H Z SWITCH 4 Z X = Don’t Care PIN 16 = VCC PIN 7 = VEE PIN 8 = GND VCC 16 Y 15 X 14 X1 13 X0 12 A 11 B 10 C 9 NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch Figure 5. Logic Diagram − MC74HCT4053A Triple Single−Pole, Double−Position Plus Common Off 1 Y1 2 Y0 3 Z1 4 Z 5 Z0 6 7 Enable VEE 8 GND Figure 6. Pinout: MC74HCT4053A (Top View) Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol VCC VEE VIS Vin I PD Parameter Value Unit V V V V Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) −0.5 to +7.0 −0.5 to +14.0 −7.0 to +5.0 Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage VEE − 0.5 to VCC + 0.5 Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air, Storage Temperature Range −0.5 to VCC + 0.5 ±25 500 450 mA SOIC Package† TSSOP Package† mW °C Tstg −65 to +150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating − SOIC Package: − 7 mW/°C from 65°C to 125°C TSSOP Package: − 6.1 mW/°C from 65°C to 125°C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. http://onsemi.com 3 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎ Î Î ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Symbol VCC VEE VIS Vin TA Parameter Min 2.0 2.0 Max Unit V V V V V Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) 6.0 12.0 Negative DC Supply Voltage, Output (Referenced to GND) Analog Input Voltage −6.0 VEE GND VCC VCC 1.2 Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch GND VIO* tr, tf Operating Temperature Range, All Package Types Input Rise/Fall Time (Channel Select or Enable Inputs) −55 0 0 0 0 +125 1000 600 500 400 °C ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. RECOMMENDED OPERATING CONDITIONS DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol VIH VIL Iin ICC Parameter Minimum High−Level Input Voltage, Channel−Select or Enable Inputs Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs Maximum Input Leakage Current, Channel−Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Condition Ron = Per Spec Ron = Per Spec Vin = VCC or GND, VEE = − 6.0 V Channel Select, Enable and VIS = VCC or GND; VEE = GND VEE = − 6.0 VIO = 0 V VCC V 4.5 to 5.5 4.5 to 5.5 6.0 Guaranteed Limit −55 to 25°C 2.0 0.8 ±0.1 ≤85°C 2.0 0.8 ±1.0 ≤125°C 2.0 0.8 ±1.0 Unit V V mA mA 6.0 6.0 1 4 10 40 20 80 http://onsemi.com 4 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A DC CHARACTERISTICS − Analog Section Guaranteed Limit Symbol Ron Parameter Maximum “ON” Resistance Condition Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA (Figures 7, 8) Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 7, 8) DRon Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 3) VCC 4.5 4.5 6.0 4.5 4.5 6.0 4.5 4.5 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 VEE 0.0 −4.5 −6.0 0.0 −4.5 −6.0 0.0 −4.5 −6.0 −6.0 −6.0 −6.0 −6.0 −6.0 −6.0 −6.0 −55 to 25°C 190 120 100 150 100 80 30 12 10 0.1 0.2 0.1 0.1 0.2 0.1 0.1 ≤85°C 240 150 125 190 125 100 35 15 12 0.5 2.0 1.0 1.0 2.0 1.0 1.0 ≤125°C 280 170 140 230 140 115 40 18 14 1.0 4.0 2.0 2.0 4.0 2.0 2.0 mA W Unit W Ioff mA Maximum Off−Channel HCT4051A Vin = VIL or VIH; Leakage Current, HCT4052A VIO = VCC − VEE; Common Channel HCT4053A Switch Off (Figure 10) Ion Maximum On−Channel HCT4051A Vin = VIL or VIH; Leakage Current, HCT4052A Switch−to−Switch = Channel−to−Channel HCT4053A VCC − VEE; (Figure 11) http://onsemi.com 5 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Channel−Select to Analog Output (Figure 15) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit −55 to 25°C 270 90 59 45 40 25 12 10 160 70 48 39 245 115 49 39 10 35 130 80 50 1.0 ≤85°C 320 110 79 65 60 30 15 13 200 95 63 55 315 145 69 58 10 35 130 80 50 1.0 ≤125°C 350 125 85 75 70 32 18 15 220 110 76 63 345 155 83 67 10 35 130 80 50 1.0 Unit ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 16) ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 17) ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 17) ns Cin CI/O Maximum Input Capacitance, Channel−Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I: HCT4051A HCT4052A HCT4053A Feed−through pF pF Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 19)* HCT4051A HCT4052A HCT4053A 45 80 45 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . http://onsemi.com 6 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW Parameter Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 12) Condition fin = 1 MHz Sine Wave; Adjust fin Voltage to Obtain 0 dBm at VOS; Increase fin Frequency Until dB Meter Reads −3 dB; RL = 50 W, CL = 10 pF fin = Sine Wave; Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF VCC V VEE V ‘51 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 −2.25 −4.50 −6.00 −2.25 −4.50 −6.00 −2.25 −4.50 −6.00 −2.25 −4.50 −6.00 −2.25 −4.50 −6.00 −2.25 −4.50 −6.00 −2.25 −4.50 −6.00 80 80 80 Limit* 25°C ‘52 95 95 95 −50 −50 −50 −40 −40 −40 25 105 135 35 145 190 −50 −50 −50 −60 −60 −60 % 2.25 4.50 6.00 −2.25 −4.50 −6.00 0.10 0.08 0.05 dB mVPP ‘53 120 120 120 dB Unit MHz − Off−Channel Feed−through Isolation (Figure 13) fin = 1.0 MHz, RL = 50 W, CL = 10 pF − Feedthrough Noise. Channel−Select Input to Common I/O (Figure 14) Vin ≤ 1 MHz Square Wave (tr = tf = 6 ns); Adjust RL at Setup so that IS = 0 A; Enable = GND RL = 600 W, CL = 50 pF RL = 10 kW, CL = 10 pF − Crosstalk Between Any Two Switches (Figure 18) (Test does not apply to HCT4051A) fin = Sine Wave; Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF THD Total Harmonic Distortion (Figure 20) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDmeasured − THDsource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Limits not tested. Determined by design and verified by qualification. 300 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 250 200 125°C 150 100 50 0 25°C - 55°C 180 160 140 120 100 80 60 40 20 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE - 55°C 125°C 25°C VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 7. Figure 7a. Typical On Resistance, VCC − VEE = 2.0 V Figure 7b. Typical On Resistance, VCC − VEE = 3.0 V http://onsemi.com 7 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A 120 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 100 80 60 25°C 40 20 0 - 55°C 105 90 75 60 45 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 125°C 25°C - 55°C 125°C VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 7c. Typical On Resistance, VCC − VEE = 4.5 V Figure 7d. Typical On Resistance, VCC − VEE = 6.0 V 80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 25°C - 55°C 125°C 60 50 40 30 - 55°C 20 10 0 0 125°C 25°C 1 2 3 4 5 6 7 8 9 10 11 12 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 7e. Typical On Resistance, VCC − VEE = 9.0 V Figure 7f. Typical On Resistance, VCC − VEE = 12.0 V PLOTTER PROGRAMMABLE POWER SUPPLY + MINI COMPUTER DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND VEE Figure 8. On Resistance Test Set−Up http://onsemi.com 8 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC VCC VEE OFF VCC A NC OFF 16 VCC VEE VCC 16 ANALOG I/O OFF OFF VCC COMMON O/I COMMON O/I VIH 6 7 8 VIH 6 7 8 VEE VEE Figure 9. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 10. Maximum Off Channel Leakage Current, Common Channel, Test Set−Up VCC A ON VEE VCC ANALOG I/O VIL 6 7 8 OFF VCC 16 VCC fin COMMON O/I N/C 0.1mF ON 16 VOS dB METER CL* RL 6 7 8 VEE *Includes all probe and jig capacitance VEE Figure 11. Maximum On Channel Leakage Current, Channel to Channel, Test Set−Up Figure 12. Maximum On Channel Bandwidth, Test Set−Up VIS 0.1mF fin RL OFF VCC 16 VOS dB METER CL* RL RL ON/OFF ANALOG I/O OFF/ON RL VCC 16 COMMON O/I RL CL* TEST POINT 6 7 8 VEE VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance 3.0 V GND Vin ≤ 1 MHz tr = tf = 6 ns 6 7 8 VEE VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 13. Off Channel Feedthrough Isolation, Test Set−Up Figure 14. Feedthrough Noise, Channel Select to Common Out, Test Set−Up http://onsemi.com 9 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC VCC CHANNEL SELECT (VI) tPLH ANALOG OUT VI = GND to 3.0 V Vm = 1.3 V Vm GND tPHL 6 7 8 CHANNEL SELECT *Includes all probe and jig capacitance ON/OFF ANALOG I/O OFF/ON CL* VCC 16 COMMON O/I TEST POINT 50% Figure 15a. Propagation Delays, Channel Select to Analog Out Figure 15b. Propagation Delay, Test Set−Up Channel Select to Analog Out Figure 15. VCC 16 VCC ANALOG I/O ON CL* GND COMMON O/I TEST POINT ANALOG IN tPLH ANALOG OUT 50% tPHL 50% 6 7 8 *Includes all probe and jig capacitance Figure 16a. Propagation Delays, Analog In to Analog Out Figure 16. tf ENABLE (VI) VM tPZL ANALOG OUT 50% 10% tPZH ANALOG OUT VI = GND to 3.0 V Vm = 1.3 V 50% HIGH IMPEDANCE tPHZ 90% VOH VOL tPLZ tr 90% VM 10% VCC GND HIGH IMPEDANCE Figure 16b. Propagation Delay, Test Set−Up Analog In to Analog Out 1 2 VCC 1 2 POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 ANALOG I/O ON/OFF CL* ENABLE 1kW TEST POINT 6 7 8 Figure 17a. Propagation Delays, Enable to Analog Out Figure 17. Figure 17b. Propagation Delay, Test Set−Up Enable to Analog Out http://onsemi.com 10 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A VCC VIS VCC RL fin 0.1mF OFF VEE RL 6 7 8 *Includes all probe and jig capacitance RL CL* RL CL* VEE 6 7 8 VCC 11 ON 16 VOS ANALOG I/O OFF/ON ON/OFF 16 COMMON O/I NC A CHANNEL SELECT Figure 18. Crosstalk Between Any Two Switches, Test Set−Up 0 VCC 0.1mF fin ON RL CL* 16 VOS TO DISTORTION METER dB - 10 - 20 - 30 - 40 - 50 - 60 6 7 8 VEE *Includes all probe and jig capacitance - 70 - 80 - 90 - 100 Figure 19. Power Dissipation Capacitance, Test Set−Up VIS FUNDAMENTAL FREQUENCY DEVICE SOURCE Figure 20. Figure 20a. Total Harmonic Distortion, Test Set−Up 1.0 2.0 FREQUENCY (kHz) 3.125 Figure 20b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 21, a maximum analog signal of ten volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feed−through noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC − GND = 2 to 6 V VEE − GND = 0 to −6 V VCC − VEE = 2 to 12 V and VEE ≤ GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 22. These diodes should be able to absorb the maximum anticipated current surges during clipping. http://onsemi.com 11 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A +5V +5V -5V 16 ANALOG SIGNAL ON ANALOG SIGNAL +5V -5V VCC Dx VCC 16 ON/OFF Dx VEE 6 7 8 -5V 11 10 9 TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS VEE Dx VEE VCC Dx 7 8 Figure 21. Application Example Figure 22. External Germanium or Schottky Clipping Diodes +5V +5V VEE 16 ANALOG SIGNAL ON/OFF HC405x 6 7 8 VEE 11 10 9 * 2K ≤ R ≤ 10K ANALOG SIGNAL +5V * R R +5V VEE R LSTTL/NMOS CIRCUITRY VEE 6 7 8 11 10 9 +5V VEE 16 ANALOG SIGNAL ON/OFF HCT405x +5V ANALOG SIGNAL +5V VEE +5V LSTTL/NMOS CIRCUITRY a. Using Pull−Up Resistors with a HC Device b. Using HCT Interface Figure 23. Interfacing LSTTL/NMOS to CMOS Inputs 11 LEVEL SHIFTER 13 A X0 14 X1 B 10 LEVEL SHIFTER 15 X2 12 X3 C 9 LEVEL SHIFTER 1 X4 5 X5 ENABLE 6 LEVEL SHIFTER 2 X6 4 X7 3 Figure 24. Function Diagram, HCT4051A X http://onsemi.com 12 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A A 10 LEVEL SHIFTER 12 X0 14 X1 B 9 LEVEL SHIFTER 15 X2 11 13 ENABLE 6 LEVEL SHIFTER 1 X3 X Y0 5 Y1 2 Y2 4 Y3 3 Y Figure 26. Function Diagram, HCT4052A A 11 LEVEL SHIFTER 13 X1 12 14 B 10 LEVEL SHIFTER 1 X0 X Y1 2 15 C 9 LEVEL SHIFTER 3 Y0 Y Z1 5 4 ENABLE 6 LEVEL SHIFTER Z0 Z Figure 25. Function Diagram, HCT4053A http://onsemi.com 13 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ORDERING INFORMATION Device MC74HCT4051ADG MC74HCT4051ADR2G MC74HCT4051ADTG MC74HCT4051ADTR2G MC74HCT4051ADWG MC74HCT4051ADWR2G MC74HCT4052ADG MC74HCT4052ADR2G MC74HCT4052ADTG MC74HCT4052ADTR2G MC74HCT4052ADWG MC74HCT4052ADWR2G MC74HCT4053ADG MC74HCT4053ADR2G MC74HCT4053ADTG MC74HCT4053ADTR2G MC74HCT4053ADWG MC74HCT4053ADWR2G Package SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16* TSSOP−16* SOIC−16 WIDE (Pb−Free) SOIC−16 WIDE (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16* TSSOP−16* SOIC−16 WIDE (Pb−Free) SOIC−16 WIDE (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16* TSSOP−16* SOIC−16 WIDE (Pb−Free) SOIC−16 WIDE (Pb−Free) Shipping† 48 Units / Rail 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel 48 Units / Rail 1000 / Tape & Reel 48 Units / Rail 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel 48 Units / Rail 1000 / Tape & Reel 48 Units / Rail 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel 48 Units / Rail 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 14 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A PACKAGE DIMENSIONS SOIC−16 WIDE DW SUFFIX CASE 751G−03 ISSUE C D 16 M 9 A q h X 45 _ 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ H M B 8X 1 16X 8 B TA S 0.25 M B S A E B A1 14X e SEATING PLANE T C http://onsemi.com 15 L MC74HCT4051A, MC74HCT4052A, MC74HCT4053A PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K −A− 16 9 −B− 1 8 P 8 PL 0.25 (0.010) M B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S SOLDERING FOOTPRINT* 6.40 16X 8X 1.12 16 1 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 16 MC74HCT4051A, MC74HCT4052A, MC74HCT4053A PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 2X L/2 16 9 J1 B −U− SECTION N−N L PIN 1 IDENT. 1 8 J N 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.36 16X 16X 1.26 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 ÉÉ Ç ÇÇ ÉÉ Ç ÇÇ −W− 0.65 PITCH DIMENSIONS: MILLIMETERS MC74HCT4051A, MC74HCT4052A, MC74HCT4053A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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