MC74HCT4066A
Quad Analog Switch/
Multiplexer/Demultiplexer
with LSTTL Compatible
Inputs
http://onsemi.com
High−Performance Silicon−Gate CMOS
The MC74HCT4066A utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
O F F −c h a n n e l l e a k a g e c u r r e n t . T h i s b i l a t e r a l s w i t c h /
multiplexer/demultiplexer controls analog and digital voltages that
may vary across the full power−supply range (from VCC to GND).
The HCT4066A is identical in pinout to the metal−gate CMOS
MC14016 and MC14066. Each device has four independent switches.
The device has been designed so the ON resistances (RON) are more
linear over input voltage than RON of metal−gate CMOS analog
switches.
The ON/OFF control inputs are compatible with standard CMOS and
LSTTL outputs. For analog switches with voltage−level translators, see
the HC4316A.
Features
•
•
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Wide Power−Supply Voltage Range (VCC − GND) = 4.5 to 5.5 V
Analog Input Voltage Range (VCC − GND) = 0 to 5.5 V
Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
Low Noise
Chip Complexity: 44 FETs or 11 Equivalent Gates
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
November, 2010 − Rev. 1
1
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
14
1
HCT4066AG
AWLYWW
1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
A
L, WL
Y, YY
W, WW
G or
HCT40
66A
ALYW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC74HCT4066A/D
MC74HCT4066A
XA
1
14
VCC
YA
2
13
A ON/OFF CONTROL
YB
3
12
D ON/OFF CONTROL
XB
4
11
XD
B ON/OFF CONTROL
5
10
YD
C ON/OFF CONTROL
6
9
YC
GND
7
8
XC
XA
A ON/OFF CONTROL
XB
B ON/OFF CONTROL
XC
C ON/OFF CONTROL
Figure 1. Pin Assignment
FUNCTION TABLE
On/Off Control
Input
State of
Analog Switch
L
H
Off
On
XD
D ON/OFF CONTROL
1
2
YA
13
4
3
YB
5
8
9
YC
ANALOG
OUTPUTS/INPUTS
6
11
10
YD
12
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
PIN 14 = VCC
PIN 7 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
Package
Shipping†
MC74HCT4066ADG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74HCT4066ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
TSSOP−14*
2500 / Tape & Reel
Device
MC74HCT4066ADTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
2
MC74HCT4066A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +14.0
V
Analog Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Digital Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
±25
mA
500
450
mW
–65 to +150
°C
VCC
Positive DC Supply Voltage (Referenced to GND)
VIS
Vin
I
DC Current Into or Out of Any Pin
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating − SOIC Package: – 7 mW/°C from 65°C to 125°C
TSSOP Package: − 6.1 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
4.5
5.5
V
VCC
Positive DC Supply Voltage (Referenced to GND)
VIS
Analog Input Voltage (Referenced to GND)
GND
VCC
V
Vin
Digital Input Voltage (Referenced to GND)
GND
VCC
V
VIO*
Static or Dynamic Voltage Across Switch
−
1.2
V
–55
+125
°C
0
500
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time, ON/OFF Control Inputs
(Figure 10)
ns
VCC = 4.5 V
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
– 55 to
25°C
v 85°C
v 125°C
Unit
VIH
Minimum High−Level Voltage
ON/OFF Control Inputs
Ron = Per Spec
4.5 to 5.5
2.0
2.0
2.0
V
VIL
Maximum Low−Level Voltage
ON/OFF Control Inputs
Ron = Per Spec
4.5 to 5.5
0.8
0.8
0.8
V
Iin
Maximum Input Leakage Current
ON/OFF Control Inputs
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
A
ICC
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
VIO = 0 V
5.5
2
20
40
A
ICC
Additional Quiescent Supply Current
(per Input)
Vin = VCC − 2.1 V
Other control inputs at VCC
or GND
4.5 to 5.5
360
450
490
A
Symbol
Parameter
Test Conditions
http://onsemi.com
3
MC74HCT4066A
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Ron
Parameter
VCC
V
– 55 to
25°C
v 85°C
v 125°C
Unit
Vin = VIH
VIS = VCC to GND
IS v 2.0 mA (Figures 3, 4)
4.5
120
160
200
Vin = VIH
VIS = VCC or GND
(Endpoints)
IS v 2.0 mA (Figures 3, 4)
4.5
70
85
120
Test Conditions
Maximum “ON” Resistance
Ron
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIH
VIS = 1/2 (VCC − GND)
IS v 2.0 mA
4.5
20
25
30
Ioff
Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL
VIO = VCC or GND
Switch Off (Figure 5)
5.5
0.1
0.5
1.0
A
Ion
Maximum On−Channel Leakage
Current, Any One Channel
Vin = VIH
VIS = VCC or GND
(Figure 6)
5.5
0.1
0.5
1.0
A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Guaranteed Limit
Parameter
Symbol
VCC
V
– 55 to
25°C
v 85°C
v 125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 10 and 11)
4.5
10
13
15
ns
tPLZ,
tPHZ
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 12 and 13)
4.5
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 12 and 13)
4.5
25
32
37
ns
ON/OFF Control Input
−
10
10
10
pF
Control Input = GND
Analog I/O
Feedthrough
−
−
35
1.0
35
1.0
35
1.0
C
Maximum Capacitance
Typical @ 25°C, VCC = 5.0 V
CPD
15
Power Dissipation Capacitance (Per Switch) (Figure 15)*
*Used to determine the no−load dynamic power consumption: PD = CPD VCC
2f
+ ICC VCC .
http://onsemi.com
4
pF
MC74HCT4066A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
Test Conditions
BW
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 7)
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter Reads – 3 dB
RL = 50 , CL = 10 pF
−
−
−
THD
Off−Channel Feedthrough Isolation
(Figure 8)
VCC
V
Limit*
25°C
54/74HCT
4.5
150
dB
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 , CL = 50 pF
4.5
−50
fin = 1.0 MHz, RL = 50 , CL = 10 pF
4.5
−40
Feedthrough Noise, Control to
Switch
(Figure 9)
Vin v 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 , CL = 50 pF
4.5
60
RL = 10 k, CL = 10 pF
4.5
30
Crosstalk Between Any Two
Switches
(Figure 14)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 , CL = 50 pF
4.5
–70
fin = 1.0 MHz, RL = 50 , CL = 10 pF
4.5
–80
Total Harmonic Distortion
(Figure 16)
fin = 1 kHz, RL = 10 k, CL = 50 pF
THD = THDMeasured − THDSource
VIS = 4.0 VPP sine wave
*Guaranteed limits not tested. Determined by design and verified by qualification.
http://onsemi.com
5
Unit
MHz
mVPP
dB
%
4.5
0.10
MC74HCT4066A
200
+25 °C
+125°C
−55°C
180
RON @ 4.5 V
160
140
120
100
80
60
40
20
0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 3. Typical On Resistance, VCC = 4.5 V
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
-
MINI COMPUTER
DC ANALYZER
+
VCC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
Figure 4. On Resistance Test Set−Up
VCC
VCC
VCC
VCC
14
GND
14
A
VCC
A
OFF
7
SELECTED
CONTROL
INPUT
N/C
ON
GND
VIL
7
Figure 5. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
SELECTED
CONTROL
INPUT
VIH
Figure 6. Maximum On Channel Leakage Current,
Test Set−Up
http://onsemi.com
6
MC74HCT4066A
VOS
VCC
VCC
VIS
14
fin
ON
0.1F
CL*
7
VOS
14
SELECTED
CONTROL
INPUT
fin
dB
METER
OFF
0.1F
CL*
RL
dB
METER
SELECTED
CONTROL
INPUT
VCC
7
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 7. Maximum On−Channel Bandwidth
Test Set−Up
VCC
VCC/2
Figure 8. Off−Channel Feedthrough Isolation,
Test Set−Up
VCC/2
14
RL
RL
OFF/ON
VOS
IS
VCC
CL*
3.0 V
GND
Vin ≤ 1 MHz
tr = tf = 6 ns
7
ANALOG IN
(VI)
tPLH
SELECTED
CONTROL
INPUT
CONTROL
ANALOG OUT
50%
GND
tPHL
50%
*Includes all probe and jig capacitance.
Figure 9. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
Figure 10. Propagation Delays, Analog In to
Analog Out
http://onsemi.com
7
MC74HCT4066A
VCC
tr
tf
14
ANALOG IN
ANALOG OUT
ON
TEST
POINT
VCC
90%
CONTROL
(VI)
Vm
10%
GND
CL*
7
SELECTED
CONTROL
INPUT
tPZL
tPLZ
HIGH
IMPEDANCE
50%
VCC
ANALOG
OUT
tPZH
10%
VOL
90%
VOH
tPHZ
50%
*Includes all probe and jig capacitance.
HIGH
IMPEDANCE
VI = GND to 3.0 V
Vm = 1.3 V
Figure 11. Propagation Delay Test Set−Up
Figure 12. Propagation Delay, ON/OFF Control
to Analog Out
VIS
1
POSITIONWHEN
TESTING tPHZ AND tPZH
VCC
2
POSITIONWHEN
TESTING tPLZ AND tPZL
1
14
RL
2
VCC
VCC
fin
TEST
POINT
ON/OFF
2
0.1 F
1 k
14
1
VOS
ON
OFF
VCC OR GND
CL*
RL
RL
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
CL*
VCC/2
RL
CL*
VCC/2
7
7
VCC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 13. Propagation Delay Test Set−Up
Figure 14. Crosstalk Between Any Two Switches,
Test Set−Up
VCC
A
VIS
VCC
14
N/C
OFF/ON
VOS
0.1 F
N/C
fin
ON
RL
7
CL*
TO
DISTORTION
METER
VCC/2
SELECTED
CONTROL
INPUT
7
SELECTED
CONTROL
INPUT
VCC
ON/OFF CONTROL
*Includes all probe and jig capacitance.
Figure 15. Power Dissipation Capacitance
Test Set−Up
Figure 16. Total Harmonic Distortion, Test Set−Up
http://onsemi.com
8
MC74HCT4066A
0
-10
FUNDAMENTAL FREQUENCY
-20
dBm
-30
-40
-50
DEVICE
-60
SOURCE
-70
-80
-90
1.0
3.0
2.0
FREQUENCY (kHz)
Figure 17. Plot, Harmonic Distortion
APPLICATION INFORMATION
analog signal of twelve volts peak−to−peak can be
controlled.
When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn−on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
MOSORB® (MOSORB is an acronym for high current
surge protectors). MOSORBs are fast turn−on devices
ideally suited for precise DC protection with no inherent
wear out mechanism.
Unused analog inputs/outputs may be left floating (not
connected). However, it is advisable to tie unused analog
inputs and outputs to VCC or GND through a low value
resistor. This minimizes crosstalk and feedthrough noise
that may be picked−up by the unused I/O pins.
The maximum analog voltage swings are determined by
the supply voltages VCC and GND. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below GND. In the example
below, the difference between VCC and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
VCC
VCC = 5 V
+5V
14
ANALOG I/O
ON
ANALOG O/I
Dx
+5V
SELECTED
CONTROL
INPUT
16
Dx
ON
0V
0V
VCC
Dx
VCC
OTHER CONTROL
INPUTS
Dx
SELECTED
CONTROL
INPUT
OTHER CONTROL
INPUTS
7
7
Figure 18. 5 V Application
Figure 19. Transient Suppressor Application
http://onsemi.com
9
MC74HCT4066A
+5 V
+5 V
14
ANALOG
SIGNALS
R*
R* R* R*
HC4066A
LSTTL/
NMOS
6
15
ANALOG
SIGNALS
HCT4066A
LSTTL/
NMOS
5
14
14
ANALOG
SIGNALS
ANALOG
SIGNALS
5
6
CONTROL
INPUTS
14
CONTROL
INPUTS
15
7
7
R* = 2 TO 10 k
a. Using Pull-Up Resistors with HC Device
b. Using HCT Buffer
Figure 20. LSTTL/NMOS to HCTMOS Interface
CHANNEL 4
1 OF 4
SWITCHES
CHANNEL 3
1 OF 4
SWITCHES
CHANNEL 2
1 OF 4
SWITCHES
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
INPUT
1 OF 4
SWITCHES
+
OUTPUT
LF356 OR
EQUIVALENT
0.01 F
1
2
3 4
CONTROL INPUTS
Figure 21. 4−Input Multiplexer
Figure 22. Sample/Hold Amplifier
http://onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
