EMIF06-VID01F2

EMIF06-VID01F2 6-line IPAD™, low capacitance EMI filter and ESD protection Features ■ High efficiency EMI filtering (-40 dB @ 900 MHz) ■ Low line capacitance suitable for high speed data bus ■ Low serial resistance for camera impedance adaptation ■ Lead-free package ■ Optimized PCB space occupation: 2.92 mm x 1.29 mm ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4) ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging ® Flip Chip (15 bumps) Figure 1. Pin layout (bump side) 9 8 I6 7 6 I5 I4 Gnd O6 Figure 2. 5 4 3 I3 I2 Gnd O5 O4 O3 2 1 I1 Gnd O2 A B O1 C Device configuration Complies with the following standards: R ■ IEC 61000-4-2 Level 4 on input pins – 15 kV (air discharge) – 8 kV (contact discharge) ■ MIL STD 883E - Method 3015-6 Class 3 Input Output R = 100Ω CLINE = 16pF typ. @ 3V Application Where EMI filtering in ESD sensitive equipment is required: Description ■ LCD and camera for mobile phones ■ Computers and printers ■ Communication systems The EMIF06-VID01F2 is a 6-line highly integrated array designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interference. ■ MCU board The EMIF06-VID01F2 Flip Chip packaging means the package size is equal to the die size. Additionally, this filter includes ESD protection circuitry which prevents damage to the protected device when subjected to ESD surges up to 15 kV. April 2008 Rev 2 1/7 www.st.com 7 Characteristics 1 EMIF06-VID01F2 Characteristics Table 1. Symbol Tj Absolute ratings (limiting values) Parameter and test conditions Unit 125 °C Maximum junction temperature Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage Cline VRM IR IRM IRM IR VRM VBR V Input capacitance per line Test conditions VBR IR = 1 mA IRM VRM = 3 V per line Cline VBR Series resistance between input and output Symbol R I Parameter VBR R 2/7 Value I = 10 mA VR = 3 V dc, 1 MHz VOSC = 30 mV Min. Typ. Max. Unit 6 8 10 V 500 nA 100 120 Ω 16 19 pF 80 EMIF06-VID01F2 Figure 3. Characteristics S21 (dB) attenuation measurement Figure 4. Analog crosstalk measurement 0 0 dB dB -10 -10 -20 -30 -20 -40 -50 -30 -60 -40 -70 -80 -50 -90 -100 -60 100k 1M 10M 100M 100k 1G 1M 10M Figure 5. 100M 1G f/Hz f/Hz ESD response to IEC 61000-4-2 Figure 6. (+15 kV air discharge) on one input (Vin) and on one output (Vout) ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input (Vin) and on one output (Vout) Input 10V/d Input 10V/d Output 10V/d Output 10V/d 200ns/d Figure 7. 200ns/d Junction capacitance versus reverse voltage applied (typical values) CLINE(pF) 28 26 24 22 20 18 16 14 12 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VLINE(V) 3/7 Ordering information scheme 2 EMIF06-VID01F2 Ordering information scheme Figure 8. Ordering information scheme EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 2: Lead-free, pitch = 500 µm, bump = 315 µm 3 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 9. Flip Chip package dimensions 1.29 mm ± 50 µm 650 µm ± 65 50 1µ m ±5 0 250 µm ± 50 210 µm 500 µm ± 50 435 µm ± 50 315 µm ± 50 210 µm 2.92 mm ± 50 µm 4/7 EMIF06-VID01F2 Package information Figure 10. Footprint recommendations Figure 11. Marking Dot, ST logo xx = marking z = manufacturing location yww = date code (y = year ww = week) Copper pad diameter: 250 µm recommended, 300 µm max E Solder stencil opening: 330 µm x x z y w w Solder mask opening recommendation: 340 µm min for 300 µm copper pad diameter Figure 12. Flip Chip tape and reel specification Dot identifying Pin A1 location Ø 1.5 ± 0.1 1.75 ± 0.1 4 ± 0.1 3.5 ± 0.1 1.52 ST E xxx yww 3.0 ST E xxx yww Note: ST E All dimensions in mm xxx yww 8 ± 0.3 0.73 ± 0.05 4 ± 0.1 User direction of unreeling More packing information is available in the application note AN1235: “Flip Chip: Package description and recommendations for use” AN1751: “EMI Filters: Recommendations and measurements” 5/7 Ordering information 4 Ordering information Table 3. 5 Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF06-VID01F2 GR Flip Chip 5.4 mg 5000 Tape and reel 7” Revision history Table 4. 6/7 EMIF06-VID01F2 Document revision history Date Revision Changes 15-Feb-2005 1 First issue. 28-Apr-2008 2 Added ECOPACK statement. Updated Figure 9, Figure 11, and Figure 12. Reformatted to current standards. EMIF06-VID01F2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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