STP190N55LF3

STP190N55LF3 N-channel 55 V, 2.9 mΩ, 120 A, TO-220 STripFET™ Power MOSFET Features Type VDSS RDS(on) max STP190N55LF3 55 V < 3.7 mΩ ■ Logic level drive ■ 100% avalanche tested ID PD 120 A 312 W 3 Application ■ 1 2 TO-220 Switching applications – Automotive Description Figure 1. This n-channel enhancement mode Power MOSFET is the latest refinement of STMicroelectronics' unique “single feature size” strip-based process, which has decreased the critical alignment steps, offering remarkable manufacturing reproducibility. The outcome is a transistor with extremely high packing density for low on resistance, rugged avalanche characteristics and low gate charge. Table 1. Internal schematic diagram Device summary Order code Marking Package Packaging STP190N55LF3 190N55LF3 TO-220 Tube November 2008 Rev 1 1/12 www.st.com 12 Contents STP190N55LF3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 STP190N55LF3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 55 V VDS Drain-source voltage (VGS=0) VGS Gate-Source voltage ± 18 V ID (1) Drain current (continuous) at TC = 25 °C 120 A ID (1) Drain current (continuous) at TC = 100 °C 120 A IDM (2) Drain current (pulsed) 480 A PTOT Total dissipation at TC = 25 °C 312 W Derating factor 2.08 W/°C Single pulse avalanche energy 1000 mJ -55 to 175 °C 175 °C Value Unit Thermal resistance junction-case max 0.48 °C/W Thermal resistance junction-ambient max 62.5 °C/W Maximum lead temperature for soldering purpose 300 °C EAS (3) Tstg Tj Storage temperature Max. operating junction temperature 1. Current limited by package 2. Pulse width limited by safe operating area 3. Starting Tj = 25 °C, ID = 60 A, VDD = 40 V Table 3. Symbol Rthj-case Rthj-a TL Thermal resistance Parameter 3/12 Electrical characteristics 2 STP190N55LF3 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS Static Parameter Drain-source breakdown Voltage Test conditions ID = 250 µA, VGS= 0 55 V VDS = Max rating, VDS = Max rating,Tc = 125 °C 10 100 µA µA Gate body leakage current (VDS = 0) VGS = ±18 V ±200 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA 2.5 V RDS(on) Static drain-source on resistance VGS= 10 V, ID= 30 A 3.7 4.5 mΩ mΩ IDSS Zero gate voltage drain current (VGS = 0) IGSS Table 5. Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd 1 2.9 3.3 VGS= 5 V, ID= 30 A Dynamic Parameter Test conditions Min Typ. Max. Unit Forward transconductance VDS = 15 V, ID=60 A 250 S Input capacitance Output capacitance Reverse transfer capacitance VDS = 25 V, f=1 MHz, VGS=0 6200 1450 80 pF pF pF Total gate charge Gate-source charge Gate-drain charge VGS = 5 V VDD= 44 V, ID = 120 A (see Figure 16) 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 4/12 Min. Typ. Max. Unit 60 20 30 80 nC nC nC STP190N55LF3 Electrical characteristics Table 6. Symbol Switching on/off (inductive load) Parameter Test conditions Min. Typ. Max. Unit VDD= 27.5 V, ID= 60 A, td(on) tr RG=4.7 Ω, VGS=10 V Turn-on delay time Rise time (see Figure 15), (see Figure 18) 20 40 ns ns 160 40 ns ns VDD= 27.5 V, ID= 60 A, td(off) tf Table 7. Symbol ISD Parameter VSD Forward on voltage IRRM Test conditions Min. Typ. Source-drain current Source-drain current Qrr (see Figure 15), (see Figure 18) Source drain diode ISDM trr RG=4.7 Ω, VGS=10 V Turn-off delay time Fall time (pulsed)(1) Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 120 A, VGS=0 ISD= 120 A, di/dt = 100A/µs, VDD= 35 V, Tj= 150 °C (see Figure 17) 50 90 3.6 Max. Unit 120 480 A A 1.5 V ns nC A 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 5/12 Electrical characteristics STP190N55LF3 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM01591v1 ID (A) 280tok K δ=0.5 s ai re n) s a DS(o i h t in xR on ma ati by r e d Op ite Lim 100 0.2 100µs 0.1 1ms 10 0.05 -1 10ms Tj=150°C Tc=25°C 10 0.02 1 Zth=k Rthj-c δ=tp/τ 0.01 Sinlge pulse Single pulse tp τ 0.1 0.1 Figure 4. ID (A) -2 10 1 100 10 -5 10 VDS(V) Output characteristics Figure 5. AM01592v1 VGS=10V -4 -3 10 10 -1 10 tp (s) Transfer characteristics AM01593v1 ID (A) 250 400 -2 10 VDS=10V 5V 350 200 300 4V 250 150 200 100 150 100 50 50 0 0 Figure 6. 6/12 3V 2 4 6 8 VDS(V) Normalized BVDSS vs temperature 0 0 Figure 7. 1 2 3 4 VGS(V) Static drain-source on resistance STP190N55LF3 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. AM01594v1 VGS (V) VDD=44V VGS=10V ID=120A 10 Capacitance variations AM01595v1 C (pF) 10000 Ciss 8 1000 Coss 6 100 4 Crss 10 2 0 0 20 40 60 80 100 120 Qg(nC) Figure 10. Normalized gate threshold voltage vs temperature 1 0 10 20 30 20 30 VDS(V) Figure 11. Normalized on resistance vs temperature AM01596v1 VGS(th) (norm) 1.00 0.80 0.60 0.40 0.20 -50 0 50 100 150 TJ(°C) Figure 12. Source-drain diode forward characteristics 7/12 Test circuit 3 STP190N55LF3 Test circuit Figure 13. Unclamped inductive load test circuit Figure 14. Unclamped inductive waveform VDD 12V 47kΩ 1kΩ 100nF 3.3 µF 2200 RL µF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 µF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 15. Switching times test circuit for resistive load A A D.U.T. FAST DIODE B B AM01469v1 Figure 16. Gate charge test circuit L A D G VD L=100µH S 3.3 µF B 25 Ω 1000 µF D VDD 2200 µF 3.3 µF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Test circuit for inductive load Figure 18. Switching time waveform switching and diode recovery times ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/12 0 10% AM01473v1 STP190N55LF3 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STP190N55LF3 TO-220 mechanical data mm inch Dim Min A b b1 c D D1 E e e1 F H1 J1 L L1 L20 L30 ∅P Q 10/12 Typ 4.40 0.61 1.14 0.48 15.25 Max Min 4.60 0.88 1.70 0.70 15.75 0.173 0.024 0.044 0.019 0.6 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 1.27 10 2.40 4.95 1.23 6.20 2.40 13 3.50 Max 0.181 0.034 0.066 0.027 0.62 0.050 16.40 28.90 3.75 2.65 Typ 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 3.85 2.95 0.147 0.104 0.151 0.116 STP190N55LF3 5 Revision history Revision history Table 8. Document revision history Date Revision 05-Nov-2008 1 Changes First release 11/12 STP190N55LF3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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