PIC16F8X
18-pin Flash/EEPROM 8-Bit Microcontrollers
Devices Included in this Data Sheet:
Pin Diagrams
PIC16F83
PIC16F84
PIC16CR83
PIC16CR84
Extended voltage range devices available
(PIC16LF8X, PIC16LCR8X)
PDIP, SOIC
High Performance RISC CPU Features:
• Only 35 single word instructions to learn
• All instructions single cycle except for program
branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Device
Program
Memory
(words)
Data
Data
RAM
EEPROM
(bytes) (bytes)
Max.
Freq
(MHz)
PIC16F83
512 Flash
36
64
PIC16F84
1 K Flash
68
64
10
PIC16CR83 512 ROM
36
64
10
PIC16CR84 1 K ROM
68
64
10
•
•
•
•
•
•
10
14-bit wide instructions
8-bit wide data path
15 special function hardware registers
Eight-level deep hardware stack
Direct, indirect and relative addressing modes
Four interrupt sources:
- External RB0/INT pin
- TMR0 timer overflow
- PORTB interrupt on change
- Data EEPROM write complete
• 1000 erase/write cycles Flash program memory
• 10,000,000 erase/write cycles EEPROM data memory
• EEPROM Data Retention > 40 years
Peripheral Features:
RA2
1
18
RA1
RA3
2
17
RA0
RA4/T0CKI
3
16
OSC1/CLKIN
MCLR
4
15
OSC2/CLKOUT
VSS
5
14
VDD
RB0/INT
6
13
RB7
RB1
7
12
RB6
RB2
8
11
RB5
RB3
9
10
RB4
PIC16F8X
PIC16CR8X
•
•
•
•
•
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) - via two
pins (ROM devices support only Data EEPROM
programming)
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
CMOS Flash/EEPROM Technology:
• Low-power, high-speed technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.0V to 6.0V
- Industrial:
2.0V to 6.0V
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 15 A typical @ 2V, 32 kHz
- < 1 A typical standby current @ 2V
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
1996-2013 Microchip Technology Inc.
DS30430D-page 1
PIC16F8X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU ...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support ................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information .............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: What’s New In This Data Sheet ................................................................................................................................. 114
Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
PIC16F8X Product Identification System ........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response form in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.
DS30430D-page 2
1996-2013 Microchip Technology Inc.
PIC16F8X
1.0
GENERAL DESCRIPTION
The PIC16F8X is a group in the PIC16CXX family of
low-cost, high-performance, CMOS, fully-static, 8-bit
microcontrollers. This group contains the following
devices:
•
•
•
•
PIC16F83
PIC16F84
PIC16CR83
PIC16CR84
All PIC® microcontrollers employ an advanced RISC
architecture. PIC16F8X devices have enhanced core
features, eight-level deep stack, and multiple internal
and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with a separate
8-bit wide data bus. The two stage instruction pipeline
allows all instructions to execute in a single cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set is
used to achieve a very high performance level.
PIC16F8X microcontrollers typically achieve a 2:1 code
compression and up to a 4:1 speed improvement (at 20
MHz) over other 8-bit microcontrollers in their class.
The PIC16F8X has up to 68 bytes of RAM, 64 bytes of
Data EEPROM memory, and 13 I/O pins. A timer/counter is also available.
The PIC16CXX family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake the chip from sleep through several
external and internal interrupts and resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
Table 1-1 lists the features of the PIC16F8X. A simplified block diagram of the PIC16F8X is shown in
Figure 3-1.
The PIC16F8X fits perfectly in applications ranging
from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
security devices and smart cards. The Flash/EEPROM
technology makes customization of application
programs (transmitter codes, motor speeds, receiver
frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
microcontroller series perfect for all applications with
space limitations. Low-cost, low-power, high
performance, ease-of-use and I/O flexibility make the
PIC16F8X very versatile even in areas where no
microcontroller use has been considered before
(e.g., timer functions; serial communication; capture,
compare and PWM functions; and co-processor
applications).
The serial in-system programming feature (via two
pins) offers flexibility of customizing the product after
complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
program the device with the current firmware before
shipping.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X devices can be easily ported to
PIC16F8X devices (Appendix B).
1.2
Development Support
The PIC16CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
The devices with Flash program memory allow the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).
1996-2013 Microchip Technology Inc.
DS30430D-page 3
PIC16F8X
TABLE 1-1
PIC16F8X FAMILY OF DEVICES
PIC16F83
Clock
Memory
Maximum Frequency
of Operation (MHz)
PIC16CR83
10
PIC16F84
10
PIC16CR84
10
Flash Program Memory
512
—
1K
—
EEPROM Program Memory
—
—
—
—
ROM Program Memory
—
512
—
1K
Data Memory (bytes)
36
36
68
68
Data EEPROM (bytes)
64
64
64
64
TMR0
TMR0
TMR0
TMR0
Interrupt Sources
4
4
4
4
I/O Pins
13
13
13
13
Voltage Range (Volts)
2.0-6.0
2.0-6.0
2.0-6.0
2.0-6.0
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
Peripherals Timer Module(s)
Features
10
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30430D-page 4
1996-2013 Microchip Technology Inc.
PIC16F8X
2.0
PIC16F8X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in this section. When placing
orders, please use the “PIC16F8X Product
Identification System” at the back of this data sheet to
specify the correct part number.
There are four device “types” as indicated in the device
number.
1.
2.
3.
4.
F, as in PIC16F84. These devices have Flash
program memory and operate over the standard
voltage range.
LF, as in PIC16LF84. These devices have Flash
program memory and operate over an extended
voltage range.
CR, as in PIC16CR83. These devices have
ROM program memory and operate over the
standard voltage range.
LCR, as in PIC16LCR84. These devices have
ROM program memory and operate over an
extended voltage range.
When discussing memory maps and other architectural
features, the use of F and CR also implies the LF and
LCR versions.
2.1
2.3
Serialized Quick-TurnaroundProduction (SQTP SM ) Devices
Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers
may
be
random,
pseudo-random
or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
For information on submitting a SQTP code, please
contact your Microchip Regional Sales Office.
2.4
ROM Devices
Some of Microchip’s devices have a corresponding
device where the program memory is a ROM. These
devices give a cost savings over Microchip’s traditional
user programmed devices (EPROM, EEPROM).
ROM devices (PIC16CR8X) do not allow serialization
information in the program memory space. The user
may program this information into the Data EEPROM.
For information on submitting a ROM code, please
contact your Microchip Regional Sales Office.
Flash Devices
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed incircuit, or by device programmers, such as Microchip's
PICSTART® Plus or PRO MATE® II programmers.
2.2
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices have all Flash
locations and configuration options already programmed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available.
For information on submitting a QTP code, please
contact your Microchip Regional Sales Office.
1996-2013 Microchip Technology Inc.
DS30430D-page 5
PIC16F8X
NOTES:
DS30430D-page 6
1996-2013 Microchip Technology Inc.
PIC16F8X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CXX uses a Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC16CXX opcodes are 14-bits wide, enabling single
word instructions. The full 14-bit wide program memory
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle except for program branches.
The PIC16F83 and PIC16CR83 address 512 x 14 of
program memory, and the PIC16F84 and PIC16CR84
address 1K x 14 program memory. All program memory is internal.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. An orthogonal (symmetrical)
instruction set makes it possible to carry out any operation on any register using any addressing mode. This
symmetrical nature and lack of ‘special optimal
situations’ make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.
1996-2013 Microchip Technology Inc.
DS30430D-page 7
PIC16F8X
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
data in the working register and any register file.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register), and the other operand is a file register or
an immediate constant. In single operand instructions,
the operand is either the W register or a file register.
FIGURE 3-1:
PIC16F8X BLOCK DIAGRAM
Data Bus
13
8
Program Counter
Flash/ROM
Program
Memory
PIC16F83/CR83
512 x 14
PIC16F84/CR84
1K x 14
Program
Bus
A simplified block diagram for the PIC16F8X is shown
in Figure 3-1, its corresponding pin description is
shown in Table 3-1.
8 Level Stack
(13-bit)
14
EEPROM Data Memory
RAM
File Registers
PIC16F83/CR83
36 x 8
PIC16F84/CR84
68 x 8
7
EEDATA
RAM Addr
EEPROM
Data Memory
64 x 8
EEADR
Addr Mux
Instruction reg
7
Direct Addr
5
TMR0
Indirect
Addr
FSR reg
RA4/T0CKI
STATUS reg
8
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
Oscillator
Start-up Timer
8
ALU
Power-on
Reset
Watchdog
Timer
I/O Ports
RA3:RA0
W reg
RB7:RB1
RB0/INT
OSC2/CLKOUT
OSC1/CLKIN
DS30430D-page 8
MCLR
VDD, VSS
1996-2013 Microchip Technology Inc.
PIC16F8X
TABLE 3-1
PIC16F8X PINOUT DESCRIPTION
DIP
No.
SOIC
No.
I/O/P
Type
OSC1/CLKIN
16
16
I
OSC2/CLKOUT
15
15
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR
4
4
I/P
ST
Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
Pin Name
Buffer
Type
Description
ST/CMOS (3) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA0
17
17
I/O
TTL
RA1
18
18
I/O
TTL
RA2
1
1
I/O
TTL
RA3
2
2
I/O
TTL
RA4/T0CKI
3
3
I/O
ST
Can also be selected to be the clock input to the TMR0 timer/
counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT
6
6
I/O
TTL/ST (1)
RB1
7
7
I/O
TTL
RB2
8
8
I/O
TTL
RB0/INT can also be selected as an external interrupt pin.
RB3
9
9
I/O
TTL
RB4
10
10
I/O
TTL
Interrupt on change pin.
RB5
11
11
I/O
TTL
Interrupt on change pin.
RB6
12
12
I/O
TTL/ST (2)
(2)
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
RB7
13
13
I/O
VSS
5
5
P
—
Ground reference for logic and I/O pins.
VDD
14
14
P
—
Positive supply for logic and I/O pins.
Legend: I= input
O = output
I/O = Input/Output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1996-2013 Microchip Technology Inc.
DS30430D-page 9
PIC16F8X
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
PC+1
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30430D-page 10
1996-2013 Microchip Technology Inc.
PIC16F8X
MEMORY ORGANIZATION
There are two memory blocks in the PIC16F8X. These
are the program memory and the data memory. Each
block has its own bus, so that access to each block can
occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK - PIC16F83/CR83
PC
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
User Memory
Space
4.0
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
1FFh
Program Memory Organization
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16F83 and PIC16CR83, the first 512 x 14
(0000h-01FFh)
are
physically
implemented
(Figure 4-1). For the PIC16F84 and PIC16CR84, the
first 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-2). Accessing a location above the
physically implemented address will cause a wraparound. For example, for the PIC16F84 locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
1FFFh
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK - PIC16F84/CR84
PC
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
User Memory
Space
The reset vector is at 0000h and the interrupt vector is
at 0004h.
3FFh
1FFFh
1996-2013 Microchip Technology Inc.
DS30430D-page 11
PIC16F8X
4.2
Data Memory Organization
4.2.1
GENERAL PURPOSE REGISTER FILE
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
accessed either directly or indirectly through the FSR
(Section 4.5).
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 4-1 and Figure 4-2 show the data memory map
organization.
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR.
Instructions MOVWF and MOVF can move values from
the W register to any location in the register file (“F”),
and vice-versa.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-1, Figure 4-2
and Table 4-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are General Purpose Registers implemented as static RAM.
DS30430D-page 12
1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 4-1:
REGISTER FILE MAP PIC16F83/CR83
File Address
FIGURE 4-2:
REGISTER FILE MAP PIC16F84/CR84
File Address
File Address
80h
00h
Indirect addr.(1)
OPTION
81h
01h
TMR0
OPTION
81h
PCL
82h
02h
PCL
PCL
82h
STATUS
STATUS
83h
03h
STATUS
STATUS
83h
FSR
FSR
84h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
06h
PORTB
TRISB
86h
87h
07h
08h
EEDATA
EECON1
88h
08h
EEDATA
EECON1
88h
09h
EEADR
EECON2(1)
89h
09h
EEADR
EECON2(1)
89h
0Ah
PCLATH
PCLATH
8Ah
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
0Bh
INTCON
INTCON
8Bh
8Ch
0Ch
00h
Indirect addr.(1)
01h
TMR0
02h
PCL
03h
04h
Indirect addr.(1)
07h
0Ch
36
General
Purpose
registers
(SRAM)
Mapped
(accesses)
in Bank 0
2Fh
30h
File Address
8Ch
Mapped
(accesses)
in Bank 0
4Fh
50h
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
1996-2013 Microchip Technology Inc.
80h
87h
68
General
Purpose
registers
(SRAM)
AFh
B0h
Indirect addr.(1)
CFh
D0h
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
DS30430D-page 13
PIC16F8X
TABLE 4-1
Address
REGISTER FILE SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Bank 0
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ----
---- ----
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
02h
PCL
Low order 8 bits of the Program Counter (PC)
0000 0000
0000 0000
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
(2)
TO
03h
STATUS
04h
FSR
05h
PORTA
—
—
—
RA4/T0CKI
RA3
RA2
RA1
RA0
---x xxxx
---u uuuu
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
xxxx xxxx
uuuu uuuu
07h
IRP
RP1
RP0
PD
Z
DC
C
Indirect data memory address pointer 0
Unimplemented location, read as '0'
---- ----
---- ----
xxxx xxxx
uuuu uuuu
08h
EEDATA
EEPROM data register
09h
EEADR
EEPROM address register
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
EEIE
T0IE
xxxx xxxx
uuuu uuuu
---0 0000
---0 0000
0000 000x
0000 000u
---- ----
---- ----
1111 1111
1111 1111
0000 0000
0000 0000
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
---1 1111
---1 1111
PORTB data direction register
1111 1111
1111 1111
Unimplemented location, read as '0'
---- ----
---- ----
---0 x000
---0 q000
Write buffer for upper 5 bits of the PC (1)
INTE
RBIE
T0IF
INTF
RBIF
Bank 1
80h
INDF
81h
OPTION_
REG
82h
PCL
83h
STATUS (2)
84h
FSR
85h
TRISA
86h
TRISB
87h
88h
EECON1
Uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Low order 8 bits of Program Counter (PC)
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer 0
—
—
—
—
—
—
89h
EECON2
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
EEIE
T0IE
PORTA data direction register
EEIF
WRERR
WREN
WR
RD
EEPROM control register 2 (not a physical register)
Write buffer for upper 5 bits of the PC (1)
INTE
RBIE
T0IF
INTF
RBIF
---- ----
---- ----
---0 0000
---0 0000
0000 000x
0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430D-page 14
1996-2013 Microchip Technology Inc.
PIC16F8X
4.2.2.1
STATUS REGISTER
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destination for any instruction. If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
FIGURE 4-1:
R/W-0
IRP
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 9-2)
because these instructions do not affect any status bit.
Note 1: The IRP and RP1 bits (STATUS) are
not used by the PIC16F8X and should be
programmed as cleared. Use of these bits
as general purpose R/W bits is NOT
recommended, since this may affect
upward compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Note 3: When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
bit7
bit 7:
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (for ADDWF and ADDLW instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low
order bit of the source register.
1996-2013 Microchip Technology Inc.
DS30430D-page 15
PIC16F8X
4.2.2.2
OPTION_REG REGISTER
Note:
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-1:
When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
prescaler assignment.
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS30430D-page 16
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1996-2013 Microchip Technology Inc.
PIC16F8X
4.2.2.3
INTCON REGISTER
Note:
The INTCON register is a readable and writable
register which contains the various enable bits for all
interrupt sources.
FIGURE 4-1:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6:
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1:
INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1996-2013 Microchip Technology Inc.
DS30430D-page 17
PIC16F8X
4.3
Program Counter: PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte is the PCL register, which is a readable and
writable register. The high byte of the PC (PC) is
not directly readable nor writable and comes from the
PCLATH register. The PCLATH (PC latch high) register
is a holding register for PC. The contents of
PCLATH are transferred to the upper byte of the
program counter when the PC is loaded with a new
value. This occurs during a CALL, GOTO or a write to
PCL. The high bits of PC are loaded from PCLATH as
shown in Figure 4-1.
FIGURE 4-1:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
12
PCL
8 7
0
INST with PCL
as dest
PC
8
PCLATH
5
ALU result
manipulation of the PCLATH is not required for
the return instructions (which “pops” the PC from the
stack).
Note:
4.4
The PIC16F8X ignores the PCLATH
bits, which are used for program memory
pages 1, 2 and 3 (0800h - 1FFFh). The
use of PCLATH as general purpose
R/W bits is not recommended since this
may affect upward compatibility with
future products.
Stack
The PIC16FXX has an 8 deep x 13-bit wide hardware
stack (Figure 4-1). The stack space is not part of either
program or data space and the stack pointer is not
readable or writable.
The entire 13-bit PC is “pushed” onto the stack when a
CALL instruction is executed or an interrupt is acknowledged. The stack is “popped” in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a push or a pop operation.
PCLATH
Note:
PCH
12 11 10
PCL
8 7
0
PC
GOTO, CALL
2
PCLATH
11
Opcode
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256 word block). Refer to the application
note “Implementing a Table Read” (AN556).
4.3.2
There are no instruction mnemonics
called push or pop. These are actions that
occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
The stack operates as a circular buffer. That is, after the
stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
If the stack is effectively popped nine times, the PC
value is the same as the value from the first pop.
Note:
There are no status bits to indicate stack
overflow or stack underflow conditions.
PROGRAM MEMORY PAGING
The PIC16F83 and PIC16CR83 have 512 words of program memory. The PIC16F84 and PIC16CR84 have
1K of program memory. The CALL and GOTO instructions have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. For future PIC16F8X program memory
expansion, there must be another two bits to specify
the program memory page. These paging bits come
from the PCLATH bits (Figure 4-1). When doing a
CALL or a GOTO instruction, the user must ensure that
these page bits (PCLATH) are programmed to
the desired program memory page. If a CALL instruction (or interrupt) is executed, the entire 13-bit PC is
“pushed” onto the stack (see next section). Therefore,
DS30430D-page 18
1996-2013 Microchip Technology Inc.
PIC16F8X
4.5
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
Indirect Addressing; INDF and FSR
Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 4-2:
EXAMPLE 4-1:
NEXT
INDIRECT ADDRESSING
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
:
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS), as
shown in Figure 4-1. However, IRP is not used in the
PIC16F8X.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 4-1:
DIRECT/INDIRECT ADDRESSING
Indirect Addressing
Direct Addressing
RP1 RP0
bank select
6
from opcode
0
IRP
location select
7
bank select
00
01
10
11
not used
not used
Bank 2
Bank 3
(FSR)
0
location select
00h
00h
0Bh
0Ch
Data
Memory (3)
Addresses
map back
to Bank 0
2Fh (1)
30h (1)
4Fh (2)
50h (2)
7Fh
7Fh
Bank 0
Bank 1
Note 1: PIC16F83 and PIC16CR83 devices.
2: PIC16F84 and PIC16CR84 devices
3: For memory map detail see Figure 4-1.
1996-2013 Microchip Technology Inc.
DS30430D-page 19
PIC16F8X
NOTES:
DS30430D-page 20
1996-2013 Microchip Technology Inc.
PIC16F8X
5.0
I/O PORTS
EXAMPLE 5-1:
INITIALIZING PORTA
CLRF
PORTA
BSF
MOVLW
STATUS, RP0
0x0F
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
MOVWF
TRISA
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
FIGURE 5-2:
The PIC16F8X has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate function for other features on the device.
5.1
;
;
;
;
;
;
;
;
;
;
;
PORTA and TRISA Registers
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
Data
bus
WR
PORT
Initialize PORTA by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA as inputs
RA4 as outputs
TRISA are always
read as '0'.
BLOCK DIAGRAM OF PIN RA4
D
Q
CK
Q
N
Data Latch
VSS
WR
TRIS
The RA4 pin is multiplexed with the TMR0 clock input.
D
Q
CK
Q
Schmitt
Trigger
input
buffer
TRIS Latch
FIGURE 5-1:
BLOCK DIAGRAM OF PINS
RA3:RA0
Data
bus
RD TRIS
D
WR
Port
RA4 pin
Q
Q
VDD
CK
Q
D
EN
EN
P
RD PORT
Data Latch
N
D
WR
TRIS
I/O pin
Q
VSS
CK
TMR0 clock input
Note: I/O pin has protection diodes to VSS only.
Q
TRIS Latch
TTL
input
buffer
RD TRIS
Q
D
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
1996-2013 Microchip Technology Inc.
DS30430D-page 21
PIC16F8X
TABLE 5-1
PORTA FUNCTIONS
Name
Bit0
Buffer Type
RA0
RA1
RA2
RA3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Function
Input/output
Input/output
Input/output
Input/output
Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
05h
PORTA
—
—
—
RA4/T0CKI
RA3
RA2
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
Bit 0
Value on
Power-on
Reset
Value on all
other resets
RA1
RA0
---x xxxx
---u uuuu
TRISA1
TRISA0
---1 1111
---1 1111
Bit 1
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30430D-page 22
1996-2013 Microchip Technology Inc.
PIC16F8X
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding
output driver in a hi-impedance mode. A '0' on any bit
in the TRISB register puts the contents of the output
latch on the selected pin(s).
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION_REG) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of the pins are
OR’ed together to generate the RB port
change interrupt.
FIGURE 5-3:
BLOCK DIAGRAM OF PINS
RB7:RB4
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Read (or write) PORTB. This will end the mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
Note 1: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY (4/fOSC) wide.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-4:
BLOCK DIAGRAM OF PINS
RB3:RB0
VDD
RBPU(1)
VDD
RBPU(1)
Data bus
weak
P pull-up
Data Latch
D
WR Port
Q
I/O
pin(2)
CK
Data bus
WR Port
WR TRIS
WR TRIS
Q
Data Latch
D
Q
I/O
pin(2)
CK
TRIS Latch
D
Q
TRIS Latch
D
weak
P pull-up
TTL
Input
Buffer
CK
TTL
Input
Buffer
CK
RD TRIS
Q
Latch
RD TRIS
Q
RD Port
D
RD Port
D
EN
EN
Set RBIF
RB0/INT
From other
RB7:RB4 pins
Q
Schmitt Trigger
Buffer
D
RD Port
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
EN
2: I/O pins have diode protection to VDD and VSS.
RD Port
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
1996-2013 Microchip Technology Inc.
DS30430D-page 23
PIC16F8X
EXAMPLE 5-1:
INITIALIZING PORTB
CLRF
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
TABLE 5-3
Name
RB0/INT
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
PORTB FUNCTIONS
Bit
Buffer Type
bit0
TTL/ST(1)
I/O Consistency Function
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
RB6
bit6
TTL/ST(2)
weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change). Internal software programmable
RB7
bit7
TTL/ST(2)
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4
Address
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
xxxx xxxx
uuuu uuuu
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
81h
OPTION_
REG
PS0
1111 1111
1111 1111
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30430D-page 24
1996-2013 Microchip Technology Inc.
PIC16F8X
5.3
I/O Programming Considerations
5.3.1
BI-DIRECTIONAL I/O PORTS
5.3.2
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However, if
bit0 is switched into output mode later on, the content
of the data latch is unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output current may damage the chip.
FIGURE 5-5:
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-5). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such that the pin voltage stabilizes (load dependent)
before the next instruction which causes that file to be
read into the CPU is executed. Otherwise, the previous
state of that pin may be read into the CPU rather than
the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF, etc.) on
an I/O port.
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORT settings: PORTB Inputs
;
PORTB Outputs
;PORTB have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------BCF PORTB, 7
; 01pp ppp
11pp ppp
BCF PORTB, 6
; 10pp ppp
11pp ppp
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp ppp
11pp ppp
BCF TRISB, 6
; 10pp ppp
10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
SUCCESSIVE OPERATIONS ON I/O
PORTS
PC
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
Note:
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
1996-2013 Microchip Technology Inc.
MOVF PORTB,W
Therefore, at higher clock frequencies,
a write followed by a read may be problematic.
DS30430D-page 25
PIC16F8X
NOTES:
DS30430D-page 26
1996-2013 Microchip Technology Inc.
PIC16F8X
6.0
TIMER0 MODULE AND TMR0
REGISTER
edge select bit, T0SE (OPTION_REG). Clearing bit
T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
controlled, in software, by control bit PSA
(OPTION_REG). Clearing bit PSA will assign the
prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
6.1
Timer mode is selected by clearing the T0CS bit
(OPTION_REG). In timer mode, the Timer0 module (Figure 6-1) will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two cycles
(Figure 6-2 and Figure 6-3). The user can work around
this by writing an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
the T0IF bit (INTCON). The interrupt can be
masked by clearing enable bit T0IE (INTCON). The
T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
the processor from SLEEP since the timer is shut off
during SLEEP.
Counter mode is selected by setting the T0CS bit
(OPTION_REG). In this mode TMR0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the T0 source
FIGURE 6-1:
TMR0 Interrupt
TMR0 BLOCK DIAGRAM
Data bus
FOSC/4
0
PSout
1
Sync with
Internal
clocks
1
RA4/T0CKI
pin
Programmable
Prescaler
8
0
TMR0 register
PSout
(2 cycle delay)
T0SE
3
PS2, PS1, PS0
Set bit T0IF
on Overflow
PSA
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
TMR0
PC
MOVWF TMR0
Instruction
Fetch
T0
T0+1
Instruction
Executed
1996-2013 Microchip Technology Inc.
PC+1
PC+2
PC+3
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0 + 1
NT0+2
T0
Read TMR0
reads NT0 + 2
DS30430D-page 27
PIC16F8X
FIGURE 6-3:
TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
PC+3
T0+1
T0
TMR0
PC+2
Instruction
Execute
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
FIGURE 6-4:
PC+4
MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TMR0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
T0IF bit 4
(INTCON)
1
FFh
00h
01h
02h
1
GIE bit
(INTCON)
Interrupt Latency(2)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30430D-page 28
1996-2013 Microchip Technology Inc.
PIC16F8X
6.2
Using TMR0 with External Clock
6.2.2
TMR0 INCREMENT DELAY
When an external clock input is used for TMR0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing
of
the
TMR0
register
after
synchronization.
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
Module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
6.2.1
6.3
EXTERNAL CLOCK SYNCHRONIZATION
Prescaler
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of pin RA4/T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (plus a small RC delay) and low
for at least 2Tosc (plus a small RC delay). Refer to the
electrical specification of the desired device.
An 8-bit counter is available as a prescaler for the
Timer0 Module, or as a postscaler for the Watchdog
Timer (Figure 6-6). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 Module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 Module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
When a prescaler is used, the external clock input is
divided by an asynchronous ripple counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4Tosc (plus a small RC delay) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the AC Electrical
Specifications of the desired device.
The PSA and PS2:PS0 bits (OPTION_REG)
determine the prescaler assignment and prescale ratio.
1996-2013 Microchip Technology Inc.
When assigned to the Timer0 Module, all instructions
writing to the Timer0 Module (e.g., CLRF 1, MOVWF
1, BSF 1,x ....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
DS30430D-page 29
PIC16F8X
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Ext. Clock Input or
Prescaler Out (Note 2)
(Note 3)
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
FIGURE 6-6:
BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
Data Bus
CLKOUT (= Fosc/4)
0
RA4/T0CKI
pin
M
U
X
8
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 register
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set bit T0IF
on overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.
DS30430D-page 30
1996-2013 Microchip Technology Inc.
PIC16F8X
6.3.1
SWITCHING PRESCALER ASSIGNMENT
EXAMPLE 6-1:
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution).
Note:
To avoid an unintended device RESET, the
following
instruction
sequence
(Example 6-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be taken even if the WDT is disabled. To
change prescaler from the WDT to the
Timer0 module use the sequence shown in
Example 6-2.
TABLE 6-1
Address
CHANGING PRESCALER
(TIMER0WDT)
BCF
CLRF
STATUS, RP0
TMR0
BSF
CLRWDT
MOVLW
MOVWF
BCF
STATUS, RP0
b'xxxx1xxx'
OPTION_REG
STATUS, RP0
EXAMPLE 6-2:
;Bank 0
;Clear TMR0
; and Prescaler
;Bank 1
;Clears WDT
;Select new
; prescale value
;Bank 0
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION_REG
STATUS, RP0
;Clear WDT and
; prescaler
;Bank 1
;Select TMR0, new
; prescale value
’ and clock source
;
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
Value on
Power-on
Reset
Value on all
other resets
xxxx xxxx
uuuu uuuu
01h
TMR0
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 0000
81h
OPTION_
REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
1996-2013 Microchip Technology Inc.
DS30430D-page 31
PIC16F8X
NOTES:
DS30430D-page 32
1996-2013 Microchip Technology Inc.
PIC16F8X
7.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
•
•
•
•
EECON1
EECON2
EEDATA
EEADR
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
7.1
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16F8X devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
FIGURE 7-1:
EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 64 bytes of
data EEPROM are implemented.
The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
address is in the 64 byte memory space.
EECON1 REGISTER (ADDRESS 88h)
U
U
U
R/W-0
R/W-x
R/W-0
R/S-0
R/S-x
—
—
—
EEIF
WRERR
WREN
WR
RD
bit7
bit0
R
W
S
U
= Readable bit
= Writable bit
= Settable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
1996-2013 Microchip Technology Inc.
DS30430D-page 33
PIC16F8X
EECON1 and EECON2 Registers
EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are nonexistent and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The data and
address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It
must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
7.3
Reading the EEPROM Data Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 7-1:
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
DATA EEPROM READ
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
DS30430D-page 34
;
;
;
;
;
;
;
Bank 0
7.4
Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 7-1:
Required
Sequence
7.2
DATA EEPROM WRITE
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
STATUS, RP0
INTCON, GIE
EECON1, WREN
55h
EECON2
AAh
EECON2
EECON1,WR
BSF
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
Bank 1
Disable INTs.
Enable Write
Write 55h
Write AAh
Set WR bit
begin write
Enable INTs.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
Address to read
Bank 1
EE Read
Bank 0
W = EEDATA
1996-2013 Microchip Technology Inc.
PIC16F8X
7.5
Write Verify
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO WRITE_ERR
:
:
Depending on the application, good programming practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
7.6
WRITE VERIFY
BCF
:
:
MOVF
BSF
STATUS, RP0 ;
;
;
EEDATA, W
;
STATUS, RP0 ;
BSF
EECON1, RD
Bank 0
Any code can go here
7.7
Must be in Bank 0
Bank 1
Data EEPROM Operation during Code
Protect
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data EEPROM.
; YES, Read the
;
value written
STATUS, RP0 ; Bank 0
BCF
;
; Is the value written (in W reg) and
;
read (in EEDATA) the same?
;
Address
Protection Against Spurious Writes
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
READ
TABLE 7-1
Is difference 0?
NO, Write error
YES, Good write
Continue program
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
Generally the EEPROM write failure will be a bit which
was written as a '1', but reads back as a '0' (due to
leakage off the bit).
EXAMPLE 7-1:
;
;
;
;
;
For ROM devices, there are two code protection bits
(Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
08h
EEDATA
EEPROM data register
xxxx xxxx
uuuu uuuu
09h
EEADR
EEPROM address register
xxxx xxxx
uuuu uuuu
88h
EECON1
---0 x000
---0 q000
89h
EECON2
---- ----
---- ----
—
—
—
EEPROM control register 2
EEIF
WRERR
WREN
WR
RD
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
used by Data EEPROM.
1996-2013 Microchip Technology Inc.
DS30430D-page 35
PIC16F8X
NOTES:
DS30430D-page 36
1996-2013 Microchip Technology Inc.
PIC16F8X
8.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16F8X has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
The PIC16F8X has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
design keeps the device in reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
1996-2013 Microchip Technology Inc.
DS30430D-page 37
PIC16F8X
8.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
FIGURE 8-1:
Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
be accessed during programming.
To find out how to program the PIC16C84, refer to
PIC16C84 EEPROM Memory Programming Specification (DS30189).
CONFIGURATION WORD - PIC16CR83 AND PIC16CR84
R-u
R-u
R-u
R-u
R-u
R-u
R/P-u
R-u
R-u
R-u
CP
CP
CP
CP
CP
CP
DP
CP
CP
CP
bit13
R-u
R-u
R-u
R-u
PWRTE WDTE FOSC1 FOSC0
bit0
R = Readable bit
P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 13:8 CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 7
DP: Data Memory Code Protection bit
1 = Code protection off
0 = Data memory is code protected
bit 6:4
CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 3
PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
DS30430D-page 38
1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-2:
CONFIGURATION WORD - PIC16F83 AND PIC16F84
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
CP
CP
CP
CP
CP
CP
CP
CP
R/P-u
R/P-u
CP
CP
R/P-u
R/P-u
R/P-u
R/P-u
PWRTE WDTE FOSC1 FOSC0
bit13
bit0
R = Readable bit
P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 13:4 CP: Code Protection bit
1 = Code protection off
0 = All memory is code protected
bit 3
PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
8.2
Oscillator Configurations
8.2.1
OSCILLATOR TYPES
The PIC16F8X can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP
XT
HS
RC
8.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 8-3).
FIGURE 8-3:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
OSC2
RS(2)
C2(1)
Note1:
2:
3:
To
internal
logic
SLEEP
PIC16FXX
See Table 8-1 for recommended values of
C1 and C2.
A series resistor (RS) may be required for
AT strip cut crystals.
RF varies with the crystal chosen.
The PIC16F8X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the device
can have an external clock source to drive the
OSC1/CLKIN pin (Figure 8-4).
1996-2013 Microchip Technology Inc.
DS30430D-page 39
PIC16F8X
FIGURE 8-4:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC16FXX
Open
TABLE 8-1
OSC2
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Tested:
Mode
Freq
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
HS
Note :
OSC1/C1
OSC2/C2
47 - 100 pF 47 - 100 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
Recommended values of C1 and C2 are identical to
the ranges tested table.
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for the
appropriate values of external components.
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
1.0 MHz
2.0 MHz
4.0 MHz
10.0 MHz
8.2.3
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 KHz
ECS ECS-10-13-2
ECS ECS-20-S-2
ECS ECS-40-S-4
ECS ECS-100-S-4
20 PPM
20 PPM
20 PPM
50 PPM
50 PPM
50 PPM
50 PPM
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits are
available; one with series resonance, and one with
parallel resonance.
Figure 8-5 shows a parallel resonant oscillator circuit.
The circuit is designed to use the fundamental
frequency of the crystal. The 74AS04 inverter performs
the 180-degree phase shift that a parallel oscillator
requires. The 4.7 k resistor provides negative
feedback for stability. The 10 k potentiometer biases
the 74AS04 in the linear region. This could be used for
external oscillator designs.
Resonators Tested:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
10.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA10.00MTZ
0.3%
0.5%
0.5%
0.5%
0.5%
FIGURE 8-5:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
None of the resonators had built-in capacitors.
4.7k
TABLE 8-2
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Mode
Freq
OSC1/C1
OSC2/C2
LP
32 kHz
200 kHz
100 kHz
2 MHz
4 MHz
4 MHz
10 MHz
68 - 100 pF
15 - 33 pF
100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
68 - 100 pF
15 - 33 pF
100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
XT
HS
Note :
Higher capacitance increases the stability of
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal
manufacturer for appropriate values of external
components.
PIC16FXX
74AS04
CLKIN
74AS04
10k
XTAL
10k
20 pF
20 pF
Figure 8-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift. The 330 k resistors provide
the negative feedback to bias the inverters in their
linear region.
For VDD > 4.5V, C1 = C2 30 pF is recommended.
DS30430D-page 40
1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-6:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
FIGURE 8-7:
RC OSCILLATOR MODE
VDD
Rext
330 k
330 k
74AS04
74AS04
To Other
Devices
PIC16FXX
Cext
74AS04
CLKIN
Fosc/4
Recommended values:
XTAL
Note:
RC OSCILLATOR
For timing insensitive applications the RC device option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) values, capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types also affects the oscillation frequency, especially
for low Cext values. The user needs to take into
account variation due to tolerance of the external
R and C components. Figure 8-7 shows how an R/C
combination is connected to the PIC16F8X. For Rext
values below 4 k, the oscillator operation may
become unstable, or stop completely. For very high
Rext values (e.g., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend keeping Rext between 5 k and 100 k.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
See the electrical specification section for RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance has a greater affect on
RC frequency).
PIC16FXX
VSS
0.1F
8.2.4
Internal
clock
OSC1
8.3
OSC2/CLKOUT
5 k Rext 100 k
Cext > 20pF
When the device oscillator is in RC mode,
do not drive the OSC1 pin with an external
clock or you may damage the device.
Reset
The PIC16F8X differentiates between various kinds
of reset:
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Figure 8-8 shows a simplified block diagram of the
on-chip reset circuit. The MCLR reset path has a noise
filter to ignore small pulses. The electrical specifications state the pulse width requirements for the MCLR
pin.
Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
“reset state” on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
They are not affected by a WDT reset during SLEEP,
since this reset is viewed as the resumption of normal
operation.
Table 8-3 gives a description of reset conditions for the
program counter (PC) and the STATUS register.
Table 8-4 gives a full description of reset states for all
registers.
The TO and PD bits are set or cleared differently in different reset situations (Section 8.7). These bits are
used in software to determine the nature of the reset.
See the electrical specification section for variation of
oscillator frequency due to VDD for given Rext/Cext
values as well as frequency variation due to
operating temperature.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (see Figure 3-2
for waveform).
1996-2013 Microchip Technology Inc.
DS30430D-page 41
PIC16F8X
FIGURE 8-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
SLEEP
WDT
Time_Out
Reset
VDD rise
detect
Power_on_Reset
S
10-bit Ripple counter
R
VDD
OST/PWRT
OST
Chip_Reset
Q
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1)
10-bit Ripple counter
Enable PWRT
Note 1: This is a separate oscillator from the
RC oscillator of the CLKIN pin.
DS30430D-page 42
See Table 8-5
Enable OST
1996-2013 Microchip Technology Inc.
PIC16F8X
TABLE 8-3
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Program Counter
Condition
STATUS Register
Power-on Reset
000h
0001 1xxx
MCLR Reset during normal operation
000h
000u uuuu
MCLR Reset during SLEEP
000h
0001 0uuu
WDT Reset (during normal operation)
000h
0000 1uuu
WDT Wake-up
PC + 1
Interrupt wake-up from SLEEP
PC + 1
uuu0 0uuu
(1)
uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-4
Register
W
RESET CONDITIONS FOR ALL REGISTERS
Address
Power-on Reset
MCLR Reset during:
– normal operation
– SLEEP
WDT Reset during normal operation
Wake-up from SLEEP:
– through interrupt
– through WDT Time-out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h
---- ----
---- ----
---- ----
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000h
0000h
STATUS
03h
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
04h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
---x xxxx
---u uuuu
---u uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATA
08h
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
09h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
0Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh
0000 000x
0000 000u
uuuu uuuu(1)
INDF
80h
---- ----
---- ----
---- ----
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
PCL
82h
0000h
0000h
PC + 1(2)
PC + 1
(3)
uuuq quuu(3)
STATUS
83h
0001 1xxx
000q quuu
FSR
84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
TRISA
85h
---1 1111
---1 1111
---u uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
EECON1
88h
---0 x000
---0 q000
---0 uuuu
EECON2
89h
---- ----
---- ----
---- ----
PCLATH
8Ah
---0 0000
---0 0000
---u uuuu
INTCON
8Bh
0000 000x
0000 000u
uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0',
q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 8-3 lists the reset value for each specific condition.
1996-2013 Microchip Technology Inc.
DS30430D-page 43
PIC16F8X
8.4
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions
are met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
The POR circuit does not produce an internal reset
when VDD declines.
8.5
Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (TPWRT) from POR (Figure 8-10,
Figure 8-11, Figure 8-12 and Figure 8-13). The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT delay allows the VDD to rise to an acceptable level (Possible exception shown in Figure 8-13).
FIGURE 8-9:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
VDD
D
R
R1
MCLR
C
PIC16FXX
Note 1: External Power-on Reset circuit is required
only if VDD power-up rate is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR pin.
3: R1 = 100 to 1 k will limit any current
flowing into MCLR from external
capacitor C in the event of an MCLR pin
breakdown due to ESD or EOS.
A configuration bit, PWRTE, can enable/disable the
PWRT. See either Figure 8-1 or Figure 8-2 for the operation of the PWRTE bit for a particular device.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
8.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 8-10, Figure 8-11,
Figure 8-12 and Figure 8-13). This ensures the crystal
oscillator or resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 8-13), an external power-on reset circuit may
be necessary (Figure 8-9).
DS30430D-page 44
1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1996-2013 Microchip Technology Inc.
DS30430D-page 45
PIC16F8X
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS30430D-page 46
1996-2013 Microchip Technology Inc.
PIC16F8X
8.7
Time-out Sequence and Power-down
Status Bits (TO/PD)
On power-up (Figure 8-10, Figure 8-11, Figure 8-12
and Figure 8-13) the time-out sequence is as follows:
First PWRT time-out is invoked after a POR has
expired. Then the OST is activated. The total time-out
will vary based on oscillator configuration and PWRTE
configuration bit status. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
TABLE 8-5
Power-up
PWRT
Enabled
PWRT
Disabled
Wake-up
from
SLEEP
XT, HS, LP
72 ms +
1024TOSC
1024TOSC
1024TOSC
RC
72 ms
—
—
Table 8-6 shows the significance of the TO and PD bits.
Table 8-3 lists the reset conditions for some special
registers, while Table 8-4 lists the reset conditions for
all the registers.
TO
PD
1
0
x
0
0
1
1
1
x
0
1
0
1
0
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
To reset a PIC16F8X device when a brown-out occurs,
external brown-out protection circuits may be built, as
shown in Figure 8-14 and Figure 8-15.
VDD
VDD
33k
10k
Since the time-outs occur from the POR reset pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 8-10). This is useful for testing
purposes or to synchronize more than one PIC16F8X
device when operating in parallel.
TABLE 8-6
Reset on Brown-Out
FIGURE 8-14: BROWN-OUT PROTECTION
CIRCUIT 1
TIME-OUT IN VARIOUS
SITUATIONS
Oscillator
Configuration
8.8
STATUS BITS AND THEIR
SIGNIFICANCE
Condition
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt
wake-up from SLEEP
40k
PIC16F8X
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
FIGURE 8-15: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
40k
PIC16F8X
This brown-out circuit is less expensive, although less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
VDD •
1996-2013 Microchip Technology Inc.
MCLR
R1
R1 + R2
= 0.7V
DS30430D-page 47
PIC16F8X
8.9
Interrupts
The PIC16F8X has 4 sources of interrupt:
•
•
•
•
External interrupt RB0/INT pin
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
FIGURE 8-16: INTERRUPT LOGIC
T0IF
T0IE
INTF
INTE
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs
(Figure 8-17). The latency is the same for both one and
two cycle instructions. Once in the interrupt service
routine the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling
interrupts to avoid infinite interrupt requests.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
Wake-up
(If in SLEEP mode)
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
DS30430D-page 48
1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag
(INTCON)
Interrupt Latency 2
5
GIE bit
(INTCON)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC+1
Inst (PC+1)
Inst (PC)
0004h
PC+1
—
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
8.9.1
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2
8.9.3
PORT RB INTERRUPT
An input change on PORTB sets flag bit RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON)
(Section 5.2).
Note 1: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY wide.
TMR0 INTERRUPT
An overflow (FFh 00h) in TMR0 will set flag bit T0IF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON)
(Section 6.0).
1996-2013 Microchip Technology Inc.
DS30430D-page 49
PIC16F8X
8.10
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
Example 8-1 stores and restores the STATUS and W
register’s values. The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 8-1 does the following:
a)
b)
c)
d)
e)
Stores the W register.
Stores the STATUS register in STATUS_TEMP.
Executes the Interrupt Service Routine code.
Restores the STATUS (and bank select bit)
register.
Restores the W register.
EXAMPLE 8-1:
SAVING STATUS AND W REGISTERS IN RAM
PUSH
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
W_TEMP
STATUS, W
STATUS_TEMP
MOVWF
STATUS
SWAPF
SWAPF
W_TEMP, F
W_TEMP, W
ISR
POP
DS30430D-page 50
STATUS_TEMP, W
;
;
;
:
;
;
;
;
;
;
;
;
;
Copy W to TEMP register,
Swap status to be saved into W
Save status to STATUS_TEMP register
Interrupt Service Routine
should configure Bank as required
Swap nibbles in STATUS_TEMP register
and place result into W
Move W into STATUS register
(sets bank to original state)
Swap nibbles in W_TEMP and place result in W_TEMP
Swap nibbles in W_TEMP and place result into W
1996-2013 Microchip Technology Inc.
PIC16F8X
8.11
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 8.1).
8.11.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device
RESET condition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
8.11.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
WDT Timer
•
1
M
U
X
Postscaler
8
8 - to -1 MUX
PS2:PS0
•
To TMR0 (Figure 6-6)
PSA
WDT
Enable Bit
1
0
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 8-7
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
2007h
Config. bits
81h
OPTION_
REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
(2)
(2)
(2)
(2)
PWRTE(1)
WDTE
FOSC1
FOSC0
(2)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Value on all
other resets
1111 1111
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.
2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits.
1996-2013 Microchip Technology Inc.
DS30430D-page 51
PIC16F8X
8.12
Power-down Mode (SLEEP)
8.12.2
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
8.12.1
SLEEP
The Power-down mode is entered by executing the
SLEEP instruction.
If enabled, the Watchdog Timer is cleared (but keeps
running), the PD bit (STATUS) is cleared, the TO bit
(STATUS) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high, low,
or hi-impedance).
For the lowest current consumption in SLEEP mode,
place all I/O pins at either at VDD or VSS, with no
external circuitry drawing current from the I/O pins, and
disable external clocks. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS. The
contribution from on-chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (VIHMC).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
WDT Wake-up (if WDT was enabled).
Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR reset) will cause a device reset.
The two latter events are considered a continuation of
program execution. The TO and PD bits can be used to
determine the cause of a device reset. The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up).
While the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON)
Interrupt Latency
(Note 2)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Note
1:
2:
3:
4:
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
Inst(PC + 1)
SLEEP
PC+2
PC+2
PC + 2
Inst(PC + 2)
Inst(PC + 1)
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30430D-page 52
1996-2013 Microchip Technology Inc.
PIC16F8X
8.12.3
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
8.13
Program Verification/Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
8.14
Microchip does not recommend code protecting widowed devices.
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations to store checksum or other code
identification numbers. These locations are not
accessible during normal execution but are readable
and writable only during program/verify. Only the
4 least significant bits of ID location are usable.
8.15
In-Circuit Serial Programming
PIC16F8X
microcontrollers
can
be
serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product,
allowing the most recent firmware or custom firmware
to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) points to location 00h.
A 6-bit command is then supplied to the device, 14-bits
of program data is then supplied to or from the device,
using load or read-type instructions. For complete
details of serial programming, please refer to the
PIC16CXX Programming Specifications (Literature
#DS30189).
FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC16FXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
For ROM devices, these values are submitted along
with the ROM code.
VDD
To Normal
Connections
For ROM devices, both the program memory and Data
EEPROM memory may be read, but only the Data
EEPROM memory may be programmed.
1996-2013 Microchip Technology Inc.
DS30430D-page 53
PIC16F8X
DS30430D-page 54
1996-2013 Microchip Technology Inc.
PIC16F8X
9.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 9-1
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Label name
TOS
Top of Stack
PC
Program Counter
PCLATH
Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest
Destination either the W register or the specified
register file location
[ ]
Options
italics
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 s.
Table 9-2 lists the instructions recognized by the
MPASM assembler.
Figure 9-1 shows the general formats that the instructions can have.
Note:
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label
( )
The instruction set is highly orthogonal and is grouped
into three basic categories:
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
Contents
0
k (literal)
k = 8-bit immediate value
Assigned to
Register bit field
In the set of
User defined term (font is courier)
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
1996-2013 Microchip Technology Inc.
DS30430D-page 55
PIC16F8X
TABLE 9-2
PIC16FXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30430D-page 56
1996-2013 Microchip Technology Inc.
PIC16F8X
9.1
Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
AND Literal with W
Syntax:
[label] ADDLW
Syntax:
[label] ANDLW
Operands:
0 k 255
Operands:
0 k 255
Operation:
(W) + k (W)
Operation:
(W) .AND. (k) (W)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
k
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
ADDLW
0x15
Q Cycle Activity:
Example
=
=
ADDWF
Add W and f
Q3
Q4
Process
data
Write to
W
ANDLW
0x5F
W
0x10
=
0xA3
After Instruction
After Instruction
W
Q2
Read
literal "k"
Before Instruction
Before Instruction
W
Q1
Decode
W
0x25
=
ANDWF
AND W with f
0x03
Syntax:
[label] ADDWF
Syntax:
[label] ANDWF
Operands:
0 f 127
d
Operands:
0 f 127
d
Operation:
(W) + (f) (destination)
Operation:
(W) .AND. (f) (destination)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
00
f,d
0111
dfff
ffff
Encoding:
00
f,d
0101
dfff
ffff
Description:
Add the contents of the W register with
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
AND the W register with register 'f'. If 'd'
is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
ADDWF
FSR, 0
Before Instruction
W =
FSR =
1996-2013 Microchip Technology Inc.
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
ANDWF
FSR, 1
Before Instruction
0x17
0xC2
After Instruction
W =
FSR =
Q Cycle Activity:
W =
FSR =
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
0x17
0x02
DS30430D-page 57
PIC16F8X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BCF
Syntax:
[label] BTFSC f,b
Operands:
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f)
Operation:
skip if (f) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BCF
Encoding:
10bb
bfff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is executed.
If bit 'b', in register 'f', is '0' then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
FLAG_REG, 7
01
Description:
Before Instruction
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
No-Operat
ion
Q3
Q4
FLAG_REG = 0xC7
If Skip:
After Instruction
FLAG_REG = 0x47
(2nd Cycle)
Q1
Q2
No-Operat
ion
Example
HERE
FALSE
TRUE
No-Operati No-Opera No-Operat
on
tion
ion
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
BSF
Bit Set f
Syntax:
[label] BSF
Operands:
0 f 127
0b7
Operation:
1 (f)
Status Affected:
None
Encoding:
Description:
01
1
Cycles:
1
Example
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
Words:
Q Cycle Activity:
if FLAG = 0,
PC =
address TRUE
if FLAG=1,
PC =
address FALSE
f,b
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30430D-page 58
1996-2013 Microchip Technology Inc.
PIC16F8X
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[label] BTFSS f,b
Syntax:
[ label ] CALL k
Operands:
0 f 127
0b
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