FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
Low power, quad nanoDACs
AD5664: 16 bits
AD5624: 12 bits
Relative accuracy: ±12 LSBs max
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Power-on reset to zero
Per channel power-down
Serial interface, up to 50 MHz
GND
VREF
AD5624/AD5664
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
VOUTD
SCLK
SYNC
INTERFACE
LOGIC
DIN
POWER-ON
RESET
APPLICATIONS
POWER-DOWN
LOGIC
05943-001
Data Sheet
2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output,
Quad, 12-/16-Bit nanoDACs
AD5624/AD5664
Figure 1.
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5624/AD5664, members of the nanoDAC® family, are
low power, quad, 12-, 16-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.
The AD5624/AD5664 use a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz, and are compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.
The AD5624/AD5664 require an external reference voltage to
set the output range of the DAC. The device incorporates a
power-on reset circuit that ensures the DAC output powers up
to 0 V and remains there until a valid write takes place. The
devices contain a power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
PRODUCT HIGHLIGHTS
The low power consumption of these devices in normal
operation makes them ideally suited to portable batteryoperated equipment. The power consumption is 2.25 mW at 5
V, going down to 2.4 μW in power-down mode.
The AD5624/AD5664 on-chip precision output amplifier allows
rail-to-rail output swing to be achieved.
Rev. A
1.
2.
3.
4.
Relative accuracy: ±12 LSBs maximum.
Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,
LFCSP_WD.
Low power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
Maximum settling time of 4.5 μs (AD5624) and 7 μs
(AD5664).
Table 1. Related Devices
Part No.
AD5624R/AD5644R/AD5664R
Description
2.7 V to 5.5 V quad, 12-, 14-,
16-bit DACs with internal
reference
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Tel: 781.329.4700 ©2006–2018 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5624/AD5664
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 15
Applications ....................................................................................... 1
Input Shift Register .................................................................... 16
Functional Block Diagram .............................................................. 1
SYNC Interrupt .......................................................................... 16
General Description ......................................................................... 1
Power-On Reset .......................................................................... 16
Product Highlights ........................................................................... 1
Software Reset ............................................................................. 17
Revision History ............................................................................... 2
Power-Down Modes .................................................................. 17
Specifications..................................................................................... 3
LDAC Function .......................................................................... 18
AC Characteristics........................................................................ 4
Microprocessor Interfacing ....................................................... 19
Timing Characteristics ................................................................ 5
Applications Information .............................................................. 20
Timing Diagram ........................................................................... 5
Choosing a Reference for the AD5624/AD5664........................ 20
Absolute Maximum Ratings............................................................ 6
Using a Reference as a Power Supply for the
AD5624/AD5664........................................................................ 20
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
D/A Section ................................................................................. 15
Bipolar Operation Using the AD5624/AD5664......................... 21
Using AD5624/AD5664 with a Galvanically Isolated
Interface ....................................................................................... 21
Power Supply Bypassing and Grounding ................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide............................................................................... 23
Resistor String ............................................................................. 15
Output Amplifier ........................................................................ 15
REVISION HISTORY
6/2018—Rev. 0 to Rev. A
Changes to Figure 3 Caption and Table 6...................................... 7
Add Figure 4; Renumber Sequentially ........................................... 7
Changed Applications Section to Applications Information
Section .............................................................................................. 20
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23
6/2006—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
AD5624/AD5664
SPECIFICATIONS
VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE2
AD5664
Resolution
Relative Accuracy
Differential Nonlinearity
Min
A Grade1
Typ
Max
16
16
±8
±16
±1
AD5624
Resolution
Relative Accuracy
Differential Nonlinearity
±0.5
2
±1
−0.1
10
±10
±1
±1.5
±12
±1
Bits
LSB
LSB
±1
±0.25
Bits
LSB
LSB
Guaranteed monotonic by
design
Guaranteed monotonic by
design
All zeroes loaded to DAC register
±2
±2.5
−100
−100
dB
DAC code = midscale ; VDD ± 10%
10
10
μV
10
5
10
5
μV/mA
μV
Due to full-scale output change
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per
channel)
0
2
10
0.5
30
4
170
0.75
VDD
2
10
0.5
30
4
200
VDD
170
0.75
26
2
3
3
Rev. A | Page 3 of 23
V
nF
nF
Ω
mA
μs
All ones loaded to DAC register
Of FSR/°C
RL = ∞
RL = 2 kΩ
VDD = 5 V
Coming out of power-down
mode; VDD = 5 V
200
VDD
μA
V
kΩ
VREF = VDD = 5.5 V
±2
0.8
μA
V
V
pF
All digital inputs
VDD = 5 V, 3 V
VDD = 5 V, 3 V
26
±2
0.8
2
10
±10
±1
±1.5
Conditions/Comments
±2
±2.5
VDD
2
±1
−0.1
Unit
mV
mV
% of FSR
% of FSR
μV/°C
ppm
0
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
±6
12
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Temperature
Coefficient
DC Power Supply Rejection
Ratio
DC Crosstalk
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
Min
B Grade1
Typ
Max
AD5624/AD5664
Parameter
POWER REQUIREMENTS
VDD
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down
Modes)5
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
Data Sheet
Min
A Grade1
Typ
Max
2.7
5.5
Min
B Grade1
Typ
Max
2.7
Unit
5.5
V
0.9
0.85
mA
mA
Conditions/Comments
VIH = VDD, VIL = GND
0.45
0.44
0.9
0.85
0.45
0.44
VIH = VDD, VIL = GND
0.48
0.2
1
1
0.48
0.2
1
1
μA
μA
1
Temperature range: A grade and B grade: −40°C to +105°C.
Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded.
Guaranteed by design and characterization, not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All DACs powered down.
2
3
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2, 3
Output Voltage Settling Time
AD5664
AD5624
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
Min
Typ
Max
Unit
Conditions/Comments
4
3
1.8
10
0.1
−90
0.1
1
1
340
−80
120
100
15
7
4.5
μs
μs
V/μs
nV-s
nV-s
dBs
nV-s
nV-s
nV-s
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±0.5 LSB
1
Guaranteed by design and characterization, not production tested.
Temperature range: −40°C to +105°C; typical at 25°C.
3
See the Terminology section.
2
Rev. A | Page 4 of 23
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
VREF = 2 V ± 0.1 V p-p
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
Data Sheet
AD5624/AD5664
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
Parameter1
t12
t2
t3
t4
t5
t6
t7
t8
t9
t10
1
2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
Guaranteed by design and characterization, not production tested.
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t10
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
DIN
DB23
t6
DB0
Figure 2. Serial Write Operation
Rev. A | Page 5 of 23
05943-002
t5
AD5624/AD5664
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial (A Grade, B Grade)
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
LFCSP_WD Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
61°C/W
142°C/W
43.7°C/W
260°C ± 5°C
Rev. A | Page 6 of 23
Data Sheet
AD5624/AD5664
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUTA 1
GND 3
VOUTB 2
GND 3
VOUTC 4
AD5624/
AD5664
TOP VIEW
(Not to Scale)
VOUTD 5
10
VREF
VOUTC 4
9
VDD
VOUTD 5
8
DIN
7
SCLK
6
SYNC
AD5624/
AD5664
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
05943-003
VOUTA 1
10 VREF
9
VDD
8
DIN
7
SCLK
6
SYNC
05943-104
VOUTB 2
Figure 4. 10-Lead LFCSP Pin Configuration
Figure 3. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
VOUTA
VOUTB
GND
VOUTC
VOUTD
SYNC
7
SCLK
8
DIN
9
VDD
10
VREF
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the device
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on
the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next
24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. The supply is decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
Reference Voltage Input.
Exposed Pad. Exposed pad tied to GND on LFCSP package.
Rev. A | Page 7 of 23
AD5624/AD5664
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
10
VDD = VREF = 5V
TA = 25°C
8
6
0.10
DNL ERROR (LSB)
4
INL ERROR (LSB)
VDD = VREF = 5V
TA = 25°C
0.15
2
0
–2
–4
0.05
0
–0.05
–0.10
–6
0
–0.20
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
05943-007
–10
–0.15
05943-004
–8
0
500
1000
1500
2000 2500
CODE
3000
3500
4000
Figure 8. DNL AD5624
Figure 5. INL AD5664
8
1.0
VDD = VREF = 5V
0.8 TA = 25°C
6
MAX INL
VDD = VREF = 5V
0.6
4
ERROR (LSB)
INL ERROR (LSB)
0.4
0.2
0
–0.2
2
MAX DNL
0
MIN DNL
–2
–0.4
–4
–0.6
MIN INL
0
500
1000
1500
2000
2500
CODE
3000
3500
Figure 6. INL AD5624
0
20
40
60
TEMPERATURE (°C)
80
100
10
VDD = VREF = 5V
TA = 25°C
0.8
0.4
4
ERROR (LSB)
6
0.2
0
–0.2
MAX DNL
0
–0.6
–6
10k
20k
30k
CODE
40k
50k
MIN DNL
–2
–4
–0.8
VDD = 5V
TA = 25°C
2
–0.4
0
MAX INL
8
0.6
05943-006
DNL ERROR (LSB)
–20
Figure 9. INL Error and DNL Error vs. Temperature
1.0
–1.0
05856-022
–8
–40
4000
MIN INL
–8
–10
0.75
60k
1.25
1.75
2.25
2.75
3.25
VREF (V)
3.75
Figure 10. INL and DNL Error vs. VREF
Figure 7. DNL AD5664
Rev. A | Page 8 of 23
4.25
05943-009
–1.0
–6
05943-005
–0.8
4.75
Data Sheet
AD5624/AD5664
8
1.0
6
MAX INL
TA = 25°C
0.5
GAIN ERROR
ERROR (% FSR)
ERROR (LSB)
4
2
MAX DNL
0
MIN DNL
–2
0
FULL-SCALE ERROR
–0.5
–1.0
–4
MIN INL
05943-010
–8
2.7
3.2
3.7
4.2
VDD (V)
4.7
–2.0
2.7
5.2
3.7
4.2
VDD (V)
4.7
5.2
1.0
0
VDD = 5V
TA = 25°C
0.5
–0.04
GAIN ERROR
ERROR (mV)
–0.08
–0.10
–0.12
–0.14
ZERO-SCALE ERROR
0
–0.06
ERROR (% FSR)
3.2
Figure 14. Gain Error and Full-Scale Error vs. Supply
Figure 11. INL and DNL Error vs. Supply
–0.02
05943-013
–1.5
–6
–0.5
–1.0
–1.5
FULL-SCALE ERROR
–0.20
–40
–2.0
05943-011
–0.18
–20
0
20
40
60
TEMPERATURE (°C)
80
OFFSET ERROR
–2.5
2.7
100
Figure 12. Gain Error and Full-Scale Error vs. Temperature
3.2
3.7
4.2
VDD (V)
4.7
05943-014
–0.16
5.2
Figure 15. Zero-Scale Error and Offset Error vs. Supply
1.5
6
ZERO-SCALE ERROR
5
0
4
FREQUENCY
0.5
–0.5
–1.0
VDD = 5.5V
TA = 25°C
3
2
–1.5
OFFSET ERROR
–2.5
–40
1
–20
0
20
40
60
TEMPERATURE (°C)
80
0
100
Figure 13. Zero-Scale Error and Offset Error vs. Temperature
05943-017
–2.0
05943-012
ERROR (mV)
1.0
0.41
0.42
0.43
IDD (mA)
0.44
Figure 16. IDD Histogram with VDD = 5.5 V
Rev. A | Page 9 of 23
0.45
AD5624/AD5664
8
7
Data Sheet
VDD = 3.6V
TA = 25°C
FREQUENCY
6
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
5
4
3
VOUT = 909mV/DIV
2
0.39
0.40
0.41
IDD (mA)
0.42
05943-021
0
05943-018
1
1
0.43
TIME BASE = 4µs/DIV
Figure 20. Full-Scale Settling Time, 5 V
Figure 17. IDD Histogram with VDD = 3.6 V
0.20
0.15
DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT
VDD = VREF = 5V, 3V
TA = 25°C
VDD = VREF = 5V
TA = 25°C
ERROR VOLTAGE (V)
0.10
0.05
0
–0.05
VDD
1
–0.10
–0.15
–0.25
–5
–4
–3
–2
–1
0
I (mA)
1
2
3
4
MAX(C2)
420.0mV
2
VOUT
5
CH1 2.0V
VDD = VREFIN = 5V
1
VDD = VREFIN = 3V
0.35
8.0ns/pt
SLCK
3
0.30
0.25
0.20
0.15
VOUT
0.10
0.05
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 19. Supply Current vs. Temperature
05943-023
TA = 25°C
0
–40
–20
VDD = 5V
2
05943-026
IDD (mA)
M100µs 125MS/s
A CH1
1.28V
SYNC
0.45
0.40
CH2 500mV
Figure 21. Power-On Reset to 0 V
Figure 18. Headroom at Rails vs. Source and Sink Current
0.50
05943-022
–0.20
05943-016
DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
Figure 22. Exiting Power-Down to Midscale
Rev. A | Page 10 of 23
1.4V
16
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
VREF = VDD
TA = 25°C
14
VDD = 3V
12
TIME (µs)
10
VDD = 5V
8
6
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
4
512
05943-028
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
AD5624/AD5664
05943-024
VOUT (V)
Data Sheet
0
Figure 23. Digital-to-Analog Glitch Impulse (Negative)
2.498
3
4
5
6
7
CAPACITANCE (nF)
8
9
10
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
2.496
VOUT (V)
2
Figure 26. Settling Time vs. Capacitive Load
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
2.497
1
2.495
2.494
1
2.493
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
512
Figure 24. Analog Crosstalk
Figure 27. 0.1 Hz to 10 Hz Output Noise Plot
–20
–40
800
VDD = 5V
TA = 25°C
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3V p-p
700
OUTPUT NOISE (nV/√Hz)
–30
–60
–70
–80
–90
05943-027
(dB)
–50
–100
05943-029
0
2k
4k
6k
8k
10k
(Hz)
Figure 25. Total Harmonic Distortion
VDD = VREF = 5V
TA = 25°C
600
500
400
300
200
100
0
10
05943-030
2.491
05943-025
2.492
100
1k
10k
FREQUENCY (Hz)
Figure 28. Noise Spectral Density
Rev. A | Page 11 of 23
100k
1M
AD5624/AD5664
5
Data Sheet
VDD = 5V
TA = 25°C
0
–5
–15
–20
–25
–30
–35
–40
10k
05943-031
(dB)
–10
100k
1M
FREQUENCY (Hz)
10M
Figure 29. Multiplying Bandwidth
Rev. A | Page 12 of 23
Data Sheet
AD5624/AD5664
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 5 and Figure 6.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by ±10%.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 7 and
Figure 8.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change and is
measured from the 24th falling edge of SCLK.
Zero-Scale Error
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output is 0 V. The zero code error is always positive in the
AD5624/AD5664 because the output of the DAC cannot go
below 0 V. It is due to a combination of the offset errors in the
DAC and the output amplifier. Zero code error is expressed in
mV. A plot of zero code error vs. temperature can be seen in
Figure 13.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the
output is VDD − 1 LSB. Full-scale error is expressed in % of FSR.
A plot of full-scale error vs. temperature can be seen in Figure 12.
Gain Error
This is a measure of the span error of the DAC. It is the deviation in
slope of the DAC transfer characteristic from ideal expressed as
a % of FSR.
Zero Code Error Drift
This is a measurement of the change in zero code error with a
change in temperature. It is expressed in μV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5624/
AD5664 with code 512 loaded in the DAC register. It can be
negative or positive.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000) as shown in
Figure 23.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measurement of the harmonics
present on the DAC output. It is measured in dB.
Noise Spectral Density
This is a measurement of the internally generated random noise.
Random noise is characterized as a spectral density (nV/√Hz).
It is measured by loading the DAC to midscale and measuring
noise at the output. It is measured in nV/√Hz. A plot of noise
spectral density can be seen in Figure 28.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in μV/mA.
Rev. A | Page 13 of 23
AD5624/AD5664
Data Sheet
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was
not changed. The area of the glitch is expressed in nV-s (see
Figure 24).
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output change
of another DAC. It is measured by loading the attack channel
with a full-scale code change (all 0s to all 1s and vice versa) using
the command write to and update while monitoring the output of
the victim channel that is at midscale. The energy of the glitch is
expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
Rev. A | Page 14 of 23
Data Sheet
AD5624/AD5664
THEORY OF OPERATION
D/A SECTION
R
The AD5624/AD5664 DACs are fabricated on a CMOS process.
The architecture consists of a string DAC followed by an output
buffer amplifier. Figure 30 shows a block diagram of the DAC
architecture.
R
TO OUTPUT
AMPLIFIER
R
REF (+)
DAC
REGISTER
OUTPUT
AMPLIFIER
(GAIN = +2)
RESISTOR
STRING
REF (–)
GND
VOUT
05943-032
VDD
R
Figure 30. DAC Architecture
05943-033
R
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
VOUT VREFIN
D
N
2
Figure 31. Resistor String
SERIAL INTERFACE
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5624 (12 bit).
0 to 65535 for AD5664 (16 bit).
N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 31. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can
drive a load of 2 kΩ in parallel with 1000 pF to GND. The source
and sink capabilities of the output amplifier can be seen in
Figure 18. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale
settling time of 7 μs.
The AD5624/AD5664 have a 3-wire serial interface (SYNC,
SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as with most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5624/AD5664 compatible with high
speed DSPs. On the 24th falling clock edge, the last data bit is
clocked in and the programmed function is executed, that is, a
change in DAC register contents and/or a change in the mode
of operation. At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a falling
edge of SYNC can initiate the next write sequence. Because the
SYNC buffer draws more current when VIN = 2.0 V than it does
when VIN = 0.8 V, SYNC is idled low between write sequences for
even lower power operation. It must, however, be brought high
again just before the next write sequence.
Rev. A | Page 15 of 23
AD5624/AD5664
Data Sheet
INPUT SHIFT REGISTER
SYNC INTERRUPT
The input shift register is 24 bits wide. The first two bits are don’t
care bits. The next three bits are the Command bits, C2 to C0
(see Table 7), followed by the 3-bit DAC address, A2 to A0 (see
Table 8), and then the 16-, 12-bit data-word. The data-word
comprises the 16-, 12- bit input code followed by 0 or 4 don’t
care bits for the AD5664 and AD5624 respectively (see Figure 32
and Figure 33). These data bits are transferred to the DAC
register on the 24th falling edge of SCLK.
In a normal write sequence, the SYNC line is kept low for at least
24 falling edges of SCLK, and the DAC is updated on the 24th
falling edge. However, if SYNC is brought high before the 24th
falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 34).
POWER-ON RESET
Table 7. Command Definition
C2
0
0
0
C1
0
0
1
C0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
The AD5624/AD5664 family contains a power-on reset circuit
that controls the output voltage during power-up. The AD5624/
AD5664 DAC outputs power up to 0 V and the output remains
there until a valid write sequence is made to the DAC. This is
useful in applications where it is important to know the state of
the output of the DAC while it is in the process of powering up.
Command
Write to input register n
Update DAC register n
Write to input register n, update all (software
LDAC)
Write to and update DAC channel n
Power down DAC (power-up)
Reset
Load LDAC register
Reserved
Table 8. Address Command
A2
0
0
0
0
1
A1
0
0
1
1
1
A0
0
1
0
1
1
ADDRESS (n)
DAC A
DAC B
DAC C
DAC D
All DACs
DB23 (MSB)
X
DB0 (LSB)
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
D1
D0
05943-034
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 32. AD5664 Input Shift Register Contents
DB23 (MSB)
X
DB0 (LSB)
C2
C1
C0
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
DATA BITS
COMMAND BITS
X
X
05943-035
X
ADDRESS BITS
Figure 33. AD5624 Input Shift Register Contents
SCLK
SYNC
DB23
DB0
DB23
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
Figure 34. SYNC Interrupt Facility
Rev. A | Page 16 of 23
05943-036
DIN
Data Sheet
AD5624/AD5664
SOFTWARE RESET
Table 10. Modes of Operation for the AD5624/AD5664
The AD5624/AD5664 contain a software reset function.
Command 110 is reserved for the software reset function (see
Table 7). The software reset command contains two reset modes
that are software programmable by setting Bit DB0 in the control
register. Table 9 shows how the state of the bit corresponds to
the software reset modes of operation of the devices.
DB5
0
DB4
0
0
1
1
1
0
1
When both bits are set to 0, the devices work normally with
their normal power consumption of 450 μA at 5 V. However, for
the three power-down modes, the supply current falls to 480 nA
at 5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This allows
the output impedance of the device to be known while the
device is in power-down mode.
1 (Power-On Reset)
Registers Reset to Zero
DAC register
Input shift register
DAC register
Input shift register
LDAC register
Power-down register
POWER-DOWN MODES
The AD5624/AD5664 contain four separate modes of operation.
Command 100 is reserved for the power-down function (see
Table 7). These modes are software programmable by setting two
bits (DB5 and DB4) in the control register. Table 10 shows how
the state of the bits corresponds to the mode of operation of the
device. All DACs (DAC D to DAC A) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, and DB0) to 1. By executing the same Command 100,
any combination of DACs is powered up by setting Bit DB5 and
Bit DB4 to normal operation mode. To select which combination
of DAC channels to power-up, set the corresponding four bits
(DB3, DB2, DB1, and DB0) to 1. See Table 11 for contents of the
input shift register during the power-down/power-up operation.
The outputs can either be connected internally to GND through
a 1 kΩ or 100 kΩ resistor, or left open circuited (three-state)
(see Figure 35).
RESISTOR
STRING DAC
AMPLIFIER
POWER-DOWN
CIRCUITRY
VOUT
RESISTOR
NETWORK
05943-037
Table 9. Software Reset Modes for the AD5624/AD5664
DB0
0
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
Figure 35. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-down
is typically 4 μs for VDD = 5 V and for VDD = 3 V (see Figure 22).
Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
DB23 to
DB22
(MSB)
x
Don’t care
DB21 DB20 DB19
1
0
0
Command bits (C2 to
C0)
DB18
DB17
DB16
x
x
x
Address bits (A2 to A0);
don’t care
DB15
to DB6
x
Don’t
care
Rev. A | Page 17 of 23
DB5
DB4
PD1
PD0
Power-down
mode
DB0
DB3
DB2
DB1
(LSB)
DAC D
DAC C
DAC B
DAC A
Power-down/power-up channel
selection, set bit to 1 to select channel
AD5624/AD5664
Data Sheet
LDAC FUNCTION
The AD5624/AD5664 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The input registers are connected directly to the input
shift register and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The
DAC registers contain the digital code used by the resistor strings.
The double buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then write to the
remaining input register and update all DAC registers, the outputs
update simultaneously. Command 010 is reserved for this
software LDAC.
Access to the DAC registers is controlled by the LDAC function.
The LDAC registers contain two modes of operation for each
DAC channel. The DAC channels are selected by setting the bits
of the 4-bit LDAC register (DB3, DB2, DB1, and DB0).
Command 110 is reserved for setting up the LDAC register.
When the LDAC bit register is set low, the corresponding DAC
registers are latched and the input registers can change state
without affecting the contents of the
DAC registers. When the LDAC bit register is set high, however,
the DAC registers become transparent and the contents of the
input registers are transferred to them on the falling edge of the
24th SCLK pulse. This is equivalent to having an LDAC hardware
pin tied permanently low for the selected DAC channel, that is,
synchronous update mode. See Table 12 for the LDAC register
mode of operation. See Table 13 for contents of the input shift
register during the LDAC register set up command.
This flexibility is useful in applications where the user wants to
update select channels simultaneously, while the rest of the
channels update synchronously.
Table 12. LDAC Register Mode of Operation
Load DAC Register
LDAC Bits (DB3 to DB0) LDAC Mode of Operation
0
Normal operation (default), DAC
register update is controlled by write
command.
1
The DAC registers are updated after
new data is read in on the falling
edge of the 24th SCLK pulse.
Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664
DB23 to DB22 (MSB)
x
Don’t care
DB21
DB20
DB19
1
1
0
Command bits (C2 to C0)
DB18 DB17
DB16
x
x
x
Address bits (A3 to A0);
don’t care
Rev. A | Page 18 of 23
DB15 to DB4
x
Don’t care
DB3
DB2
DB1
DB0 (LSB)
DACD DACC DACB DACA
Set bit to 0 or 1 for required mode
of operation on respective channel
Data Sheet
AD5624/AD5664
MICROPROCESSOR INTERFACING
AD5624/AD5664 to 80C51/80L51 Interface
AD5624/AD5664 to Blackfin® ADSP-BF53x Interface
Figure 38 shows a serial interface between the AD5624/AD5664
and the 80C51/80L51 microcontroller. The setup for the interface
is as follows. TxD of the 80C51/80L51 drives SCLK of the AD5624/
AD5664, while RxD drives the serial data line of the device. The
SYNC signal is derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is transmitted to
the AD5624/AD5664, P3.3 is taken low. The 80C51/80L51
transmits data in 10-bit bytes only; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 output the serial data in a format that has the LSB first. The
AD5624/AD5664 must receive data with the MSB first. The 80C51/
80L51 transmit routine takes this into account.
TFS0
AD5624/
AD56641
SYNC
DTOPRI
DIN
TSCLK0
SCLK
1ADDITIONAL
PINS OMITTED FOR CLARITY.
05943-038
ADSP-BF53x1
80C51/80L511
Figure 36. Blackfin ADSP-BF53x Interface to AD5624/AD5664
AD5624/
AD56641
P3.3
SYNC
AD5624/AD5664 to 68HC11/68L11 Interface
TxD
SCLK
Figure 37 shows a serial interface between the AD5624/AD5664
and the 68HC11/68L11 microcontroller. SCK of the 68HC11/
68L11 drives the SCLK of the AD5624/AD5664, while the MOSI
output drives the serial data line of the DAC.
RxD
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
05943-040
Figure 36 shows a serial interface between the AD5624/AD5664
and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5624/
AD5664, the setup for the interface is as follows. DTOPRI drives
the DIN pin of the AD5624/AD5664, while TSCLK0 drives the
SCLK of the device. The SYNC is driven from TFS0.
Figure 38. 80C51/80L51 Interface to AD5624/AD5664
AD5624/AD5664 to MICROWIRE Interface
AD5624/
AD56641
PC7
SYNC
SCK
SCLK
MOSI
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
05943-039
68HC11/68L111
Figure 39 shows an interface between the AD5624/AD5664 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5624/AD5664 on the rising edge of the SK.
Figure 37. 68HC11/68L11 Interface to AD5624/AD5664
Rev. A | Page 19 of 23
MICROWIRE1
1ADDITIONAL
AD5624/
AD56641
CS
SYNC
SK
SCLK
SO
DIN
PINS OMITTED FOR CLARITY.
05943-041
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows.
The 68HC11/68L11 is configured with its CPOL bit as a 0 and
its CPHA bit as a 1. When data is being transmitted to the DAC,
the SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5624/AD5664,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC; PC7 is
taken high at the end of this procedure.
Figure 39. MICROWIRE Interface to AD5624/AD5664
AD5624/AD5664
Data Sheet
APPLICATIONS INFORMATION
To achieve the optimum performance from the AD5624/
AD5664, give thought to the choice of a precision voltage
reference. The AD5624/AD5664 have only one reference input,
VREF. The voltage on the reference input is used to supply the
positive input to the DAC. Therefore, any error in the reference
is reflected in the DAC.
When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, long
term drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the DAC.
To minimize these errors, a reference with high initial accuracy
is preferred. Choosing a reference with an output trim adjustment,
such as the ADR423, allows a system designer to trim out system
errors by setting a reference voltage to a voltage other than the
nominal. The trim adjustment can also be used at temperature
to trim out any error.
Long term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable during its entire lifetime.
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5624/AD5664
Because the supply current required by the AD5624/AD5664 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the device (see Figure 40). This
is especially useful if the power supply is quite noisy, or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5624/AD5664 (see Table 14 for a suitable
reference). If the low dropout REF195 is used, it must supply
450 μA of current to the AD5624/AD5664, with no load on the
output of the DAC. When the DAC output is loaded, the REF195
also needs to supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is
450 μA + (5 V/5 kΩ) = 1.45 mA
The load regulation of the REF195 is typically 2 ppm/mA, which
results in a 2.9 ppm (14.5 μV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error.
The temperature coefficient of a reference’s output voltage affects
INL, DNL, and TUE. Choose a reference with a tight temperature
coefficient specification to reduce temperature dependence of the
DAC output voltage in ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references such as the ADR425 produce low
output noise in the 0.1 Hz to10 Hz range. Examples of recommended precision references for use as supply to the AD5624/
AD5664 are shown in the Table 14.
15V
REF195
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
5V
500mA
VDD
VREF
AD5624/
AD5664
VOUT = 0V TO 5V
05943-042
CHOOSING A REFERENCE FOR THE AD5624/AD5664
Figure 40. REF195 as Power Supply to the AD5624/AD5664
Table 14. Partial List of Precision References for Use with the AD5624/AD5664
Part No.
ADR425
ADR395
REF195
AD780
ADR423
Initial Accuracy (mV max)
±2
±6
±2
±2
±2
Temp Drift (ppm°C max)
3
25
5
3
3
Rev. A | Page 20 of 23
0.1 Hz to 10 Hz Noise (μV p-p typ)
3.4
5
50
4
3.4
VOUT (V)
5
5
5
2.5/3
3
Data Sheet
AD5624/AD5664
5V
REGULATOR
SCLK
D R1 R2
R2
VO VDD
VDD
R1
65,536 R1
VDD
AD5624/
AD5664
SDI
V1B
VOB
SYNC
DATA
V1C
VOC
DIN
VOUT
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to consider
carefully the power supply and ground return layout on the
board. The printed circuit board containing the AD5624/AD5664
has separate analog and digital sections, each having its own
area of the board. If the AD5624/AD5664 is in a system where
other devices require an AGND-to-DGND connection, make the
connection at one point only. This ground point must be as
close as possible to the AD5624/AD5664.
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
R1 = 10kΩ
AD820/
OP295
±5V
VOUT
AD5624/
AD5664
–5V
3-WIRE
SERIAL
INTERFACE
05943-043
0.1µF
SCLK
0.1µF
Figure 42. AD5624/AD5664 with a Galvanically Isolated Interface
10 D
VO
5V
65,536
10µF
VOA
GND
where D represents the input code in decimal (0 to 65536).
With VDD = 5 V, R1 = R2 = 10 kΩ,
VDD
V1A
ADuM1300
The output voltage for any input code can be calculated as
follows:
+5V
10µF
POWER
The AD5624/AD5664 have been designed for single supply
operation, but a bipolar output range is also possible using the
circuit in Figure 41. The circuit gives an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
05943-044
BIPOLAR OPERATION USING THE AD5624/AD5664
Figure 41. Bipolar Operation with the AD5624/AD5664
USING AD5624/AD5664 WITH A GALVANICALLY
ISOLATED INTERFACE
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is
functioning. Isocouplers provide isolation in excess of 3 kV. The
AD5624/AD5664 use a 3-wire serial logic interface, so the
ADuM130x 3-channel digital isolator provides the required
isolation (see Figure 42). The power supply to the device also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5624/AD5664.
The power supply to the AD5624/AD5664 must be bypassed with
10 μF and 0.1 μF capacitors. The capacitors must be located as close
as possible to the device, with the 0.1 μF capacitor ideally right up
against the device. The 10 μF capacitor is the tantalum bead type.
It is important that the 0.1 μF capacitor has low effective series
resistance (ESR) and effective series inductance (ESI), for
example, common ceramic types of capacitors. This 0.1 μF
capacitor provides a low impedance path to ground for high
frequencies caused by transient currents due to internal logic
switching.
The power supply line itself has as large a trace as possible to
provide a low impedance path and to reduce glitch effects on
the supply line. Clocks and other fast switching digital signals
must be shielded from other parts of the board by digital ground.
Avoid crossover of digital and analog signals if possible. When
traces cross on opposite sides of the board, ensure they run at
right angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip
technique where the component side of the board is dedicated
to the ground plane only and the signal traces are placed on the
solder side. This is not always possible with a 2-layer board.
Rev. A | Page 21 of 23
AD5624/AD5664
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
SEATING
PLANE
0.30
0.25
0.20
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-07-2017-C
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SIDE VIEW
0.20 REF
Figure 43. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
3.10
3.00
2.90
10
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.15
6°
0°
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. A | Page 22 of 23
0.70
0.55
0.40
091709-A
PKG-004362
0.80
0.75
0.70
0.20 MIN
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
BOTTOM VIE W
TOP VIEW
Data Sheet
AD5624/AD5664
ORDERING GUIDE
Model1
AD5624BRMZ
AD5624BRMZ-REEL7
AD5624BCPZ-R2
AD5624BCPZ-REEL7
AD5664ARMZ
AD5664ARMZ-REEL7
AD5664BRMZ
AD5664BRMZ-REEL7
AD5664BCPZ-R2
AD5664BCPZ-REEL7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±16 LSB INL
±16 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
10-Lead LFCSP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
10-Lead LFCSP
Z = RoHS Complaint Part
©2006–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05943-0-6/18(A)
Rev. A | Page 23 of 23
Package Option
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
CP-10-9
CP-10-9
Marking Code
D5J
D5J
D5J
D5J
D7C
D7C
D78
D78
D78
D78
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