HMC742HFLP5E

HMC742HFLP5E v00.0211t 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Designer’s Kit Available Typical Applications Features The HMC742HFLP5E is ideal for: -19 to 12.5 dB Gain Control in 0.5 dB Steps • Cellular/3G Infrastructure Power-up State Selection • WiBro / WiMAX / 4G High Output IP3: +39 dBm • Microwave Radio & VSAT TTL/CMOS Compatible Serial, Parallel, or latched Parallel Control • Test Equipment and Sensors ±0.25 dB Typical Gain Step Error TE • IF & RF Applications Single +5V Supply 32 Lead 5x5mm SMT Package: 25mm2 12 - 1 General Description B SO LE The HMC742HFLP5E is a digitally controlled variable gain amplifier which operates from 0.5 GHz to 4 GHz, and can be programmed to provide from -19 dB attenuation, to 12.5 dB of gain, in 0.5 dB steps. The HMC742HFLP5E delivers noise figure of 4 dB in its maximum gain state, with output IP3 of up to +39 dBm in any state. The dual mode gain control interface accepts either a three-wire serial input or a 6 bit parallel word. The HMC742HFLP5E also features a user selectable power up state and a serial output for cascading other serially controlled Hittite components. The HMC742HFLP5E is housed in an RoHS compliant 5x5 mm QFN leadless package, and requires minimal external components. Electrical Specifications, TA = +25° C, 50 Ohm System Vdd = +5V, Vs= +5V Parameter Min. Frequency Range Typ. Max. Min. Typ. Max. Units 500 - 2700 2700-4000 MHz Gain (Maximum Gain State) 12.5 9 dB Gain Control Range 31.5 31.5 dB Input Return Loss 14 12 dB Output Return Loss 10 12 dB Gain Accuracy: (Referenced to Maximum Gain State) All Gain States ± (0.3 + 4% of relative gain setting) Max O VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 Functional Diagram Output Power for 1 dB Compression Output Third Order Intercept Point (Two-Tone Output Power= 12 dBm Each Tone) Noise Figure (Max Gain State) Switching Characteristics 21 tRISE, tFall (10 / 90% RF) tON, tOFF (Latch Enable to 10 / 90% RF) Supply Current (Amplifier) Supply Current (Controller) Idd 130 dB 22 dBm 39 38 dBm 4 4.5 dB 30 60 30 60 ns ns 150 0.12 175 0.25 130 150 0.12 175 0.25 mA mA Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, andRoad, to place orders: Analog Devices, For price, delivery and to for place Hittite Microwave Corporation, 20 Alpha Chelmsford, MA 01824Inc., responsibility is assumed by Analog Devices its use, orders: nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Relative Gain Setting (Referenced to Maximum Gain State) 0 12 -10 8 4 0 0 0.5 1 1.5 2 2.5 3 3.5 4 16dB 31.5dB -30 -40 4.5 FREQUENCY (GHz) 0 0.5 1 1.5 2.5 3.5 4 4.5 3 3.5 4 4.5 28 32 LE 0 0dB -20 -30 -40 0 B SO -10 0.5 1 1.5 2 2.5 3 3.5 4 -10 -20 -30 -40 0 4.5 0.5 1 1.5 2 2.5 FREQUENCY (GHz) FREQUENCY (GHz) Bit Error vs. Attenuation State O Bit Error vs. Frequency 1.5 3 1 BIT ERROR (dB) 4 2 31.5dB 16dB 1 0 4.0 GHz 0.7 GHz 0.5 0 -0.5 2.0 GHz 3.0 GHz -1 -1 -2 3 Output Return Loss 0 BIT ERROR (dB) 2 FREQUENCY (GHz) Input Return Loss RETURN LOSS (dB) -20 TE +25 C +85 C -40 C 8dB -1.5 0 0.5 1 1.5 2 2.5 3 FREQUENCY (GHz) 3.5 4 4.5 0 4 8 12 16 20 24 ATTENUATION STATE (dB) Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, andRoad, to place orders: Analog Devices, For price, delivery and to place Hittite Microwave Corporation, 20 Alpha Chelmsford, MA 01824Inc., responsibility is assumed by Analog Devices for its use,orders: nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT RELATIVE GAIN (dB) 16 RETURN LOSS (dB) GAIN (dB) Maximum Gain vs. Frequency 12 - 2 HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Relative Phase vs. Frequency (Referenced to Maximum Gain State) Step Attenuation vs. Attenuation State 40 1.5 31.5dB STEP ATTENUATION (dB) 16dB 20 8dB 10 -10 -20 -30 0 0.5 1 12 - 3 2 2.5 3 3.5 4 0 0 4 8 12 16 20 24 28 32 3.5 4 4.5 3.5 4 4.5 LE ATTENUATION STATE (dB) Noise Figure vs. Frequency [1] Output P1dB vs. Temperature 28 8 23 6 4 2 B SO NOISE FIGURE (dB) 0.5 -0.5 4.5 FREQUENCY (GHz) 0 0.5 1 1.5 2 2.5 3 3.5 4 18 +25 C +85 C -40 C 13 +25 C +85 C -40 C 0 8 0 4.5 0.5 1 2 2.5 3 Output IP3 vs. Temperature O Psat vs. Temperature 1.5 FREQUENCY (GHz) FREQUENCY (GHz) 50 28 45 23 40 IP3 (dBm) Psat (dBm) VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 1.5 0.7 GHz 2.0 GHz 3.0 GHz 4.0 GHz 1 TE 0 P1dB (dBm) RELATIVE PHASE (DEG) 30 18 30 +25 C +85 C -40 C 13 35 +25 C +85 C -40 C 25 20 8 0 0.5 1 1.5 2 2.5 3 FREQUENCY (GHz) 3.5 4 4.5 0 0.5 1 1.5 2 2.5 3 FREQUENCY (GHz) [1] Max Gain State Information furnisheddelivery by Analog Devices believed orders: to be accurate and reliable. However, Corporation, no For price, delivery, andRoad, to place orders: Analog Devices, For price, and tois place Hittite Microwave 20 Alpha Chelmsford, MA 01824Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Serial Control Interface The HMC742HFLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). The serial control interrface is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches are used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and the input register is loaded with parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data changes the state of the part per truth table. Typ. Min. serial period, tSCK 100 ns Control set-up time, tCS 20 ns Control hold-time, tCH 20 ns LE setup-time, tLN 10 ns Min. LE pulse width, tLEW 10 ns Min LE pulse spacing, tLES 630 ns Serial clock hold-time from LE, tCKN 10 ns Hold Time, tPH. 0 ns Latch Enable Minimum Width, tLEN 10 ns Setup Time, tPS 2 ns O Parameter Timing Diagram (Latched Parallel Mode) Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch Enable) must be at a logic high at all times to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 20 delivery, and to place orders: Analog For price, delivery and to place Microwave Corporation, Alpha Road, Chelmsford, MADevices, 01824 Inc., responsibility is assumed by Analog Devices for its use,orders: nor for any Hittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order at www.hittite.com Phone: On-line 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT B SO LE TE For all modes of operations, the DVGA state will stay constant while LE is kept low. 12 - 4 HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz PUP Truth Table Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. 12 - 5 RF Input Power at Max Gain [1] 0 0 -31.5 0 1 0 -24 0 0 1 -16 0 1 1 Insertion Loss 1 X X 0 to -31.5 dB Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. Control Voltage Input 17.5 dBm (T = +85 °C) Controller Bias Voltage (Vdd) 5.6V Amplifier Bias Voltage (Vcc) 5.5V B SO -0.5 to Vdd +0.5V Channel Temperature 175 °C Continuous Pdiss (T = 85 °C) (derate 13.3 mW/°C above 85 °C) [2] 1.2 W Thermal Resistance [3] 75.6 °C/W -65 to +150 °C Operating Temperature -40 to +85 °C ESD Sensitivity (HBM) Class 1A [1] The maximum RF input power increases by the same amount the gain is reduced. The maximum input power at any state is no more than 28 dBm. [2] This value does not include the RF power dissipation in the attenuator. The loss in the attenuator depends on the state of the attenuator. The loss in the attenuator should be included to determine the total power dissipation in the part. [3] This value does not include the RF power dissipation in the attenuator. The thermal resistance at different states of the attenuator can be determined based on note [2] Bias Voltage Vdd (V) 0 Truth Table Digital Inputs (LE, SERIN, CLK, P/S, DO-D5, PUP1, PUP2) Storage Temperature Gain Relative to Maximum Gain LE Absolute Maximum Ratings O VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND PUP2 TE Power-On Sequence PUP1 LE Idd (Typ.) (mA) +5.0 0.12 Vs (V) Is (mA) +5.0 150 Gain Relative to Maximum Gain D5 D4 D3 D2 D1 D0 High High High High High High 0 dB High High High High High Low -0.5 dB High High High High Low High -1 dB High High High Low High High -2 dB -4 dB High High Low High High High High Low High High High High -8 dB Low High High High High High -16 dB Low Low Low Low Low Low -31.5 dB Any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Control Voltage Table State Vdd = +3V Vdd = +5V Low 0 to 0.5V @