CLC5665IM

CLC5665 Low Distortion Amplifier with Disable General Description The CLC5665 is a low cost, wideband amplifier that provides very low 2nd and 3rd harmonic distortion at 1MHz (−89/−92dBc). The great slew rate of 1800V/µs, bandwidth of 90MHz (AV = +1) and fast disable make it an excellent choice for many high speed multiplexing applications. Like all current feedback op amps, the CLC5665 allows the frequency response to be optimized (or adjusted) by the selection of the feedback resistor. For demanding video applications, the 0.1 dB bandwidth to 20MHz and differential gain/phase of 0.05%/0.05˚ make the CLC5665 the preferred component for broadcast quality NTSC and PAL video systems. The large voltage swing (28VPP) , continuous output current (85mA) and slew rate (1800V/µs) provide high fidelity signal conditioning for applications such as CCDs, transmission lines and low impedance circuits. xDSL, video distribution, multimedia and general purpose applications will benefit from the CLC5665’s wide bandwidth and disable feature. Power is reduced and the output becomes a high impedance when disabled. The wide gain range of the CLC5665 makes this general purpose op amp an improved solution for circuits such as active filters, differential-to-single-ended drivers, DAC transimpedance amplifiers and MOSFET drivers. n n n n 200ns disable to high impedance output Wide gain range −89/−92dBc HD2/HD3 (RL =500Ω) Low cost Applications n n n n n n n n xDSL driver Twisted pair driver Cable driver Video distribution CCD clock driver Multimedia systems DAC output buffers Imaging systems Non-Inverting Frequency Response Features n n n n n n 0.1dB gain flatness to 20MHz (AV = +2) 90MHz bandwidth (AV = +1) Large signal BW 25MHz 1800V/µs slew rate 0.05%/0.05˚ differential gain/phase ± 5V, ± 15V or single supplies DS015015-1 Connection Diagram DS015015-3 Pinout DIP & SOIC © 2000 National Semiconductor Corporation DS015015 www.national.com CLC5665 Low Distortion Amplifier with Disable December 2000 CLC5665 Typical Application DS015015-2 Differential Line Driver for xDSL Ordering Information Package Temperature Range Industrial Packaging Marking NSC Drawing 8-pin plastic DIP −40˚C to +85˚C CLC5665IN N08E 8-pin plastic SOIC −40˚C to +85˚C CLC5665IM M08A CLC5665IMX www.national.com 2 Lead Temperature (soldering 10 sec) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Operating Ratings Thermal Resistance Package MDIP SOIC ± 16V Supply Voltage Short Circuit Current Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range (see (Note 4)) ± VCC +150˚C −65˚C to +150˚C +300˚C (θJC) 65˚C/W 50˚C/W (θJA) 130˚C/W 145˚C/W Electrical Characteristics VCC = ± 15V, AV = +2V/V; Rf =604Ω, RL =100Ω; unless specified Symbol Parameter Ambient Temperature Conditions VCC CLC5665IN/IM Typ +25˚C Min/Max Ratings (Note 2) +25˚C 0 to 70˚C Units −40 to 85˚C Frequency Domain Response Small-Signal Bandwidth (AV = +1) Small-Signal Bandwidth VOUT < 1.0VPP ± 15 VOUT < 1.0VPP ± 15 ±5 ± 15 ±5 VOUT < 1.0VPP 0.1dB Bandwidth VOUT < 1.0VPP Large-Signal Bandwidth VOUT < 1.0VPP VOUT < 10VPP VOUT < 1.0VPP Gain Flatness 90 MHz 70 MHz 50 MHz 20 MHz 15 MHz 25 MHz dB Peaking DC to 10MHz 0.03 Rolloff DC to 20MHz 0.1 dB Linear Phase Deviation DC to 20MHz 0.7 deg Differential Gain RL = 150Ω, 4.43MHz 0.05 % ± 15 ±5 ± 15 ±5 RL = 150Ω, 4.43MHz Differential Phase RL = 150Ω, 4.43MHz RL = 150Ω, 4.43MHz 0.05 % 0.05 deg 0.1 deg Time Domain Response Rise and Fall Time Settling Time to 0.05% 2V Step 5 ns 10V Step 10 ns 2V Step 35 ns Overshoot 2V Step 5 % Slew Rate 20V Step 1800 V/µs 2nd Harmonic DIstortion 1VPP,1MHz, RL = 500Ω −89 dBc 3rd Harmonic Distortion 2VPP,1MHz, RL = 500Ω −92 dBc Input Voltage Noise > 1MHz 3.0 nV/ Non-Inverting Input Current Noise > 1MHz 3.2 pA/ Inverting Input Current Noise > 1MHz 15 pA/ Distortion And Noise Response DC Performance ± 15 Input Offset Voltage (Note 3) Average Drift 1.0 25 3 7.5 9.0 10.0 mV µV/˚C www.national.com CLC5665 Absolute Maximum Ratings (Note 1) CLC5665 Electrical Characteristics (Continued) VCC = ± 15V, AV = +2V/V; Rf =604Ω, RL =100Ω; unless specified Symbol VCC Typ Non-Inverting ± 15, ±5 3 Inverting ± 15, ±5 Parameter Conditions Min/Max Ratings (Note 2) Units DC Performance Input Bias Current (Note 3) Average Drift Input Bias Current (Note 3) 20 20 20 20 20 20 10 Average Drift 3 µA nA/˚C 10 µA nA/˚C Power Supply Rejection Ratio DC 60 55 50 50 dB Common-Mode Rejection Ratio DC 60 55 50 50 dB Supply Current (Note 3) RL = ∞ 11,8.5 12 14 15 mA Disabled (Note 3) RL = ∞ 1.5 2.5 2.5 2.5 mA ns ± 15, ±5 ± 15, ±5 Switching Performance Turn on Time 400 500 550 550 Turn Off Time (Note 5) 200 800 800 800 ns Off Isolation 10MHz 59 56 56 56 dB High Input Voltage VIH 11.8 12.5 12.7 V 1.8 2.5 2.7 V 10.8 10.5 10.0 V 0.8 0.6 0.1 V Non-Inverting Input Resistance 8.0 3.0 2.5 1.7 MΩ Non-Inverting Input Capacitance 0.5 1.0 1.0 1.0 pF ± 12.5 ± 2.5 ± 14 ± 4.0 ± 85 ± 12.3 ± 2.3 ± 13.7 ± 3.9 ± 60 ± 12.1 ± 2.2 ± 13.7 ± 3.8 ± 50 ± 11.8 ± 1.9 ± 13.6 ± 3.7 ± 45 Ω Low Input Voltage ± 15 ±5 ± 15 ±5 VIL Miscellaneous Performance Input Voltage Range ± 15 ±5 ± 15 ±5 Common Mode Common Mode Output Voltage Range RL = ∞ RL = ∞ Output Current V V V mA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 125mA. Note 5: To > 50dB attenuation @10MHz. www.national.com 4 (VCC = ± 15V, AV = +2V/V; Rf = 604Ω, RL = 100;Ω unless specified) Non-Inverting Frequency Response Av = 1 Rf = 698 0 -45 Av = 50 -90 Av = 2 Av = 50 Rf = 500 -135 Av = 10 1 10 Av = -10 Rf = 500 Av = -2 Rf = 500 Phase 0 -45 Av = -50 -90 Av = -10 1 -135 Av = -2 Av = -50 Rf = 2.5k -180 100 Phase (deg) Phase Av = 2 Rf = 604 Av = 1 Phase (deg) Av = 10 Rf = 100 Av = -1 Rf = 500 Gain Magnitude (1dB/div) Gain Magnitude (1dB/div) Inverting Frequency Response -180 Av = -1 10 Frequency (MHz) 100 Frequency (MHz) DS015015-4 Frequency Response vs. Load DS015015-5 Open-Loop Transimpedance Gain (Zs) 130 RL = 1k 0 -45 RL = 50 -90 RL = 100 10 Gain (20 log) RL = 1k Phase (deg) RL = 100 1 0 110 RL = 50 Phase Gain 120 20 100 40 90 60 Phase 80 80 70 100 60 120 -135 50 140 -180 40 160 30 0.0001 100 0.001 Frequency (MHz) 0.01 0.1 1 10 Phase (deg) Magnitude (1dB/div) Gain 100 Frequency (MHz) DS015015-6 Flatness Gain and Linear Phase DS015015-7 Equivalent Input Noise Magnitude (0.1dB/div) Phase (0.2ϒ/div) Phase Inverting Current 14.8pA/√Hz 10 Non-Inverting Current 3.2pA/√Hz Voltage 3.0nV/√Hz Noise Current (pA/√Hz) Gain Noise Voltage (nV/√Hz) 100 1 0 4 8 12 16 20 0.1k Frequency (MHz) 1k 10k 100k 1M 10M 100M Frequency (MHz) DS015015-8 DS015015-9 5 www.national.com CLC5665 Typical Performance Characteristics (VCC = ± 15V, AV = +2V/V; Rf = 604Ω, RL = 100;Ω unless specified)) (Continued) PSRR, CMRR and Closed Loop RO Small Signal Output (0.5V/div) Large Signal Output (2V/div) Signal Pulse Response Large Signal Small Signal Time (20ns/div) DS015015-10 DS015015-11 Differential Gain and Phase (3.58MHz) Short Term Settling Time 0.2 0.30 1 2V output step 0.15 Gain Negative Sync 0.24 0.04 0.18 0.12 Phase Negative Sync Phase (deg) Phase Positive Sync 0.06 Settling Error (%) 0.08 Gain (%) 0.1 0.05 -0.05 -0.1 0.06 0.02 -0.15 Gain Positive Sync -0.2 0.03 0 1 2 Short Term 0 3 Time (10ns/div) 4 DS015015-13 Number of 150Ω Loads DS015015-12 IBI, IBN, VOS vs. Temperature 2-Tone, 3rd Order Intermodulation Intercept 60 50 Intercept (+dBm) CLC5665 Typical Performance Characteristics 40 30 50Ω 20 Pout 50Ω 750Ω 750Ω 10 106 107 Frequency (MHz) DS015015-14 www.national.com DS015015-15 6 (VCC = ± 15V, AV = +2V/V; Rf = 604Ω, RL = 100;Ω unless specified)) (Continued) −1dBm Compression to Load Harmonic Distortion vs. Frequency Compression Point (dBm) 26 24 22 20 18 16 14 Load 12 50Ω Vin 10 50Ω 698Ω 698Ω 8 6 0 5 10 15 20 25 30 35 40 45 50 Frequency (MHz) DS015015-16 DS015015-17 Harmonic Distortion vs. Frequency DS015015-18 7 www.national.com CLC5665 Typical Performance Characteristics CLC5665 Application Division General Design Considerations Enable Disable The CLC5665 is a general purpose current-feedback amplifier for use in a variety of small- and large-signal applications. Use the feedback resistor to fine tune the gain flatness and −3dB bandwidth for any gain setting. National provides information for the performance at a gain of +2 for small and large signal bandwidths. The plots show feedback resistor values for selected gains. Gain Use the following equations to set the CLC5665’s noninverting or inverting gain: Non − Inverting Gain = 1 + Inverting Gain = > 12.7V > 2.7V < 10.0V < 0.8V The amplifier is enabled with pin 8 left open due to the 2kΩ pull-up resistor, shown in Figure 2. +Vcc 2kΩ Rf Rg To CLC5665 Bias network -R f Rg 8kΩ -Vcc Pin 8 DISABLE Choose the resistor values for non-inverting or inverting gain by the following steps. DS015015-21 FIGURE 2. Pin 8 Equivalent Disable Circuit Vin + Rin Rs CLC5665 Open-collector or CMOS interfaces are recommended to drive pin 8. The turn on and off time depends on the speed of the digital interface. The equivalent output impedance when disabled is shown in Figure 3. With Rg connected to ground, the sum of Rf and Rg dominates and reduces the disabled output impedance. To raise the output impedance in the disabled state, connect the CLC5665 as a unity-gain voltage follower by removing Rg. Current-feedback op amps need the recommended Rf in a unity-gain follower circuit. For high density circuit layouts consider using the dual CLC431 (with disable) or the dual CLC432 (without disable). Vo Rf Rg DS015015-20 FIGURE 1. Component Identification 1) Select the recommended feedback resistor Rf (refer to plot in the plot section entitled Rf vs. Gain). Equivalent Impedance in Disable Vin + 2) Choose the value of Rg to set gain. 3) Select Rs to set the circuit output impedance. 4) Select Rin for input impedance and input bias. 300kΩ Vout High Gains Current feedback closed-loop bandwidth is independent of gain-bandwidth-product for small gain changes. For larger gain changes the optimum feedback resister Rf is derived by the following: Rf = 724Ω - 60Ω · (AV) 8pF - Rg As gain is increased, the feedback resistor allows bandwidth to be held constant over a wide gain range. For a more complete explanation refer to application note OA-25 Stability Analysis of Current-Feedback Amplifiers. Resistors have varying parasitics that affect circuit performance in high speed design. For best results, use leaded metal film resistors or surface mount resistors. A SPICE model for the CLC430 is available to simulate overall circuit performance. Enable/Disable Function The CLC430 amplifier features an enable/disable function that changes the output and inverting input from low to high impedance. The pin 8 enable/disable logic levels are as follows: VCC ± 15V ± 5V www.national.com Rf DS015015-22 8 Applications Circuits (Continued) Level Shifting The circuit shown in Figure 5 implements level shifting by AC coupling the input signal and summing a DC voltage. The resistor Rin and the capacitor C set the high pass break frequency. The amplifier closed-loop bandwidth is fixed by the selection of Rf. The DC and AC gains for circuit of Figure 5 are different. The AC gain is set by the ratio of Rf and Rg. And the DC gain is set by the parallel combination of Rg and R2. 1M 100k Zout (Ω) 10k 1k   R   Rf  f Vout = Vinac 1 +   − VinDC     R2    Rg R2   100 10 + Vin AC 1 1 10 C 100 Vout Rin CLC5665 Frequency (MHz) - DS015015-23 FIGURE 3. Equivalent Disabled Output Impedance Vin DC 2nd and 3rd Harmonic Distortion To meet low distortion requirements, recognize the effect of the feedback resistor. Increasing the feedback resistor will decrease the loop gain and increase distortion. Decreasing the load impedance increases 3rd harmonic distortion more than 2nd. Differential Gain and Differential Phase The CLC5665 has low DG and DP errors for video applications. Add an external pulldown resistor to the CLC5665’s output to improve DG and DP as seen in Figure 4. A 604Ω RP will improve DG and DP to 0.01% and 0.02˚. Rg DS015015-26 FIGURE 5. Level Shifting Circuit Multiplexing Multiple signal switching is easily handled with the disable function of the CLC5665. Board trace capacitance at the output pin will affect the frequency response and switching transients. To lessen the effects of output capacitance place a resistor (Ro) within the feedback loop to isolate the outputs as shown in Figure 6. To match the mux output impedance to a transmission line, add a resistor (Rs) in series with the output. Add Rp to improve DG and DP Vin + Vout Rin CLC5665 Rf Rg Rs - - Rp Rg Rf R2 Ro CLC5665 Vin1 + Rf Rs DIS1 Rin Vin2 DIS2 + Ro -Vcc RL CLC5665 Rin DS015015-24 Vout - FIGURE 4. Improved DG and DP Video Amplifier Printed Circuit Layout To get the best amplifier performance careful placement of the amplifier, components and printed circuit traces must be observed. Place the 0.1µF ceramic decoupling capacitors less than 0.1″ (3mm) from the power supply pins. Place the 6.8µF tantalum capacitors less than 0.75″ (20mm) from the power supply pins. Shorten traces between the inverting pin and components to less than 0.25″ (6mm). Clear ground plane 0.1″ (3mm) away from pads and traces that connect to the inverting, non-inverting and output pins. Do not place ground or power plane beneath the op amp package. National provides literature and evaluation boards 730013 DIP or 730027 SOIC illustrating the recommended op amp layout. Rf Rg DS015015-27 FIGURE 6. Output Connection for Multiplexing Circuits Differential Line Driver With Load Impedance Conversion The circuit shown in Figure 7, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5665’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5665. The line’s characteristic impedance 9 www.national.com CLC5665 Application Division CLC5665 Application Division Full Duplex Cable Driver (Continued) The circuit shown in Figure 8 below, operates as a full duplex cable driver which allows simultaneous transmission and reception of signals on one transmission line. The circuit on either side of the transmission line uses are CLC5665 as a cable driver, and the second CLC5665 as a receiver. VoA is an attenuated version of VinA, while VoB is a attenuated version of VinB. is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven. Rf2 Rg2 Vd/2 Vin + Rt1 CLC5665 - - CLC5665 Rf1 -Vd/2 1:n Req + Io Zo RL UTP + Vo - VinA + Z0 Rm1 + Rm1 CLC5665 Rt1 CLC5665 - - VinB Rt1 Rm/2 Rt2 Rg1 Rm/2 Rf1 FIGURE 7. Differential Line Driver with Load Impedance Conversion Rg2 Rf2 DS015015-28 Rg2 - VoB Rf2 - CLC5665 Rt2 + Set up the CLC5665 as a difference amplifier. Vd is determined by: Rf1 Rt2 CLC5665 VoA + DS015015-34 FIGURE 8. Full Duplex Cable Driver  Vd R  R = 2 ⋅ 1 + f1  = 2 ⋅ f2 Vin R g2  R g1  Rm1 is used to match the transmission line. Rf2 and Rg2 set the DC gain of the CLC5665, which is used in a difference mode. Rt2 provides good CMRR and DC offset. The transmitting CLC5665’s are shown in a unity gain configuration because they consume the least power of any gain, for a given load. For proper operation we need Rf2 = Rg2. The receiver output voltages are: Make the best use of the CLC5665’s output drive capability as follows: VoutA(B) ≈ VinA(B) ⋅ A + where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the maximum Output Current. Match the line’s characteristic impedance: VinB(A)  Z o(5665) (jω )  R ⋅ 1 − f2 +  2 Rm1   R g2 where A is the attenuation of the cable, Zo(5665)(jω) is the ouput impedance of the CLC5665, and |Zo(5665)(jω)|