CLC5623IM

CLC5623 Triple, High Output, Video Amplifier June 1999 N CLC5623 Triple, High Output, Video Amplifier General Description The CLC5623 has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (3.0mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear-phase response up to one half of the -3dB frequency. The CLC5623 offers 0.1dB gain flatness to 15MHz and differential gain and phase errors of 0.06% and 0.06°. These features are ideal for professional and consumer video applications. The CLC5623 offers superior dynamic performance with a 148MHz small-signal bandwidth, 370V/µs slew rate and 4.4ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high-speed performance make the CLC5623 well suited for many battery-powered personal communication/computing systems. The ability to drive low-impedance, highly capacitive loads, with minimum distortion, makes the CLC5623 ideal for cable applications. The CLC5623 will drive a 100Ω load with only -78/-94dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -82/-96dBc second/third harmonic distortion. The CLC5623 can also be used for driving differential-input stepup transformers for applications such as Asynchronous Digital Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber Lines (HDSL). When driving the input of high-resolution A/D converters, the CLC5623 provides excellent -86/-96dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast settling time. Features s s s s s s s s s 130mA output current 0.06%, 0.06° differential gain, phase 3.0mA/ch supply current 148MHz bandwidth (Av = +2) -86/-96dBc HD2/HD3 (1MHz) 18ns settling to 0.05% 370V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V or ±5V supplies Video line driver ADSL/HDSL driver Coaxial cable driver UTP differential line driver Transformer/coil driver High capacitive load driver Portable/battery-powered applications Differential A/D driver Maximum Output Voltage vs. RL 10 9 Applications s s s s s s s s Output Voltage (Vpp) 8 7 6 5 4 3 2 1 10 100 1000 Vs = +5V VCC = ±5V RL (Ω) Typical Application Single Supply Cable Driver +5V 6.8µF + Pinout DIP & SOIC NC NC 1 -+ -+ +- 14 OUT2 13 -IN2 12 +IN2 11 -Vs 10 +IN3 9 8 -IN3 OUT3 2 3 4 5 6 7 Vin 0.1µF 5kΩ 5kΩ 5 6 1/3 CLC5623 + 4 0.1µF 7 75Ω 0.1µF 10m of 75Ω Coaxial Cable NC Vo 75Ω +Vs +IN1 -IN1 OUT1 - 11 1kΩ 1kΩ 0.1µF © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com +5V Characteristics (A PARAMETERS Ambient Temperature 1 v = +2, Rf = 750Ω, Rf = 1kΩ (PDIP), Rf = 750Ω (SOIC),Vs = +5V ,Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) CONDITIONS CLC5623IN TYP +25°C 107 14 0 0.3 1.0 0.03 0.08 4.5 17 11 280 -76 -85 -63 -88 -96 -65 4.9 6.6 11.1 -51 -49 1 8 6 40 6 25 48 45 3.0 0.86 1.8 4.2 0.8 4.0 1.0 4.1 0.9 100 70 MIN/MAX RATINGS +25°C 0 to 70°C -40 to 85°C 85 13 0.5 0.7 2.0 – – 6.0 25 15 195 – – -58 – – -62 5.9 8.5 14.7 – – 4 – 18 – 14 – 45 43 3.4 0.50 2.75 4.1 0.9 3.9 1.1 4.0 1.0 80 105 75 10 0.9 0.8 2.4 – – 6.4 40 18 165 – – -56 – – -60 6.4 9.3 15.8 – – 6 – 22 – 16 – 43 41 3.6 0.45 2.75 4.1 0.9 3.9 1.1 4.0 1.0 65 105 75 10 0.9 0.8 2.4 – – 6.8 60 18 150 – – -56 – – -60 6.4 9.3 15.8 – – 6 – 24 – 17 – 43 41 3.6 0.45 2.75 4.0 1.0 3.8 1.2 3.9 1.1 40 140 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 1.5Vpp -0.1dB bandwidth Vo = 0.5Vpp gain peaking 1MHz crosstalk (input referred) 10MHz, 1Vpp crosstalk, all hostile (input referred) 10MHz, 1Vpp STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current per channel DC DC RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) input voltage range, High input voltage range, Low output voltage range, High RL = 100Ω output voltage range, Low RL = 100Ω output voltage range, High RL = ∞ output voltage range, Low RL = ∞ output current output resistance, closed loop DC B Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes A) J-level: spec is 100% tested at +25°C. B) The short circuit current can exceed the maximum safe output current. 1) Vs = VCC - VEE Absolute Maximum Ratings supply voltage (VCC - VEE) output current (see note C) common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) 147 Reliability Information Transistor Count +14V 140mA VEE to VCC +150°C -65°C to +150°C +300°C http://www.national.com 2 ±5V Characteristics (A PARAMETERS Ambient Temperature v = +2, Rf = 1kΩ (PDIP), Rf = 750Ω (SOIC), RL = 100Ω, VCC = ±5V, unless specified) CONDITIONS CLC5623IN TYP +25°C 148 72 15 0 0.1 0.08 0.06 0.06 4.4 18 19 370 -78 -86 -65 -94 -96 -73 4.9 6.6 11.1 -51 -49 1 10 8 40 9 30 48 47 3.2 0.88 1.45 ±4.2 ±3.8 ±4.0 130 60 GUARANTEED MIN/MAX +25°C 0 to 70°C -40 to 85°C 110 55 12 0.5 0.3 1.6 0.12 0.1 5.8 25 21 280 – – -60 – – -60 5.9 8.5 14.7 – – 6 – 18 – 24 – 45 43 3.8 0.52 2.15 ±4.1 ±3.6 ±3.8 100 90 105 52 9 0.9 0.5 2.0 – – 6.2 40 23 260 – – -58 – – -58 6.4 9.3 15.8 – – 7 – 23 – 28 – 43 41 4.0 0.47 2.15 ±4.1 ±3.6 ±3.8 80 90 85 52 9 1.3 0.5 2.0 – – 6.8 60 24 240 – – -58 – – -58 6.4 9.3 15.8 – – 8 – 25 – 28 – 43 41 4.0 0.47 2.15 ±4.0 ±3.5 ±3.7 50 120 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 1.5Vpp Vo = 4.0Vpp -0.1dB bandwidth Vo = 1.0Vpp gain peaking 1MHz crosstalk (input referred) 10MHz, 1Vpp crosstalk, all hostile (input referred) 10MHz, 1Vpp STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current (per channel) DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) common-mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop DC B Notes B) The short circuit current can exceed the maximum safe output current. Model CLC5623IN CLC5623IM CLC5623IMX Ordering Information Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C Description 8-pin PDIP 8-pin SOIC 8-pin SOIC tape and reel Package Thermal Resistance Package Plastic (IN) Surface Mount (IM) θJC 60°C/W 55°C/W θJA 110°C/W 125°C/W 3 http://www.national.com +5V Typ. Perform. (A Frequency Response Normalized Magnitude (1dB/div) Vo = 0.5Vpp PDIP Package Gain Av = +2 Rf = 750Ω v = +2, Rf = 1kΩ (PDIP), Rf = 750Ω (SOIC), RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Inverting Frequency Response Av = +1 Rf = 1kΩ Frequency Response vs. RL Vo = 0.5Vpp PDIP Package RL = 100Ω RL = 1kΩ Gain Normalized Magnitude (1dB/div) Vo = 0.5Vpp PDIP Package Gain Av = -2 Rf = 499Ω Phase (deg) Phase (deg) Phase 0 -90 -180 -270 -360 -450 100M Phase Magnitude (1dB/div) Phase (deg) Av = -1 Rf = 549Ω 180 135 Av = -5 Rf = 402Ω Av = -10 Rf = 250Ω Phase RL = 25Ω 0 -90 -180 -270 -360 -450 Av = +5 Rf = 402Ω Av = +10 Rf = 200Ω 90 45 0 -45 100M 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo PDIP Package Frequency (Hz) Gain Flatness & Linear Phase 0 Gain Frequency (Hz) Open Loop Transimpedance Gain, Z(s) 140 120 Phase Gain 225 180 Magnitude (0.05dB/div) Magnitude (1dB/div) Vo = 0.1Vpp -0.2 Magnitude (dBΩ) Phase (deg) Phase (deg) Phase Vo = 1Vpp Vo = 2Vpp -0.4 -0.6 -0.8 -1.0 100 80 60 40 1k 10k 100k 1M 10M 135 90 45 0 100M 1M 10M 100M 0 10 20 30 Frequency (Hz) PSRR & CMRR 60 3.3 PSRR CMRR Frequency (MHz) Equivalent Input Noise 12.5 -50 Frequency (Hz) 2nd & 3rd Harmonic Distortion Vo = 2Vpp 2nd RL = 100Ω 3rd RL = 100Ω Noise Voltage (nV/√Hz) PSRR & CMRR (dB) 50 40 30 20 10 0 1k 3.25 3.2 3.15 3.1 3.05 3.0 Noise Current (pA/√Hz) Inverting Current 11pA/√Hz -60 10.5 Distortion (dBc) -70 -80 2nd RL = 1kΩ Voltage 3.08nV/√Hz Non-Inverting Current 7.5pA/√Hz 8.5 -90 -100 1M 3rd RL = 1kΩ 6.5 10k 100k 1M 10M 10k 100k 1M 10M 100M 10M Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 25Ω -40 -45 3rd, 10MHz 2nd, 10MHz Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 100Ω -50 2nd, 10MHz Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 -60 Distortion (dBc) Distortion (dBc) Distortion (dBc) -50 -55 -60 -65 -70 -75 -80 0 3rd, 1MHz 2nd, 1MHz -60 -70 3rd, 10MHz 3rd, 10MHz 2nd, 10MHz -70 -80 -90 2nd, 1MHz 2nd, 1MHz -80 -90 3rd, 1MHz -100 -110 3rd, 1MHz -100 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 0.5 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Large & Small Signal Pulse Response 50 Output Amplitude (Vpp) Output Impedance vs. Frequency 0 Output Amplitude (Vpp) IBI, IBN, VIO vs. Temperature 4 Output Voltage (0.5V/div) 40 30 20 10 0 Offset Voltage VIO (mV) Large Signal Output Impedance (Ω) 3 IBI IBI, IBN (µA) Small Signal -0.5 IBN 2 VIO 1 -1 1k 10k 100k 1M 10M 100M -60 -20 20 60 100 140 0 Time (10ns/div) Frequency (Hz) Temperature (°C) http://www.national.com 4 ±5V Typical Performance (A Frequency Response Normalized Magnitude (1dB/div) Vo = 1.5Vpp PDIP Package Gain Av = +1 Rf = 750Ω Av = +2 Rf = 750Ω v = +2, Rf = 1kΩ (PDIP), RL = 100Ω, VCC = ±5V, unless specified) Inverting Frequency Response Normalized Magnitude (1dB/div) Vo = 1.5Vpp PDIP Package Gain Av = -10 Rf = 250Ω Av = -5 Rf = 402Ω Frequency Response vs. RL Vo = 1.5Vpp PDIP Package RL = 1kΩ Magnitude (1dB/div) Phase (deg) Phase (deg) Phase (deg) Gain RL = 100Ω Phase Phase 0 -45 -90 -135 -180 -225 100M Phase 180 135 90 45 0 -45 100M 0 -90 RL = 25Ω Av = +10 Rf = 200Ω Av = +5 Rf = 402Ω Av = -2 Rf = 449Ω Av = -10 Rf = 250Ω -180 -270 -360 -450 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo PDIP Package Vo = 0.1Vpp Vo = 1Vpp Frequency (Hz) Gain Flatness & Linear Phase Phase Frequency (Hz) Small Signal Pulse Response 0 Magnitude (0.02dB/div) Vo = 1.5Vpp PDIP package Gain -0.4 -0.6 -0.8 -1.0 Vo = 5Vpp Vo = 2Vpp Amplitude (0.2V/div) Magnitude (1dB/div) -0.2 Av = +1 Phase (deg) Av = -1 1M 10M 100M 0 5 10 15 20 25 30 Time (10ns/div) Frequency (Hz) Large Signal Pulse Response -0.01 f = 3.58MHz Av = +2 Frequency (MHz) Differential Gain & Phase -0.02 Gain Pos Sync 2nd & 3rd Harmonic Distortion -60 Vo = 2Vpp 2nd RL = 100Ω -0.02 -0.03 -0.04 3rd RL = 100Ω Amplitude (0.5V/div) -0.04 -0.05 Gain Neg Sync Phase Neg Sync -0.08 -0.1 -0.12 Distortion (dBc) -0.06 -70 Phase (deg) Gain (%) -80 3rd RL = 1kΩ 2nd RL = 1kΩ -0.06 Av = -2 Phase Pos Sync -90 -0.07 -0.08 -0.14 -0.16 1 2 3 4 -100 1 Time (20ns/div) 2nd & 3rd Harmonic Distortion, RL = 25Ω -50 2nd, 10MHz 10 Number of 150 Ω Loads 2nd & 3rd Harmonic Distortion, RL = 100Ω -50 2nd, 10MHz Frequency (MHz) 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 -60 3rd, 10MHz -60 -60 Distortion (dBc) Distortion (dBc) Distortion (dBc) 3rd, 10MHz -70 -80 -90 3rd, 1MHz 2nd, 1MHz 3rd, 10MHz -70 -80 -90 3rd, 1MHz 2nd, 1MHz -70 2nd, 1MHz -80 -90 2nd, 10MHz 3rd, 1MHz -100 -110 0 1 -100 -110 -100 -110 2 3 4 5 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 Output Amplitude (Vpp) Short Term Settling Time 0.2 0.15 0.2 0.15 Output Amplitude (Vpp) Long Term Settling Time 1.6 Output Amplitude (Vpp) IBI, IBN, VOS vs. Temperature 7 IBI Offset Voltage VOS(mV) 1.4 1.2 1.0 0.8 0.6 5 3 1 -1 -3 Vo (% Output Step) Vo (% Output Step) 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1 10 100 1000 10000 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1µ 10µ 100µ 1m 10m IBI, IBN (µA) VOS IBN 0.4 -60 -20 20 60 100 -5 Time (ns) Time (s) Temperature (°C) 5 http://www.national.com ±5V Typical Channel Matching Performance (A Channel Matching -20 PDIP Package Vo = 1Vpp Channel 3 v = +2, Rf = 1kΩ (PDIP), RL = 100Ω, VCC = ±5V, unless specified) Pulse Crosstalk Active Output Channel Input Referred Crosstalk Inactive Channel Amplitude (20mV/div) Magnitude (0.5dB/div) Active Channel Amplitude (0.2V/div) -35 Magnitude (dB) Channel 2 Inactive Output Channel 2 -45 -55 -65 -75 Inactive Output Channel 3 Channel 1 Active Output Channel 1 1M 10M 100M 1M 10M 100M Time (20ns/div) Frequency (Hz) Frequency (Hz) CLC5623 OPERATION The CLC5623 is a current feedback amplifier built in an advanced complementary bipolar process. The CLC5623 operates from a single 5V supply or dual ±5V supplies. Operating from a single supply, the CLC5623 has the following features: s s s Vo = Vin where: s s s Av Rf 1+ Z(jω ) Equation 1 Provides 100mA of output current while consuming 15mW of power Offers low -85/-96dB 2nd and 3rd harmonic distortion Provides BW > 100MHz and 1MHz distortion < -70dBc at Vo = 2Vpp Av is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC5623’s open loop transimpedance gain Z( jω ) is the loop gain Rf s The CLC5623 performance is further enhanced in ±5V supply applications as indicated in the ±5V Electrical Characteristics table and ±5V Typical Performance plots. Current Feedback Amplifiers Some of the key features of current feedback technology are: s Independence of AC bandwidth and voltage gain s Inherently stable at unity gain s Adjustable frequency response with feedback resistor s High slew rate s Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: s s s s s Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity Refer to the Feedback Resistor Selection section for more details on selecting a feedback resistor value. CLC5623 DESIGN INFORMATION Single Supply Operation (VCC = +5V, VEE = GND) The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5623 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. http://www.national.com 6 DC Coupled Single Supply Operation Figures 1 and 2 show the recommended non-inverting and inverting configurations for input signals that remain above 0.8V DC. VCC Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. VCC 6.8µF + VCC 2 Vin Cc Rg R 5 6 6.8µF + 1/3 CLC5623 + 4 0.1µF 7 Vo - 11 Rf Vin Rt Vcm 5 6 1/3 CLC5623 + 4 0.1µF 7 R Vo RL Vcm  R Vo = Vin  − f  + 2.5  Rg  low frequency cutoff = 1 2πR gC c - 11 Rf Rg Vcm R Vo = A v = 1+ f Vin Rg Figure 4: AC Coupled Inverting Configuration Dual Supply Operation The CLC5623 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 5 and 6. VCC 6.8µF + Figure 1: Non-Inverting Configuration VCC 6.8µF + Note: Rb, provides DC bias for non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. 5 Rb Vin Vcm Rt Vcm Rg 6 1/3 CLC5623 + 4 0.1µF 7 Vo RL Vcm Vin Rt 5 - 11 Rf 6 1/3 CLC5623 + 4 0.1µF 7 Vo - 11 Rf 0.1µF + R Vo = Av = − f Vin Rg Select Rt to yield desired Rin = Rt || Rg Rg R Vo = A v = 1+ f Vin Rg Figure 2: Inverting Configuration AC Coupled Single Supply Operation Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VCC 6.8µF + 6 6.8µF VEE Figure 5: Dual Supply Non-Inverting Configuration VCC 6.8µF + Rb 5 1/3 CLC5623 + 4 0.1µF 7 Vo Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt || Rg. Vin Rg - 11 Rf 0.1µF + Vin Cc VCC 2 R 5 R 6 1/3 CLC5623 + 4 0.1µF 7 Rt Vo R Vo = Av = − f Vin Rg VEE - 11 Rf 6.8µF  R Vo = Vin 1 + f  + 2.5 Rg   low frequency cutoff = Rg C 1 R , where: Rin = 2πRinC c 2 R >> R source Figure 6: Dual Supply Inverting Configuration Figure 3: AC Coupled Non-Inverting Configuration 7 http://www.national.com Magnitude (0.5dB/div) Feedback Resistor Selection The feedback resistor, Rf, affects the loop gain and frequency response of a current feedback amplifier. Optimum performance of the CLC5623, at a gain of +2V/V, is achieved with Rf equal to 750Ω for the SOIC package and 1kΩ for the PDIP package. The frequency response plots in the Typical Performance sections illustrate the recommended Rf for several gains. These recommended values of Rf provide the maximum bandwidth with minimal peaking. Within limits, Rf can be adjusted to optimize the frequency response. s Figure 8 illustrates the channel matching performance of the surface mount version of the CLC5623. Once again, the surface mount package performs better. If optimum performance is desired, use the surface mount version of the CLC5623. Channel 3 Channel 2 Channel 1 s Decrease Rf to peak frequency response and extend bandwidth Increase Rf to roll off frequency response and compress bandwidth Av = 2, Rf =750Ω Vo = VCC = ±5V SOIC Package As a rule of thumb, if the recommended Rf is doubled, then the bandwidth will be cut in half. Unity Gain Operation The recommended Rf for unity gain (+1V/V) operation is 750Ω (for the PDIP package). Rg is left open. Parasitic capacitance at the inverting node may require a slight increase in Rf to maintain a flat frequency response. Load Termination The CLC5623 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Additional parasitics and limitations on decoupling in the CLC5623IN combine to provide a lower level of performance than the CLC5623IM. The specifications in the Electrical Characteristics tables are based on the performance of the DIP package (CLC5623IN). For optimum performance, use the CLC5623IM (SOIC package). Proper supply decoupling and board layout are critical factors for obtaining optimum performance of the CLC5623IN. Board layout is less critical for the SOIC package. Use the evaluation boards as a guide to proper layout. Figure 7 illustrates the frequency response versus output amplitude for the CLC5623IM. Compare the Frequency Response vs. Vo plot, in the ±5V Typical Performance section, with Figure 7. Notice that gain flatness and bandwidth improve when the SOIC package is used. 1M 10M 100M Frequency (Hz) Figure 8: Channel Matching Perfomance Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5623 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 9, gives the recommended series resistance value for optimum flatness at various capacitive loads. Vo = 1Vpp Magnitude (1dB/div) CL = 10pF Rs = 68.1Ω CL = 100pF Rs = 17.4Ω CL = 1000pF Rs = 6.7Ω + - Rs 1k CL 1k 1k 1M 10M 100M Frequency (Hz) Figure 9: Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 10 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-inverting gain applications: s s s Magnitude (1dB/div) Vo = 0.1Vpp Vo = 1Vpp Vo = 1.5Vpp Vo = 2Vpp Av = 2, Rf =750Ω Vo = VCC = ±5V SOIC Package Vo = 2.5Vpp 1M 10M 100M Frequency (Hz) Connect Rg directly to ground. Make R1, R2, R6, and R7 equal to Zo. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Figure 7: Frequency Response vs. Vo http://www.national.com 8 R1 V1 + R4 V2 + - Z0 R3 R2 C6 1/3 CLC5623 + - Z0 R6 Vo R7 Z0 Rg R5 Rf Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5623 (CLC730075-DIP, CLC730074-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: s Figure 10: Transmission Line Matching Inverting gain applications: s s s Connect R3 directly to ground. Make the resistors R4, R6, and R7 equal to Zo. Make R5 II Rg = Zo. s The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. Power Dissipation Follow these steps to determine the power consumption of the CLC5623: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP and SOIC packages can dissipate at a given temperature is illustrated in Figure 11. The power derating curve for any CLC5623 package can be derived by utilizing the following equation: (175° − Tamb ) θ JA where Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W 1.0 0.8 IN IM s s s s Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information A data sheet is available for the CLC730075/ CLC730074 evaluation boards. The evaluation board data sheet provides: s s s Evaluation board schematics Evaluation board layouts General information about the boards The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: s s Power (W) 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 120 140 160 180 s Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Ambient Temperature (°C) Figure 11: Power Derating Curves 9 http://www.national.com Application Circuits Single Supply Cable Driver The typical application shown below shows one of the CLC5623 amplifiers driving 10m of 75Ω coaxial cable. The CLC5623 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. +5V 6.8µF + Gain = K = 1 + Rf Rg 1 R1R 2C1C2 Corner frequency = ω c = Q= 1 R 2C 2 + R1C1 R1C2 R1C1 + (1− K) R 2C1 R 2C 2 Vin 0.1µF 5kΩ 5kΩ 5 For R1 = R 2 = R and C1 = C2 = C 7 6 1/3 CLC5623 + 4 0.1µF 75Ω 0.1µF 10m of 75Ω Coaxial Cable Vo 75Ω ωc = Q= 1 RC - 11 1kΩ 1kΩ 0.1µF 1 (3 − K) Figure 15: Design Equations Figure 12: Single Supply Cable Driver Vin = 10MHz, 0.5Vpp This example illustrates a lowpass filter with Q = 0.707 and corner frequency fc = 10MHz. A Q of 0.707 was chosen to achieve a maximally flat, Butterworth response. Figure 16 indicates the filter response. 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1M 10M 100M 100mV/div 20ns/div Figure 13: Response After 10m of Cable Single Supply Lowpass Filter Figures 14 and 15 illustrate a lowpass filter and design equations. The circuit operates from a single supply of +5V. The voltage divider biases the non-inverting input to 2.5V. And the input is AC coupled to prevent the need for level shifting the input signal at the source. Use the design equations to determine R1, R2, C1, and C2 based on the desired Q and corner frequency. +5V 0.1µF R2 C2 100pF 5 6 Magnitude (dB) Frequency (Hz) Figure 16: Lowpass Response Differential Line Driver With Load Impedance Conversion The circuit shown in the Typical Application schematic on the front page and in Figure 17, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5623’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5623. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven. Vin 0.1µF 5kΩ R1 5kΩ 158Ω 158Ω + 4 C1 7 1/3 CLC5623 0.1µF Vo 100Ω - 11 Rf 1kΩ 1.698kΩ Rg 0.1µF Figure 14: Lowpass Filter Topology http://www.national.com 10 Rg2 Vin Rt1 Vd/2 + 1/3 CLC5623 Rf2 1/3 CLC5623 Rf1 Rt2 -Vd/2 Rm/2 Req Rm/2 1:n Io Zo RL UTP + + Vo - Rg1 Bandpass Filter Figure 18 illustrates a low-sensitivity bandpass filter and design equations. This topology utilizes the CLC5623’s closely matched amplifiers to obtain low op-amp sensitivity at high frequencies. The third CLC5623 is used as a buffer to obtain low output impedance. The overall circuit gain is unity. For additional gain, the third CLC5623 can be configured as a non-inverting amplifier. To design the filter, choose C and then determine values for R and R1 based on the desired resonant frequency (fr) and Q factor. C + 1/3 CLC5623 Figure 17: Differential Line Driver wtih Load Impedance Conversion Set up the CLC5623 as a difference amplifier:  Vd R R = 2 ⋅ 1 + f1  = 2 ⋅ f2 Vin R g2  R g1  Make the best use of the CLC5623’s output drive capability as follows: Rm + Req = 2 ⋅ Vmax Imax R R Vin R1 C R R 1/3 CLC5623 + + 1/3 CLC5623 Vo Rf where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the maximum Output Current. Match the line’s characteristic impedance: RL = Z o Rm = Req n= RL Req - 1 R= 2πfr C R1 = QR Figure 18: Bandpass Filter Topology Instrumentation Amplifier An instrumentation circuit is shown on the front page and reproduced in Figure 19. The DC CMRR can be fine tuned by adjusting R1. V1 + 1/3 CLC5623 Select the transformer so that it loads the line with a value very near Zo over frequency range. The output impedance of the CLC5623 also affects the match. With an ideal transformer we obtain: Return Loss = −20 ⋅ log10 n ⋅ Z o(5623) ( jω ) ,dB Zo 2 - 750Ω 750Ω - 750Ω Vout = 3(V2 - V1) 750Ω 750Ω V2 1/3 CLC5623 750Ω 1/3 CLC5623 + R1 750Ω + where Zo(5623)(jω) is the output impedance of the CLC5623 and |Zo(5623)(jω)|