LMH0318RTWR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMH0318 SNLS508 – SEPTEMBER 2015 LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver 1 Features 2 Applications • • • • • 1 • • • • • • • • • • • • Supports ST 424(3G), 292(HD), 259(SD), MADI, and DVB-ASI Locks to rates 2.97 Gbps, 1.485 Gbps, or Divided by 1.001 sub-rates, and DVB-ASI Reference-free Operation with Fast Lock Time covering all Supported or Selected Data Rates 75 Ω and 100 Ω Transmitter Outputs Integrated 2:1 Mux Input, 1:2 Demux/Fanout Outputs Automatic Slew Rate Based on Input Rate Detect On-chip Eye Monitor Low 300 mW Power Consumption With Automatic Power Down On Loss Of Input Signal Programmable via SPI, Or SMBus Interface Single 2.5 V Supply Operation Small 4 mm × 4 mm 24-pin QFN Package -40°C to +85°C Operating Temperature Range Footprint compatible with LMH1218 for easy upgrade to 12G SMPTE Compatible Serial Digital Interface (SDI) Broadcast Video Routers, Switches, and Monitors Digital Video Processing and Editing DVB-ASI and Distribution Amplifiers 3 Description The LMH0318 is a 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver designed to drive serial video data compatible to SMPTE-SDI and DVB-ASI standards. The clock and data recovery circuit eliminates accumulated jitter and detects the incoming data rate without requiring an external reference clock. The integrated driver with 75 ohm and 50 ohm outputs enables multiple media options such as coax and FR4 PCB. Device Information(1) PART NUMBER LMH0318 PACKAGE WQFN (24) BODY SIZE (NOM) 4 mm × 4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified SPI Schematic VDD .: .: MODE_SEL ENABLE 0.01 PF 0.01 PF 1 6 11 OUT VDD VDD 7 IN0+ 21 4.7 PF OUT0+ 20 :T-Line 100: Differential T-Line 4.7 PF FPGA 12 OUT OUT0- 19 IN0- 4.7 PF DAP VSS LMH0318 VSS 8 OUT 9 OUT 4.7 PF OUT1+ 2 23 IN+ FPGA 100: Differential T-Line IN1OUT1- SS_N 10 IN1+ 100: Differential T-Line 4.7 PF FPGA : 24 3 4 13 15 IN22 16 SCK MOSI LOS_INT_N MISO LOCK 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH0318 SNLS508 – SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description continued ........................................... Pin Configuration and Functions ......................... Specifications......................................................... 8.4 Device Functional Modes........................................ 24 8.5 Programming .......................................................... 24 1 1 1 2 3 3 6 9 9.1 9.2 9.3 9.4 Application Information............................................ Typical Application ................................................. Do's and Don'ts ....................................................... Initialization Set Up ................................................. 43 43 48 48 10 Power Supply Recommendations ..................... 48 11 Layout................................................................... 49 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Recommended SMBus Interface AC Timing Specifications ........................................................... 11 7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications ............................................... 11 7.8 Typical Characteristics ............................................ 12 8 Application and Implementation ........................ 43 11.1 Layout Guidelines ................................................. 49 11.2 Layout Example .................................................... 49 11.3 Solder Profile......................................................... 50 12 Device and Documentation Support ................. 51 12.1 12.2 12.3 12.4 12.5 12.6 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 51 51 51 51 51 51 13 Mechanical, Packaging, and Orderable Information ........................................................... 51 4 Revision History 2 DATE REVISION NOTES September 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 LMH0318 www.ti.com SNLS508 – SEPTEMBER 2015 5 Description continued The integrated 2-to-1 MUX on the input of the LMH0318 enables selection between two video sources, while the programmable equalizer compensates for the PC board loss to extend signal reach. With a wide range clockand-data recovery (CDR) circuit, the on-chip reclocker automatically detects and locks to serial data from 270 Mbps to 2.97 Gbps without the need for an external reference clock and loop filter component, thereby simplifying board design and lowering system cost. The reclocked serial data can be routed to either the 75 Ω or 50 Ω transmitter output, or both simultaneously (1-to-2 fanout mode). The output voltage swing is compatible to ST 424, 344, 292, and 259 standards. A non-disruptive eye monitor allows for real-time measurement of serial data to simplify system startup or field tuning. The LMH0318 is pin compatible with the LMH1218, 12 Gbps Cable Driver with Integrated Reclocker. 6 Pin Configuration and Functions ENABLE RESERVED OUT_CTRL_MOSI_SDA EQ_SCL_SCK IN_OUT_SEL_SPI_SS_N_ADR0 MODE_SEL 6 5 4 3 2 1 24-Pin WQFN Package RTWA0024A (Top View) VDD 7 24 VSS IN1+ 8 23 OUT1+ IN1- 9 22 OUT1- VSS 10 21 VDD IN0+ 11 20 OUT0+ IN0- 12 19 OUT0- 13 14 15 16 17 18 LOS_INT_N RESERVED VOD_MISO_ADR1 LOCK RESERVED RESERVED DAP = GND Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 3 LMH0318 SNLS508 – SEPTEMBER 2015 www.ti.com Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD PIN NAME NO. I/O DESCRIPTION CONTROL/INDICATOR I/O MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus 1 kΩ to VDD: • SPI mode. See Initialization Set Up SS_N 2 Input, 2-Level SPI Slave Select. . This pin has internal pull up SCK 3 Input, 2.5V LVCMOS, 2-Level 4 Input, 2-Level MOSI RESERVED 5,14,17, 18 SPI serial clock input SPI Master Output / Slave Input. LMH0318 SPI data receive No Connect Powers down device when pulled low 1 kΩ to VDD: • Power down until valid signal detected Float(Default): • Reserved 20 kΩ to GND: • Reserved 1 kΩ to GND: • Power down including signal detects and Reset Registers upon power-up ENABLE 6 Input, 4-Level LOS_INT_N 13 Output, LVCMOS Open Drain, 2-Level MISO 15 Output, 2.5 V LVCMOS, 2-Level SPI Master Input / Slave Output. LMH0318 SPI data transmit 16 Output, 2.5V LVCMOS, 2-Level Indicates CDR lock detect status High: • CDR locked Low: • CDR not locked IN0+ 11 Input, Analog IN0- 12 Input, Analog IN1+ 8 Input, Analog IN1- 9 Input, Analog OUT0+ 20 Output, 75 Ω CML Compatible OUT0- 19 Output, 75 Ω CML Compatible OUT1+ 23 Output, Analog OUT1- 22 Output, Analog VDD 7, 21 2.5 V Supply VSS 10, 24 Ground Connect directly to ground (GND) Ground Exposed DAP, connect to GND using at least 5 vias (see Figure 23 ) LOCK Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, or change in lock. External 4.7-kΩ pull-up resistor is required. This pin is 3.3 V LVCMOS tolerant. HIGH SPEED DIFFERENTIAL I/O Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC coupling capacitors. Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN1+ to IN1-. Inputs require 4.7 µF AC coupling capacitors. Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC coupling capacitors Inverting and non-inverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC coupling capacitors POWER DAP 4 2.5 V ± 5% Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 LMH0318 www.ti.com SNLS508 – SEPTEMBER 2015 Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND PIN NAME NO. MODE_SEL 1 ADDR0 2 ADDR1 15 SCL 3 SDA 4 RESERVED I/O DESCRIPTION Input, 4-Level Determines Device Configuration: SPI or SMBus 1 kΩ to GND: SMBUS mode. See Initialization Set Up Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. Note SMBus section for further details. The four strap options include: 1 kΩ to VDD: • Represents logic state 11’b Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17 20 kΩ to GND: • Represents logic state 01'b 1 kΩ to GND: • Represents logic state 00'b Input, 2-Level SMBus clock input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is required as per SMBus interface standard. This pin is 3.3 V LVCMOS tolerant. SMBus data input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is I/O, Open Drain, 2required as per SMBus interface standard. This pin is 3.3 V LVCMOS Level tolerant. 5,14,17, 18 No Connect Powers down device when pulled low 1 kΩ to VDD: • Power down until valid signal detected Float(Default): Reserved 20 kΩ to GND: • Reserved 1 kΩ to GND: • Power down including signal detects and Reset Registers upon power-up ENABLE 6 Input, 4-Level LOS_INT_N 13 Output, LVCMOS Open Drain, 2Level Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, change in lock. External 4.7-kΩ pull-up resistor is required. This pin is 3.3 V LVCMOS tolerant. 16 Output, 2.5 V LVCMOS, 2-Level Indicates CDR lock Status High: • CDR locked Low: • CDR not locked IN0+ 11 Input, Analog IN0- 12 Input, Analog IN1+ 8 Input, Analog IN1- 9 Input, Analog OUT0+ 20 Output, 75 Ω CML Compatible OUT0- 19 Output, 75 Ω CML Compatible OUT1+ 23 Output, Analog OUT1- 22 Output, Analog VDD 7, 21 2.5 V Supply VSS 10, 24 Ground Connect directly to ground (GND) Ground Exposed DAP, connect to GND using at least 5 vias (see Figure 23 ) LOCK HIGH SPEED DIFFERENTIAL I/O DAP Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC coupling capacitors. Inverting and non-inverting differential inputs. An on-chip 100 Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC coupling capacitors. Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC coupling capacitors Inverting and non-inverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC coupling capacitors 2.5V ± 5% Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 5 LMH0318 SNLS508 – SEPTEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply Voltage (VDD to GND) -0.5 2.75 V 3.3 V Open drain I/O input/output voltage (SDA, SCL, LOS_INT_N) -0.5 4.0 V 2.5V LVCMOS Input/Output Voltage -0.5 2.75 V High Speed input Voltage -0.5 2.75 V High Speed Input Current -30 30 mA (1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±4500 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500 V may actually have higher performance. 7.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) Supply voltage (1) 3.3 V Open drain I/O input/output voltage (1) MIN TYP MAX UNIT 2.375 2.5 2.625 V 3 3.3 3.6 Supply noise, 50 Hz to 10 MHz, sinusoidal 40 V mVpp Ambient Temperature -40 25 85 Source transmit differential launch amplitude 300 500 1000 mVP-P 100 400 kHz 3.6 V 20 MHz SMBus clock frequency (SCL) in SMBus slave mode SMBUS SDA and SCL Voltage Level SPI Clock Frequency (1) 10 ºC DC plus AC power should not exceed these limits. 7.4 Thermal Information THERMAL METRIC (1) (2) RTWA0024A 24 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 31.4 RθJB Junction-to-board thermal resistance 11.8 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 11.8 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 (1) (2) 6 UNIT 34 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 LMH0318 www.ti.com SNLS508 – SEPTEMBER 2015 7.5 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER PD PD_RAW Power dissipation Power dissipation in force RAW mode (CDR bypass) Locked 75 Ω OUT0 only (800 mVpp), EOM powered down 300 mW Locked OUT1 only (600 mVpp, diff), EOM powered down 195 mW Transient power during CDR lock acquisition, 75 Ω OUT0 and OUT1 powered up, EOM powered down 400 EQ bypass, OUT0 720mVpp, OUT1 600mVpp IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1 195 mW IN0 to OUT0, OUT1 powered down 160 mW IN1 to OUT1, OUT0 powered down 80 mW 500 mW 4-LEVEL INPUT and 2.5 V LVCMOS DC SPECIFICATIONS VIH High level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.95*VDD V VIF Float level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.67*VDD V VI20K 20K to GND input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.33*VDD V VIL Low level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.1 V VOH High level output voltage IOH = -3 mA VOL Low level output voltage IOL = 3 mA 0.4 V IIH Input high leakage current Vinput = VDD SPI Mode: LVCMOS (SPI_SCK, SPI_SS_N) pins 15 µA SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) pins 15 µA IIL Input low leakage current 2 V SMBus Mode: 4-Levels (ADDR0, ADDR1) pins 20 44 80 µA 4-Levels (MODE_SEL, ENABLE) pins 20 44 80 µA Vinput = GND SPI Mode: LVCMOS (SPI_MOSI, SPI_SCK) pins -15 µA Vinput = GND SPI Mode: LVCMOS (SPI_SS_N) pins -37 µA SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL pins -15 µA SMBus Mode: 4-Levels (ADDR0, ADDR1) pins -160 -93 -40 µA 4-Levels (MODE_SEL, ENABLE) pins -160 -93 -40 µA Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 7 LMH0318 SNLS508 – SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N) VIH25 High level input voltage VIL Low level input voltage 2.5 V Supply Voltage 1.75 3.6 V GND 0.8 V VOL Low level output voltage IOL = 1.25 mA 0.4 V IIH Input high current VIN = 2.5 V, VDD = 2.5 V 20 40 μA IIL Input low current VIN = GND, VDD = 2.5 V -10 10 μA Signal detect (default) Assert threshold level (1) (2) 2.97 Gbps, EQ Pathological Pattern 22 mVP-P 2.97 Gbps, PLL Pathological Pattern 22 mVP-P 2.97 Gbps, PRBS10 Pattern 22 mVP-P 2.97 Gbps EQ Pathological Pattern 16 mVP-P 2.97 Gbps, PLL Pathological Pattern 16 mVP-P 2.97 Gbps, PRBS10 Pattern 9 mVP-P SIGNAL DETECT SDH SDL Signal detect (default) De-assert threshold level (1) HIGH SPEED RECEIVE RX INPUTS (IN_n+, IN_n-) R_RD DC Input differential resistance RLRX-SDD Input differential return loss (3) (4) RLRX-SCD Differential to common mode Input conversion (3) (4) 75 100 125 Ω Measured with the device powered up. SDD11 10 MHz to 2 GHz -14 dB SDD11 2 GHz to 3 GHz -6.5 dB Measure with the device powered up.SCD11, 10 MHz to 3 GHz -20 dB HIGH SPEED OUTPUTS (OUT_n+, OUT_n-) VVOD_OUT1 Output differential voltage (3) (4) Default setting, 8T clock pattern VVOD_OUT1_DE De-emphasis Level VOD = 600mV, maximum De-Emphasis with 16T clock pattern -9 560 VVOD_OUT1_CLK Clock output differential voltage 2.97 GHz,1.485 GHz, and 270 MHz VVOD_OUT0 Output single ended voltage at OUT0+ with OUT0- terminated (5) (3) Default setting RDIFF_OUT1 (1) (2) (3) (4) (5) 8 400 720 DC output differential resistance 600 800 100 700 mVP-P dB mVP-P 880 mVP-P Ω Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds. The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal detect assert condition These limits are ensured by bench characterization and are not production tested. Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in 75 Ohm. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMH0318 LMH0318 www.ti.com SNLS508 – SEPTEMBER 2015 Electrical Characteristics (continued) Over operating free-air temperature range (unless otherwise noted) PARAMETER RDIFF_OUT0 DC output single ended resistance TR_F_OUT1 Output rise/fall time TR_F_OUT0 Output rise/fall time, PRBS15 (3) (4) TEST CONDITIONS Output rise/fall time mismatch (3) (4) TYP MAX UNIT 75 Ω Full Slew Rate, 20% to 80% using 8T Pattern 45 ps 2.97 Gbps 35 45 ps 1.485 Gbps 35 45 ps 900 1500 ps 2.97 Gbps 3 18 ps 1.485 Gbps 3 18 ps 72 500 ps 2.4%