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LMH1226
SNLS534D – APRIL 2016 – REVISED JUNE 2018
LMH1226 Low-Power, Dual-Output 12-G UHD Reclocker
1 Features
3 Description
•
The LMH1226 is a low-power, dual-output 12G UHD
reclocker. It supports SMPTE video rates up to 11.88
Gbps and 10 GbE video over IP, enabling UHD video
for 4K/8K applications. An adaptive board trace
equalizer at IN1 is SFF-8431 compatible and
supports both SMPTE and 10 GbE data rates.
1
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Supports ST-2082-1(12G), ST-2081-1(6G), ST424(3G), ST-292(HD), and ST-259(SD)
Supports SFF8431 (SFP+) for SMPTE 2022-5/6
Compatible with DVB-ASI and AES10 (MADI)
Reference-Less Reclocker Locks to SMPTE and
10 GbE Rates: 11.88 Gbps, 5.94 Gbps, 2.97
Gbps, 1.485 Gbps, or Divide-by-1.001 Sub-Rates,
270 Mbps, and 10.3125 Gbps
Reference Free With Fast Lock Time
Adaptive Board Trace Equalizer at Input 1 (IN1)
Low Power: 214 mW (typical)
Power-Save Mode: 16 mW
Integrated 1:2 Fanout Outputs with De-Emphasis
On-Chip Loop Filter and Eye Opening Monitor
Powers from Single 2.5 V with On-Chip 1.8 V
Regulator
Configurable by Control Pins, SPI, or SMBus
Interface
4-mm × 4-mm 24-Pin QFN Package
Operating Temperature Range: –40°C to +85°C
The reclocker attenuates high frequency jitter and
provides the best signal integrity. High input jitter
tolerance of the reclocker improves timing margin.
The reclocker has built-in loop filter and operates
without the need of a precision input reference clock.
A non-disruptive eye monitor allows for real time
measurement of the serial data to simplify system
debug and accelerate board bring-up.
The integrated 1:2 fanout provides flexibility for
multiple video signals. The output drivers offer
programmable de-emphasis to compensate board
trace losses at its outputs. The typical power
consumption of LMH1226 is 214 mW. In the absence
of input signal, power is further reduced to 16 mW.
The LMH1226 is pin compatible with the LMH1219
(12G-UHD cable equalizer with integrated reclocker).
Device Information(1)
2 Applications
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•
•
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PART NUMBER
SMPTE Compatible Serial Digital Interface (SDI)
UHDTV/4K/8K/HDTV/SDTV Video
Broadcast Video Routers, Switchers, and Monitors
Digital Video Processing and Editing
10 GbE - SDI Media Gateway
LMH1226
PACKAGE
QFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
IN1±
2 Diff 100 Ÿ
Term
PCB
EQ
Reclocker
Data
with
Integrated
Clock
LoopFilter,
EyeMon
OUT_MUX
Power
Management
LDO
Single 2.5 V
or
Dual 2.5 V and 1.8 V
VDD_LDO
Control Logic
Control
Lock
Pins
Indicator
100-Ÿ
Driver
2
100-Ÿ
Driver
2
OUT0±
OUT1±
Serial
Interface
SPI
or
SMBus
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH1226
SNLS534D – APRIL 2016 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Recommended SMBus Interface AC Timing
Specifications .......................................................... 11
6.7 Serial Parallel Interface (SPI) AC Timing
Specifications ........................................................... 11
6.8 Typical Characteristics ............................................ 12
7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 20
7.5 LMH1226 Register Map .......................................... 25
8
Application and Implementation ........................ 37
8.1 Application Information............................................ 37
8.2 Typical Application ................................................. 37
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 41
10.1 PCB Layout Guidelines......................................... 41
10.2 Layout Example .................................................... 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
12 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2017) to Revision D
•
First public release of full production data sheet ................................................................................................................... 1
Changes from Revision B (February 2017) to Revision C
•
Page
Page
Added package drawing ...................................................................................................................................................... 43
Changes from Revision A (May 2016) to Revision B
Page
•
Changed eq_en_bypass bit description from "Gain Stages 3 and 4" to "Gain Stages 2 and 3" ........................................ 27
•
Changed bit location of IN1 Carrier Detect Power Down Control from Reg 0x13[5] to Reg 0x15[6] .................................. 27
Changes from Original (April 2016) to Revision A
Page
•
Deleted min and max VOD_DE amplitude specification when VOD_DE = Level F ............................................................. 8
•
Changed typical VOD_DE amplitude specifications for Levels F, R, and L .......................................................................... 8
•
Changed DEM value and DEM register settings in Table 5 to match correct VOD_DE pin logic levels ............................. 18
•
Added new row for VOD = 5, DEM = 5 setting in Table 10 ................................................................................................ 39
2
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Product Folder Links: LMH1226
LMH1226
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SNLS534D – APRIL 2016 – REVISED JUNE 2018
5 Pin Configuration and Functions
VIN
VDD_LDO
VDDIO
SCK_SCL
MISO_ADDR1
OUT_CTRL
24
23
22
21
20
19
RTW Package
24-Pin QFN
Top View
RSV1
1
18
OUT0+
RSV2
2
17
OUT0-
VSS
3
16
VSS
IN1+
4
15
OUT1+
IN1-
5
14
OUT1-
13
VDD_CDR
8
9
10
11
12
VSS
MOSI_SDA
VOD_DE
LOCK_N
SS_N_ADDR0
IN_OUT_SEL
6
EP = VSS
7
MODE_SEL
LMH1226
Pin Functions
PIN
NAME
NO.
I/O
(1)
DESCRIPTION
High-Speed Differential I/Os
IN1+
4
I, Analog
IN1-
5
I, Analog
OUT0+
18
O, Analog
OUT0-
17
O, Analog
OUT1+
15
O, Analog
OUT1-
14
O, Analog
RSV1
1
RSV2
2
Differential complementary inputs with internal 100-Ω termination. Requires external
4.7-µF AC coupling capacitors for SMPTE and 10 GbE.
Differential complementary outputs with 100-Ω internal termination. Requires external
4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user
control.
Differential complementary outputs with 100 Ω internal termination. Requires external
4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user
control.
Reserved pins.
Do not connect.
Control Pins
LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW
when the reclocker has acquired locking condition. LOCK_N is an open drain output,
3.3 V tolerant, and requires an external 2-kΩ to 5-kΩ pull-up resistor to logic supply.
LOCK_N pin can be re-configured to indicate INT_N (Interrupt) through register
programming.
LOCK_N
12
O, LVCMOS, OD
IN_OUT_SEL
8
I, 4-LEVEL
IN_OUT_SEL selects the signal flow at input ports to output ports. See Table 2 for
details. This pin setting can be overridden by register control.
I, 4-LEVEL
OUT_CTRL selects the signal flow from IN1± to OUT1± and OUT0±. It selects
reclocked data, reclocked data and clock, bypassed reclocker data (equalized data to
output driver), or bypassed equalizer and reclocker data. See Table 4 for details. This
pin setting can be overridden by register control.
OUT_CTRL
(1)
19
I = Input, O = Output, IO = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic
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LMH1226
SNLS534D – APRIL 2016 – REVISED JUNE 2018
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
I/O
(1)
DESCRIPTION
VOD_DE
11
I, 4-LEVEL
VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0±
and OUT1±. See Table 5 for details. This pin setting can be overridden by register
control.
MODE_SEL
6
I, 4-LEVEL
MODE_SEL enables SPI or SMBus serial control interface. See Table 6 for details.
Serial Control Interface (SPI Mode), MODE_SEL = F (Float)
SS_N
7
I, LVCMOS
SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the
LMH1226 slave device. SS_N is a LVCMOS input reference to VDDIO.
MISO
20
O, LVCMOS
MISO is the SPI control serial data output from the LMH1226 slave device. MISO is a
LVCMOS output reference to VDDIO.
MOSI
10
I, LVCMOS
MOSI is used as the SPI control serial data input to the LMH1226 slave device. MOSI
is LVCMOS input reference to VDDIO.
SCK
21
I, LVCMOS
SCK is the SPI serial input clock to the LMH1226 slave device. SCK is LVCMOS
reference to VDDIO.
Serial Control Interface (SMBus Mode) , MODE_SEL = L (1 kΩ to VSS)
ADDR0
7
Strap, 4-LEVEL
ADDR1
20
Strap, 4-LEVEL
SDA
10
IO, LVCMOS, OD
SCL
21
I, LVCMOS, OD
3, 9, 16
I, Ground
Ground reference.
ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus
addresses. ADDR[1:0] are 4-level straps and are read into the device at power up.
SDA is the SMBus bi-directional open drain SDA data line to or from the LMH1226
slave device. SDA is an open drain IO and tolerant to 3.3 V. SDA requires an external
2-kΩ to 5-kΩ pull-up resistor to the SMBus termination voltage.
SCL is the SMBus input clock to the LMH1226 slave device. It is driven by a
LVCMOS open drain driver from the SMBus master. SCL is tolerant to 3.3 V and
requires an external 2-kΩ to 5-kΩ pull up resistor to the SMBus termination voltage.
Power
VSS
VIN
24
I, Power
VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ±
5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO
regulator. For lower power operation, both VIN and VDD_LDO should be connected
to a 1.8 V supply.
VDDIO
22
I, Power
VDDIO powers the LVCMOS IO and 4-level input logic and connects to 2.5 V ± 5%
supply.
VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to
a 2.5 V supply. VDD_LDO output requires external 1-μF and 0.1-μF bypass
capacitors to VSS. The internal LDO is designed to power internal circuitry only.
VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation.
When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be
connected to a 1.8 V supply.
VDD_LDO
23
IO, Power
VDD_CDR
13
I, Power
VDD_CDR powers the reclocker circuitry and connects to 2.5 V ± 5% supply.
I, Ground
EP is the exposed pad at the bottom of the QFN package. The exposed pad must be
connected to the ground plane through a via array. See Figure 29 for details.
EP
4
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Product Folder Links: LMH1226
LMH1226
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SNLS534D – APRIL 2016 – REVISED JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply Voltage for 2.5 V Mode (VDD_CDR, VIN, VDDIO)
–0.5
2.75
V
Supply Voltage for 1.8 V Mode (VIN, VDD_LDO)
–0.5
2.0
V
4-Level Input/Output Voltage (IN_OUT_SEL, OUT_CTRL, VOD_DE,
MODE_SEL, ADDR0, ADDR1)
–0.5
2.75
V
SMBus Input/Output Voltage (SDA, SCL)
–0.5
4.0
V
SPI Input/Output Voltage (SS_N, MISO, MOSI, and SCK)
–0.5
2.75
V
Input Voltage (IN1±)
–0.5
2.75
V
Input Current (IN1±)
–30
Operating Junction Temperature
Storage temperature
(1)
-65
30
mA
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500 V HBM is possible with the necessary precautions. Pins listed as ±4500 V may actually have higher performance.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250 V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Single Supply Mode
Dual Supply Mode
VDDSMBUS
VIN1_LAUNCH
(1)
(2) (3)
MIN
NOM
MAX
UNIT
2.375
2.5
2.625
V
1.71
1.8
1.89
V
VDD_CDR, VDDIO to VSS
2.375
2.5
2.625
V
SMBus: SDA, SCL Open Drain Termination Voltage
2.375
3.6
V
VIN, VDDIO, VDD_CDR to VSS
VIN, VDD_LDO to VSS
Source Differential Launch Amplitude Before 5-Inch Board Trace
300
850
mVp-p
Source Differential Launch Amplitude Before 20-Inch Board Trace
650
1000
mVp-p
100
°C
85
°C
TJUNCTION
Operating Junction Temperature
TAMBIENT
Ambient Temperature
NTpsmax (4)
(1)
(2)
(3)
(4)
–40
25
Maximum Supply Noise
Tolerance
50 Hz to 1 MHz, Sinusoidal
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