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LMH1218
SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
LMH1218 Low Power Ultra HD Cable Driver With Integrated Reclocker
1 Features
3 Description
•
The LMH1218 device is a low-power cable driver with
integrated reclocker to drive serial video data
compatible to SMPTE-SDI, SMPTE 2022-5/6, 10GbE
Ethernet, and DVB-ASI standards. The LMH1218
supports up to 11.88 Gbps to enable Ultra High
Definition Video for 4K/8K applications. With 75-Ω
and 50-Ω transmitter outputs, the LMH1218 enables
multiple media options such as coax, fiber, and FR-4
PCB.
1
•
•
•
•
•
•
•
•
•
•
•
Supports ST-2082 (Proposed), ST-2081
(Proposed), SMPTE 424M, 344M, 292M, 259M,
DVB-ASI, SFF-8431 (SFP+) and 10GbE Ethernet
for SMPTE 2022-5/6
Locks to Rates 11.88 Gbps, 5.94 Gbps, 2.97
Gbps, 1.485 Gbps, or Divided by 1.001 SubRates, DVB-ASI (270 Mbps) and 10GbE (10.3125
Gbps)
Reference-Free Operation With Fast Lock Time
Covering All Supported or Selected Data Rates
75-Ω and 100-Ω Transmitter Outputs
Integrated 2:1 Mux Input, 1:2 Demux/Fanout
Outputs
Automatic Slew Rate Based on Input Rate Detect
On-Chip Eye Monitor
Low 300-mW Power Consumption With Automatic
Power Down on Loss of Input Signal
Programmable Through SPI or SMBus Interface
Single 2.5-V Supply Operation
Small 4-mm × 4-mm 24-Pin WQFN Package
–40°C to +85°C Operating Temperature Range
The integrated 2-to-1 MUX on the input of the
LMH1218 enables selection between two video
sources,
while
the
programmable
equalizer
compensates for the printed-circuit board loss to
extend signal reach. With a wide range clock-anddata recovery (CDR) circuit, the on-chip reclocker
automatically detects and locks to serial data from
270 Mbps to 11.88 Gbps without the need for an
external reference clock and loop filter component,
thereby simplifying board design and lowering system
cost. The reclocked serial data can be routed to
either the 75-Ω or 50-Ω transmitter output, or both
simultaneously (1-to-2 fanout mode). The output
voltage swing is compatible to SFF-8431 (SFP+), ST2082/1 (Proposed), SMPTE 424M, 344M, 292M, and
259M standards.
A non-disruptive eye monitor allows for real-time
measurement of serial data to simplify system startup or field tuning. The LMH1218 can be programmed
using SPI or SMBus Interface.
2 Applications
•
•
•
•
•
UHDTV/4K/8K/HDTV/SDTV Video
Digital Video Routers and Switches
Digital Video Processing and Editing
DVB-ASI and Distribution Amplifiers
10GbE for SMPTE 2022-5/6
Device Information(1)
PART NUMBER
PACKAGE
LMH1218
WQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified SPI Schematic
VDD
MODE_SEL
0.1 PF
0.01 PF
ENABLE
4.7 PF
OUT
FPGA
4.7 PF
IN0+
LMH1218
OUT0+
: T-Line
100: Differential T-Line
OUT
IN0-
OUT0DAP
VSS
4.7 PF
OUT
:
IN1+
Optical Module
100: Differential T-Line
IN1-
OUT
IN+
OUT1+
100: Differential T-Line
FPGA
4.7 PF
VSS
OUT1-
IN-
SS_N
SCK
MOSI
LOS_INT_N
MISO
LOCK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH1218
SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
7
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Recommended SMBus Interface AC Timing
Specifications ........................................................... 12
6.7 Serial Parallel Interface (SPI) Bus Interface AC
Timing Specifications ............................................... 12
6.8 Typical Characteristics ............................................ 13
7
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
14
14
15
25
25
7.6 Register Maps ......................................................... 26
8
Application and Implementation ........................ 44
8.1
8.2
8.3
8.4
Application Information............................................
Typical Application .................................................
Do's and Don'ts .......................................................
Initialization Set Up .................................................
44
44
47
47
9 Power Supply Recommendations...................... 47
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Example .................................................... 48
10.3 Solder Profile......................................................... 49
11 Device and Documentation Support ................. 50
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
50
50
50
12 Mechanical, Packaging, and Orderable
Information ........................................................... 50
4 Revision History
Changes from Revision D (December 2017) to Revision E
Page
•
Changed the note under Float(Default) setting from: Reserved to: Power down until valid signal detected ......................... 5
•
Changed MISO pin I/O description from 3-Level back to 2-Level .......................................................................................... 5
•
Changed the Acknowledge (ACK) graphic text from: Clock Line Held Low by Receiver While Interrupt is Serviced to:
Host may held clock line low to delay transaction................................................................................................................ 20
•
Changed Channel Register 0x80 default from: 0xXX to: 0x20 ............................................................................................ 43
•
Changed the OUT0_VOD bit 7 default from x to 0............................................................................................................... 43
•
Changed the bit description for the OUT0_VOD bits 7-3 from: drv_0_sel_vod[3:0] default value may change from
part to part to: drv_0_sel_vod[3:0] is typically 42 mV per step. ........................................................................................... 43
•
Changed the OUT0_VOD bit 6 default from x to 0............................................................................................................... 43
•
Changed the OUT0_VOD bit 5 default from x to 1............................................................................................................... 43
•
Changed the OUT0_VOD bit 4 default from x to 0............................................................................................................... 43
Changes from Revision C (December 2016) to Revision D
•
Page
Changed Channel Register 0x80 default value from 0101 0100’b to XXXX 0000’b ............................................................ 43
Changes from Revision B (February 2016) to Revision C
Page
•
Changed MISO pin I/O description from 2-Level to 3-Level................................................................................................... 5
•
Added test conditions to the source transmit differential launch amplitude parameters ........................................................ 7
•
Changed OUT0 VOD_Scaling_PD description for bits 7 through 4 ..................................................................................... 43
2
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SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
Changes from Revision A (March 2015) to Revision B
Page
•
Changed ESD Ratings for Human-body model (HBM) From: ±2500 To ±4500 ................................................................... 7
•
Added typical launch amplitude for 20 and 30 inch FR4 trace in the Recommended Operating Conditions ........................ 7
•
Added new Note to the Electrical Characteristics: "ATE Production tested using DC method.."........................................... 9
•
Changed the VVOD_OUT0 row information and values in the Electrical Characteristics ............................................................ 9
•
Added MAX value of 45 ps to TR_F_OUT0 in the Electrical Characteristics............................................................................. 10
•
Changed the TYP value From: 900 To: 950 ps, Added MIN and MAX values to TR_F_OUT0 (270 Mbps) in the
Electrical Characteristics ...................................................................................................................................................... 10
•
Changed the TYP value to 3 ps, Added MAX value of 18 ps to TR_F_OUT0_delta in the Electrical Characteristics.................. 10
•
Changed the TYP value From: 100 To: 72 ps, Added MAX value of 500 ps to TR_F_OUT0_delta (270 Mbps) in the
Electrical Characteristics ...................................................................................................................................................... 10
•
Changed the VOVR_UDR_SHOOT row information and values in the Electrical Characteristics ................................................. 10
•
Added tSU MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications (4) (5) .......................... 12
•
Added tH MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications (4) (5) ............................ 12
•
Added tSSSu MIN = 14 ns, Changed TYP value From: 14 To: 18 ns in the Serial Parallel Interface (SPI) Bus Interface
AC Timing Specifications (4) (5) .............................................................................................................................................. 12
•
Added tSSh MIN = 4 ns in the Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications (4) (5) ......................... 12
•
Added Selective Data Rate Lock in Application and Implementation section. .................................................................... 47
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SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
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Changes from Original (February 2015) to Revision A
•
Page
Changed document status from Product Preview to Production Data .................................................................................. 1
5 Pin Configuration and Functions
4
ENABLE
RESERVED
OUT_CTRL_MOSI_SDA
EQ_SCL_SCK
IN_OUT_SEL_SPI_SS_N_ADR0
MODE_SEL
6
5
4
3
2
1
RTW Package
24-Pin WQFN
(Top View)
VDD
7
24
VSS
IN1+
8
23
OUT1+
IN1-
9
22
OUT1-
VSS
10
21
VDD
IN0+
11
20
OUT0+
IN0-
12
19
OUT0-
13
14
15
16
17
18
LOS_INT_N
SMPTE_10GbE
VOD_MISO_ADR1
LOCK
RESERVED
RESERVED
DAP = GND
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SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
PIN
TYPE
DESCRIPTION
6
Input, 4-Level
Powers down device when pulled low
1 kΩ to VDD:
•
Power down until valid signal detected
Float(Default):
•
Power down until valid signal detected
20 kΩ to GND:
•
Reserved
1 kΩ to GND:
•
Power down including signal detects and Reset Registers upon
power-up
LOCK
16
Output, 2.5-V
LVCMOS, 2-Level
LOS_INT_N
13
Output,
LVCMOS OpenDrain, 2-Level
MISO
15
Output, 2.5-V
LVCMOS, 2-Level
MODE_SEL
1
Input, 4-Level
Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
•
SPI mode. See Initialization Set Up.
SPI Master Output / Slave Input. LMH1218 SPI data receive
NAME
NO.
CONTROL/INDICATOR I/O
ENABLE
MOSI
Indicates CDR lock detect status
High:
•
CDR locked
Low:
•
CDR not locked
Programmable Interrupt caused by change in LOS, violation of internal
eye monitor threshold, or change in lock. External 4.7-kΩ pullup resistor is
required. This pin is 3.3-V LVCMOS tolerant.
SPI Master Input / Slave Output. LMH1218 SPI data transmit
4
Input, 2-Level
5, 17, 18
—
SCK
3
Input, 2.5V
LVCMOS, 2-Level
SMPTE_10GbE
14
—
SS_N
2
Input, 2-Level
SPI Slave Select. This pin has internal pullup
IN0+
11
Input, Analog
IN0–
12
Input, Analog
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN0+ to IN0-. Inputs require 4.7-µF, AC-coupling
capacitors.
IN1+
8
Input, Analog
IN1–
9
Input, Analog
OUT0+
20
Output, 75-Ω CML
Compatible
OUT0–
19
Output, 75-Ω CML
Compatible
OUT1+
23
Output, Analog
OUT1–
22
Output, Analog
DAP
—
Ground
VDD
7, 21
2.5-V Supply
VSS
10, 24
Ground
RESERVED
No Connect
SPI serial clock input
No Connect
HIGH-SPEED DIFFERENTIAL I/O
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN1+ to IN1-. Inputs require 4.7-µF, AC-coupling
capacitors.
Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating
resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7-µF, ACcoupling capacitors
Inverting and noninverting differential outputs. An on-chip 100-Ω
terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7-µF,
AC-coupling capacitors
POWER
Exposed DAP, connect to GND using at least 5 vias (see package
drawing)
2.5 V ± 5%
Ground
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SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
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Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
PIN
NAME
NO.
ADDR0
2
ADDR1
15
TYPE
DESCRIPTION
Input, 4-Level
4-level strap pins used to set the SMBus address of the device. The pin
state is read on power-up. The multi-level nature of these pins allows for
16 unique device addresses. Note the SMBus section for further details.
The four strap options include:
1 kΩ to VDD:
•
Represents logic state 11’b
Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
•
Represents logic state 01'b
1 kΩ to GND:
•
Represents logic state 00'b
6
Input, 4-Level
Powers down device when pulled low
1 kΩ to VDD:
•
Power down until valid signal detected
Float(Default): Reserved
20 kΩ to GND:
•
Reserved
1 kΩ to GND:
•
Power down including signal detects and Reset Registers upon
power-up
LOCK
16
Output, 2.5-V
LVCMOS, 2-Level
Indicates CDR lock Status
High:
•
CDR locked
Low:
•
CDR not locked
LOS_INT_N
13
Output, LVCMOS
Open-Drain, 2Level
Programmable Interrupt caused by change in LOS, violation of internal
eye monitor threshold, change in lock. External 4.7-kΩ pullup resistor is
required. This pin is 3.3-V LVCMOS tolerant.
MODE_SEL
1
Input, 4-Level
RESERVED
5, 17, 18
—
SCL
3
Input, 2-Level
SDA
4
SMPTE_10GbE
14
ENABLE
Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
No Connect
SMBus clock input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is
required as per SMBus interface standard. This pin is 3.3-V LVCMOS
tolerant.
SMBus data input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is
I/O, Open-Drain, 2required as per SMBus interface standard. This pin is 3.3-V LVCMOS
Level
tolerant.
No Connect
HIGH-SPEED DIFFERENTIAL I/O
DAP
—
Ground
IN0+
11
Input, Analog
IN0–
12
Input, Analog
IN1+
8
Input, Analog
IN1–
9
Input, Analog
OUT0+
20
Output, 75-Ω CML
Compatible
OUT0–
19
Output, 75-Ω CML
Compatible
OUT1+
23
Output, Analog
OUT1–
22
Output, Analog
VDD
7, 21
2.5-V Supply
VSS
10, 24
Ground
6
Exposed DAP, connect to GND using at least 5 vias (see package
drawing)
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling
capacitors.
Inverting and noninverting differential inputs. An on-chip 100-Ω terminating
resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling
capacitors.
Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating
resistor connects OUT0+ and OUT0– to VDD. Outputs require 4.7-µF, ACcoupling capacitors
Inverting and noninverting differential outputs. An on-chip 100 Ω
terminating resistor connects OUT1+ to OUT1–. Outputs require 4.7-µF,
AC-coupling capacitors
2.5 V ± 5%
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage (VDD to GND)
–0.5
2.75
V
3.3-V open-drain I/O input and output voltage (SDA, SCL, LOS_INT_N)
–0.5
4.0
V
2.5-V LVCMOS input and output voltage
–0.5
VDD + 0.5
V
High-speed input voltage
–0.5
VDD + 0.5
V
High-speed input current
–30
30
mA
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
Supply voltage (1)
3.3-V open-drain I/O input and output voltage
MIN
TYP
MAX
UNIT
2.375
2.5
2.625
V
3
3.3
3.6
Supply noise, 50 Hz to 10 MHz, sinusoidal (1)
40
Ambient temperature
V
mVP-P
–40
25
85
Source transmit differential launch
amplitude (up to 20 inch FR4 trace)
PRBS15, EQ, and PLL pathological pattern. Reg
0x03 = 0x50
300
500
1000
mVP-P
Source transmit differential launch
amplitude (up to 35 inch FR4 trace)
PRBS15, EQ, and PLL pathological pattern. Reg
0x03 = 0x95
600
700
800
mVP-P
100
400
kHz
3.6
V
20
MHz
SMBus clock frequency (SCL) in SMBus slave mode
SMBUS SDA and SCL voltage level
SPI clock frequency
(1)
10
ºC
DC plus AC power should not exceed these limits.
6.4 Thermal Information
THERMAL METRIC (1) (2)
RTW (WQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
34
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.4
°C/W
RθJB
Junction-to-board thermal resistance
11.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
11.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient
temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.
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6.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
PD
Power dissipation
PD_RAW
Power dissipation in force
RAW mode (CDR bypass)
Locked 75 Ω OUT0 only
(800 mVpp), EOM
powered down
300
mW
Locked OUT1 only (600
mVpp, diff), EOM powered
down
195
mW
Transient power during
CDR lock acquisition, 75 Ω
OUT0 and OUT1 powered
up, EOM powered down
400
EQ bypass, OUT0
720mVpp, OUT1 600mVpp
IN0 to OUT0 and OUT1 or
IN1 to OUT0 and OUT1
195
mW
IN0 to OUT0, OUT1
powered down
160
mW
IN1 to OUT1, OUT0
powered down
80
mW
500
mW
4-LEVEL INPUT AND 2.5 V LVCMOS DC SPECIFICATIONS
VIH
High level input voltage
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
0.95 × VDD
V
VIF
Float level input voltage
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
0.67 × VDD
V
VI20K
20K to GND input voltage
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
0.33 × VDD
V
VIL
Low level input voltage
4-level input (MODE_SEL,
ADDR0/1, ENABLE pins)
0.1
V
VOH
High level output voltage
IOH = -3 mA
VOL
Low level output voltage
IOL = 3 mA
0.4
V
Vinput = VDD
SPI Mode: LVCMOS
(SPI_SCK, SPI_SS_N)
pins
15
µA
SMBus Mode: LVCMOS
(SMB_SDA, SMB_SCL)
pins
15
µA
IIH
IIL
8
Input high leakage current
Input low leakage current
2
V
SMBus Mode: 4-Levels
(ADDR0, ADDR1) pins
20
44
80
µA
4-Levels (MODE_SEL,
ENABLE) pins
20
44
80
µA
Vinput = GND
SPI Mode: LVCMOS
(SPI_MOSI, SPI_SCK)
pins
–15
µA
Vinput = GND
SPI Mode: LVCMOS
(SPI_SS_N) pins
–37
µA
SMBus Mode: LVCMOS
(SMB_SDA, SMB_SCL
pins
–15
µA
SMBus Mode: 4-Levels
(ADDR0, ADDR1) pins
–160
–93
–40
µA
4-Levels (MODE_SEL,
ENABLE) pins
–160
–93
–40
µA
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
VIH25
High level input voltage
VIL
Low level input voltage
2.5-V Supply Voltage
1.75
3.6
V
GND
0.8
V
VOL
Low level output voltage
IOL = 1.25 mA
0.4
V
IIH
Input high current
VIN = 2.5 V, VDD = 2.5 V
20
40
μA
IIL
Input low current
VIN = GND, VDD = 2.5 V
-10
10
μA
SIGNAL DETECT
Signal detect (default)
Assert threshold level (1) (2)
SDH
Signal detect (default)
De-assert threshold
level (1)
SDL
11.88 Gbps, SMPTE (EQ,
PLL) Pathological Pattern
26
mVP-P
10.3125 Gbps, 1010 Clock
Pattern, no media
30
mVP-P
10.3125 Gbps, PRBS31
Pattern
21
mVP-P
11.88 Gbps, SMPTE (EQ,
PLL) Pathological Patterns
20
mVP-P
10.3125 Gbps, 1010 Clock
Pattern
15
mVP-P
10.3125 Gbps, PRBS31
Pattern
12
mVP-P
HIGH-SPEED RECEIVE RX INPUTS (IN_n+, IN_n–)
R_RD
RLRX-SDD
RLRX-SCD
DC Input differential
resistance
75
Input differential return
loss (3)
Differential to common
mode Input conversion (3)
100
125
Ω
Measured with the device
powered up.
SDD11 10 MHz to 2 GHz
–14
dB
SDD11 2 GHz to 6 GHz
–6.5
dB
SDD11 6 GHz to 12 GHz
–6.5
dB
–20
dB
Measure with the device
powered up.SCD11, 10
MHz to 12 GHz
HIGH-SPEED OUTPUTS (OUT_n+, OUT_n–)
VVOD_OUT1
Output differential
voltage (3) (4)
Default setting, 8T clock
pattern
VVOD_OUT1_DE
De-emphasis Level
VOD = 600 mV, maximum
De-Emphasis with 16T
clock pattern
–9
dB
VVOD_OUT1_CLK
Clock output differential
voltage
2.97 GHz,1.485 GHz, 297
MHz, and 270 MHz
560
mVP-P
VVOD_OUT0
Output single ended
voltage at OUT0+ with
OUT0– terminated (3) (4)
RDIFF_OUT1
DC output differential
resistance
RDIFF_OUT0
DC output single-ended
resistance
TR_F_OUT1
Output rise/fall time
(1)
(2)
(3)
(4)
(5)
(5)
Default setting
Full Slew Rate, 20% to
80% using 8T Pattern
400
720
600
778
700
880
mVP-P
mVP-P
100
Ω
75
Ω
45
ps
Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the
device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.
The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal
detect assert condition
These limits are ensured by bench characterization and are not production tested.
Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board
ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in
75 Ω.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TR_F_OUT0
Output rise/fall time,
PRBS10 (3) (4)
TEST CONDITIONS
MIN
TYP
MAX
11.88 Gbps
35
45
ps
5.94 Gbps
35
45
ps
2.97 Gbps
35
45
ps
1.485 Gbps
35
45
ps
950
1500
ps
11.88 Gbps
3
18
ps
5.94 Gbps
3
18
ps
2.97 Gbps
3
18
ps
1.485 Gbps
3
18
ps
72
500
ps
2.4%
3.4%
270 Mbps
TR_F_OUT0_delta
Output rise/fall time
mismatch (3) (4)
270 Mbps
VOVR_UDR_SHOOT
VDC_OFFSET
VDC_WANDER
RLOUT0_S22
RLOUT1_SDD22
RLOUT1_SCC22
Output overshoot,
undershoot (3) (4)
DC offset
(3)
DC wander (3)
OUT0 single-ended 75-Ω
return loss (3) (4) (6)
OUT1 differential 100-Ω
return loss (3) (4) (7)
OUT1 common-mode 50Ω return loss (3) (4) (7)
UNIT
12G/6G/3G/HD/SD
Measured with 8T pattern
12G/6G/3G/HD/SD
12G/6G/3G/HD/SD EQ
Pathological
400
±0.2
V
20
mV
S22 5 MHz to 1.485 GHz
< –15
dB
S22 1.485 GHz to 3 GHz
< –10
dB
S22 3 GHz to 6 GHz
< –7
dB
S22 6 GHz to 12 GHz
< –4
dB
SDD22 10 MHz - 2 GHz
–20
dB
SDD22 2 GHz - 6 GHz
–17
dB
SDD22 6 GHz - 11.1 GHz
–14
dB
SCC22 10 MHz - 4.75
GHz
–11
dB
SCC22 4.75 GHz - 11.1
GHz
–12
dB
VVCM_OUT1_NOISE
AC common-mode voltage VOD = 0.6 Vpp, DE = 0dB,
noise (3) (4)
PRBS31, 10.3125 Gbps
TRCK_LATENCY
Latency reclocked
Reclocked Data
1.5 UI +195
ps
TRAW_LATENCY
Latency CDR bypass
Raw Data
230
ps
8
mVRMS
TRANSMIT OUTPUT JITTER SPECIFICATIONS
AJ_OUT0
Alignment jitter (3) (4)
OUT0, PRBS15, 11.88
Gbps
0.18
UI
TJ_OUT1
Total jitter (1E-12) (3) (4)
OUT1, PRBS15 10.3125
Gbps
0.12
UI
RJ_OUT1
Random jitter (rms)
OUT1, PRBS15, 10.3125
Gbps
0.38
psRMS
DJ_OUT1
Deterministic jitter
OUT1, PRBS15, 10.3125
Gbps
7
psP-P
Deterministic jitter
OUT1, RAW MODE (CDR
bypass)
PRBS15, 11.88 Gbps, 35
inch FR4 trace, EQ=0x95,
VID = 800mVpp
25
psP-P
DJ_OUT1_RAW
(6)
(7)
10
Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board
Measure with the device powered up and outputs a clock signal.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK DATA RECOVERY
DDATA_RATE
ST-2082 (proposed) (8)
11.88,
11.868
Gbps
ST-2081 (proposed) (8)
5.94, 5.934
Gbps
SMPTE 424
(8)
2.97, 2.967
Gbps
SMPTE 292
(8)
1.485,
1.4835
Gbps
SMPTE 259M (8)
270
Mbps
10.3125
Gbps
Measured with 0.2UI SJ at
10.3125 Gbps
8
MHz
Measured with 0.2UI SJ at
11.88 Gbps
13
MHz
Measured with 0.2UI SJ at
5.94 Gbps
7
MHz
Measured with 0.2UI SJ at
2.97 Gbps
5
MHz
Measured with 0.2UI SJ at
1.485 Gbps
3
MHz
Measured with 0.2UI SJ at
270 Mbps
1
MHz
Total input jitter tolerance
TJ = DJ + RJ + SJ,
DJ+RJ = 0.15 UI
SJ/PJ, low to high upward
sweep (10 kHz to 80 MHz)
0.65
UI
TLOCK
Lock time (3) (9)
From signal detected to
the lock asserted,
HEO/VEO lock monitor
disable, same setting for
11.88G, 5.94G, 2.97G,
1.485G and 270-MHz data
rates
9 to allow strap observation on
share reg 0x00
Device Version
7
VERSION[7]
0
RW
6
VERSION[6]
0
RW
5
VERSION[5]
0
RW
4
VERSION[4]
0
RW
3
VERSION[3]
0
RW
2
VERSION[2]
0
RW
1
VERSION[1]
0
RW
0
VERSION[0]
1
RW
Device revision
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Register Maps (continued)
Table 5. Global Registers (continued)
REGISTER NAME
Device ID
Reg 0xF1 Share
DEFAULT
R/RW
0x60
DEVICE_ID[7]
0
RW
6
DEVICE_ID[6]
1
RW
5
DEVICE_ID[5]
1
RW
4
DEVICE_ID[4]
0
RW
3
DEVICE_ID[3]
0
RW
2
DEVICE_ID[2]
0
RW
1
DEVICE_ID[1]
0
RW
0
DEVICE_ID[0]
0
RW
Reg 0xFF Control
0x00
Reserved
0
RW
6
Reserved
0
RW
5
los_int_bus_sel
0
RW
4
Reserved
0
RW
3
Reserved
0
RW
2
en_ch_Access
0
RW
1
Reserved
0
RW
0
Reserved
0
RW
Reg_0x00 Channel
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Rst_regs
0
1
Reserved
0
0
Reserved
LOS_status
1: Selects interrupt onto LOS pin
0: Select signal detect onto LOS pin
1: Enables access to channel registers
0: Enable access to share register
Reset all Channel Registers to Default
Values
0x00
7
Device ID
Enable Channel Control
7
Reset_Channel_Regs
DESCRIPTION
Device ID
7
Channel Control
28
FIELD REGISTER
ADDRESS
BITS
1: Reset Channel Registers ( self
clearing )
0: Normal operation
0
Reg_0x01 Channel
0x00
Signal Detect Status
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
0
RW
2
Reserved
0
RW
1
LOS1
0
R
1: Loss of signal on IN1
0: Signal present on IN1
0
LOS0
0
R
1: Loss of signal on IN0
0: Signal present on IN0
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SNLS474E – FEBRUARY 2015 – REVISED JUNE 2018
Register Maps (continued)
Table 5. Global Registers (continued)
REGISTER NAME
BITS
CDR_Status_1
FIELD REGISTER
ADDRESS
Reg_0x02 Channel
DEFAULT
R/RW
0x00
CDR Status
7
Reserved
0
R
6
Reserved
0
R
5
Reserved
0
R
4
cdr_status[4]
0
R
3
cdr_status[3]
0
R
2
Reserved
0
R
1
Reserved
0
R
0
Reserved
0
R
Interrupt Status Register
Reg 0x54 Channel
DESCRIPTION
0x00
11: CDR locked
00: CDR not locked
Interrupt Status ( clears upon read )
7
Sigdet
0
R
1: Signal Detect from the selected input
asserted
0: Signal Detect from the selected input
de-asserted
6
cdr_lock_int
0
R
1: CDR Lock interrupt
0: No interrupt from CDR Lock
5
signal_det1_int
0
R
1: IN1 Signal Detect interrupt
0: No interrupt from IN1 Signal Detect
4
signal_det0_int
0
R
1: IN0 Signal Detect interrupt
0: No interrupt from IN0 Signal Detect
3
heo_veo_int
0
R
1: HEO_VEO Threshold reached
interrupt
0: No interrupt from HEO_VEO
2
cdr_lock_loss_int
0
R
1: CDR loss of lock interrupt
0: No interrupt from CDR lock
1
signal_det1_loss_int
0
R
1: IN1 Signal Detect loss interrupt
0: No interrupt from IN1 Signal Detect
0
signal_det0_loss_int
0
R
1: IN0 Signal Detect loss interrupt
0: No interrupt from IN0 Signal Detect
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Register Maps (continued)
Table 5. Global Registers (continued)
REGISTER NAME
Interrupt Control
Reg 0x56 Channel
DEFAULT
R/RW
0x00
DESCRIPTION
Interrupt Mask
7
Reserved
0
RW
6
cdr_lock_int_en
0
RW
1: Enable Interrupt if CDR lock is
achieved
0: Disable interrupt if CDR lock is
achieved
5
signal_det1_int_en
0
RW
1: Enable interrupt if IN1 Signal Detect
is asserted
0: Disable interrupt if IN1 Signal Detect
is asserted
RW
1: Enable interrupt if IN0 Signal Detect
is asserted
0: Disable interrupt if IN0 Signal Detect
is asserted
4
30
FIELD REGISTER
ADDRESS
BITS
signal_det0_int_en
0
3
heo_veo_int_en
0
RW
1: Enable interrupt if HEO-VEO
threshold is reached
0: Disable interrupt due to HEO-VEO
threshold
2
cdr_lock_loss_int_en
0
RW
1: Enable interrupt if CDR loses lock
0: Disable interrupt if CDR loses lock
1
signal_det1_loss_int_en
0
RW
1: Enable interrupt if there is loss of
signal on IN1
0: Disable interrupt if there is loss of
signal on IN1
0
signal_det0_loss_int_en
0
RW
1: Enable interrupt if there is loss of
signal on IN0
0: Disable interrupt if there is loss of
signal on IN0
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7.6.2 Receiver Registers
Table 6. Receiver Registers
REGISTER NAME
BITS
EQ_Boost
FIELD REGISTER
ADDRESS
DEFAULT
R/RW
Reg 0x03 Channel
4 Stage EQ Boost Levels. Read-back
value going to CTLE in reg_0x52. Used
for setting EQ value when reg_0x2D[3] is
high
0x80
7
eq_BST0[1]
1
RW
6
eq_BST0[0]
0
RW
5
eq_BST1[1]
0
RW
4
eq_BST1[0]
0
RW
3
eq_BST2[1]
0
RW
2
eq_BST2[0]
0
RW
1
eq_BST3[1]
0
RW
0
eq_BST3[0]
0
RW
SD_EQ
Reg_0x0D Channel
0x00
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
0
RW
2
Reserved
0
RW
1
Reserved
0
RW
Mr_auto_eq_en_bypass
EQ_SD_CONFIG
0
Reg 0x13 Channel
7
6
5
4
Reserved
sd_0_PD
sd_1_PD
Reserved
RW
0x90
2
1
0
Reserved
eq_en_bypass
Reserved
2 Bits control for stage 1 of the CTLE.
Adapts during CTLE adaptation
2 Bits control for stage 2 of the CTLE.
Adapts during CTLE adaptation
2 Bits control for stage 3 of the CTLE.
Adapts during CTLE adaptation
1: EQ Bypass for 270 Mbps
0: Use EQ Settings in reg0x03[7:0] for 270
Mbps
Note: If 0x13[1] mr_eq_en_bypass is set,
bypass would be set and auto-bypass has
no significance.
Channel EQ Bypass and Power Down
1
RW
0
RW
1: Power Down IN0 Signal Detect
0: IN0 Signal Detect normal operation
0
RW
1: Power Down IN1 Signal Detect
0: IN1 Signal Detect normal operation
1
RW
eq_PD_EQ
3
2 Bits control for stage 0 of the CTLE.
Adapts during CTLE adaptation
270 Mbps EQ Boost Setting
7
0
DESCRIPTION
0
RW
0
RW
0
RW
0
RW
Controls the power-state of the selected
channel. The un-selected channel is
always powered-down
1: Powers down selected channel EQ
stage
0: Powers up EQ of the selected channel
1: Bypass stage 3 and 4 of CTLE
0: Enable Stage 3 and 4 of CTLE
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Table 6. Receiver Registers (continued)
REGISTER NAME
FIELD REGISTER
ADDRESS
BITS
SD0_CONFIG
Reg 0x14 Channel
DEFAULT
R/RW
0x00
IN0 Signal Detect Threshold Setting
7
Reserved
0
RW
6
Reserved
0
RW
5
sd_0_refa_sel[1]
0
RW
4
sd_0_refa_sel[0]
0
RW
3
sd_0_refd_sel[1]
0
RW
2
sd_0_refd_sel[0]
0
RW
1
Reserved
0
RW
0
Reserved
0
RW
SD1_CONFIG
Reg_0x15 Channel
0x00
Reserved
0
RW
6
Reserved
0
RW
5
sd_1_refa_sel[1]
0
RW
4
sd_1_refa_sel[0]
0
RW
3
sd_1_refd_sel[1]
0
RW
2
sd_1_refd_sel[0]
0
RW
1
Reserved
0
RW
0
Reserved
0
RW
Reg_0x2D Channel
0x88
Reserved
1
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
reg_eq_bst_ov
1
RW
2
Reserved
0
RW
1
Reserved
0
RW
0
Reserved
0
RW
CTLE Setting
Reg_0x31 Channel
7
Reserved
6
adapt_mode[1]
adapt_mode[0]
5
RW
00
RW
4
Reserved
0
RW
3
Reserved
0
RW
2
Reserved
0
RW
1
input_mux_ch_sel[1]
0
RW
0
RW
input_mux_ch_sel[0]
0
32
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1: Enable EQ boost over ride- refer to
theLMH1218 Programming Guide
(SNLU174)
0: Disable EQ boost over ride
CTLE Mode of Operation and Input/Output
Mux Selection
0x00
0
Controls signal detect SDH- Assert [5:4],
SDL- De-Assert [3:2], thresholds for IN1
0000: Default levels (nominal)
0101: Nominal -2 mV
1010: Nominal +5 mV
1111: Nominal +3 mV
EQ Boost Override
7
3
Controls signal detect SDH- Assert [5:4],
SDL- De-Assert [3:2], thresholds for IN0
0000: Default levels (nominal)
0101: Nominal -2 mV
1010: Nominal +5 mV
1111: Nominal +3 mV
IN1 Signal Detect Threshold Setting
7
EQ_BOOST_OV
DESCRIPTION
00: Normal Operation - Manual CTLE
Setting
01: Test Mode - Refer to the LMH1218
Programming Guide (SNLU174)
Other Settings - Invalid
IN0/1 and OUT0/1 selection
00: selects IN0 and OUT0/1
01: selects IN0 and OUT0
10: selects IN1 and OUT1
11: selects IN1 and OUT0/1
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Table 6. Receiver Registers (continued)
REGISTER NAME
BITS
LOW_RATE_
EQ_BST
FIELD REGISTER
ADDRESS
Reg 0x3A Channel
DEFAULT
R/RW
HD and SD EQ Level
0x00
7
fixed_eq_BST0[1]
0
RW
6
fixed_eq_BST0[0]
0
RW
5
fixed_eq_BST1[1]
0
RW
4
fixed_eq_BST1[0]
0
RW
3
fixed_eq_BST2[1]
0
RW
2
fixed_eq_BST2[0]
0
RW
1
fixed_eq_BST3[1]
0
RW
0
fixed_eq_BST3[0]
0
RW
BST_Indx0
Reg_0x40 Channel
DESCRIPTION
When CTLE is operating in test mode,
Reg 0x3A[7:0] forces fixed EQ setting for
data rates
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