LP38856-1.2EVAL

User's Guide SNVA164B – June 2006 – Revised April 2013 AN-1479 LP38856S-1.2 Evaluation Board 1 Introduction This board is designed to allow the evaluation of the LP38856S-1.2 voltage regulator. Each board is assembled and tested in the factory. This evaluation board has the TO-263 5-lead package mounted. 2 General Description The LP38856 is a dual-rail LDO linear regulator capable of suppling up to 3A of output current, and incorporates an enable function. The device has been designed to work with 10 µF input and output ceramic capacitors, and 1µF bias capacitors. Footprints areas for CIN and COUT will allow for a variety of sizes. 3 Operation The input voltage, applied between VIN and GND, should be at least 1.0 V greater than VOUT, and no higher than the applied VBIAS voltage. The bias voltage, applied between VBIAS and GND should be above the minimum bias voltage of 3.0 V, and no higher than the maximum of 5.5 V. Loads can be connected to VOUT with reference to GND. VOUT and VIN test points are provided on the board to allow accurate measurements directly on the evaluation board, eliminating any voltage drop on the PCB traces or connecting wires to the load. ON/OFF control is provided by supplying a logic level signal to the Enable pin. A minimum VEN value of 1.3 V is required at this pin to enable the LDO output. The LDO output will be shutdown when the VEN value is 1.0 V or less. The VEN threshold incorporates approximately 100 mV of hysteresis. In applications where the LP38856 is operated continuously, the Enable pin can be connected directly to VBIAS, or left open. The Enable pin has a 200 kΩ internal resistor to VBIAS. If the Enable pin is left open, care should be taken to minimize any capacitance on the Enable pin, as any capacitance will introduce an RC delay time on the Enable function. All trademarks are the property of their respective owners. SNVA164B – June 2006 – Revised April 2013 Submit Documentation Feedback AN-1479 LP38856S-1.2 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 1 Hardware www.ti.com Figure 1. Enable Thresholds 4 Hardware The schematic is shown in Figure 2 and the layout of the evaluation board is shown in Figure 3. 5 Schematic Diagram TP1 TP2 TP5 TP3 TP4 LP38856S-1.2 VIN IN (2) VOUT (4) OUT C1 10 PF BIAS (5) VBIAS C2 1 PF C3 10 PF EN (1) VEN GND (3) GND Figure 2. Evaluation Board Schematic 2 AN-1479 LP38856S-1.2 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated SNVA164B – June 2006 – Revised April 2013 Submit Documentation Feedback PCB Layout www.ti.com 6 PCB Layout R2/C5 R 2 C S S C1, 10 PF TP1 C4 LP38856S1.2 TP5 LP38856S-1.2EV LP3885X-T/X-Rev2 J1 VEN C2 C2 R1 R1 J5 VBIAS C2, 1 PF C3 C3 C1 C1 TP2 TP4 TP4 C3, 10 PF TP3 J2 J3 J4 VIN GND VOUT Figure 3. Evaluation Board Component and Pin Layout 7 Power Dissipation The TO-263 package alone has a junction to ambient thermal resistance (θJA) rating of 60°C/W. When mounted on the LP38856S evaluation board, the θJA rating is approximately 37°C/W. Although there is only approximately 0.28 square inches of copper area immediately under the tab, the top copper surface area is extended to additional copper area on the bottom of the board by five thermal vias. With the 37°C/W thermal rating, the LP38856S evaluation board will dissipate a maximum of 2.75W with TA = 25°C. Figure 4. Maximum Power Dissipation vs Ambient Temperature SNVA164B – June 2006 – Revised April 2013 Submit Documentation Feedback AN-1479 LP38856S-1.2 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 3 Bill of Materials 8 4 www.ti.com Bill of Materials ID Name U1 U1 LP38856 Description Manufacturer Part Number Texas Instruments LP38856 C1 CIN C2 CBIAS 10 µF, 10%, MLCC, 10 V, X7R, 1210 AVX 1210ZC106KAT2A 1 µF, 10%, MLCC, 10 V, X7R, 0805 AVX C3 0805ZC105KAT2A COUT 10 µF, 10%, MLCC, 10 V, X7R, 1210 AVX 1210ZC106KAT2A C4 — Not Installed — — C5 — Not Installed — — J1 VEN Banana Jack : Insulated Solder Terminal WHITE 108-0901-001 J2 VIN Banana Jack : Insulated Solder Terminal - RED 108-0902-001 J3 GND Banana Jack : Insulated Solder Terminal BLACK J4 VOUT Banana Jack : Insulated Solder Terminal ORANGE 108-0906-001 J5 VBIAS Banana Jack : Insulated Solder Terminal BLUE 108-0910-001 R1 — Not Installed — — R2 — Not Installed — — TP1 TPEN TP2 TPIN TP3 TPGND Keystone 1593–2 TP4 TPOUT TP5 TPBIAS Turret Terminal : Mounting Hole Diameter = 0.062” AN-1479 LP38856S-1.2 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated Johnson Components 108-0903-001 SNVA164B – June 2006 – Revised April 2013 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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