SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
16-PORT LVDS REPEATER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
One Receiver and Sixteen Line Drivers Meet
or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-Ω
Load
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
Propagation Delay Times < 4.7 ns
Output Skew Is < 300 ps and Part-to-Part
Skew < 1.5 ns
Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz
Driver Outputs or Receiver Input Is High
Impedance When Disabled or With VCC < 1.5
V
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
DESCRIPTION
The SN65LVDS116 is one differential line receiver
connected to sixteen differential line drivers that
implement the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS, as specified in
EIA/TIA-644, is a data signaling technique that offers
the low-power, low-noise coupling, and fast switching
speeds to transmit data at relatively long distances.
(Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of
the media, the noise coupling to the environment, and
other system characteristics.)
The intended application of this device and signaling
technique is for point-to-point or multidrop baseband
data transmission over controlled impedance media
of approximately 100 Ω. The transmission media may
be printed-circuit board traces, backplanes, or cables.
The large number of drivers integrated into the same
substrate along with the low pulse skew of balanced
signaling, allows extremely precise timing alignment
of the signals repeated from the input. This is
particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation
from –40°C to 85°C.
DGG PACKAGE
(TOP VIEW)
GND
VCC
VCC
GND
ENA
ENA
NC
NC
NC
ENB
ENB
NC
NC
NC
GND
VCC
VCC
GND
A
B
NC
ENC
ENC
S0
S1
SM
END
END
GND
VCC
VCC
GND
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM (POSITIVE LOGIC)
A1Y
A1Z
A2Y
S0
S1
SM
A2Z
A3Y
ENA
A3Z
ENA
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
ENB
B3Z
ENB
B4Y
A
B
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
ENC
C3Z
ENC
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
END
D3Z
END
D4Y
D4Z
2
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
FUNCTION TABLE (1)
INPUT
(1)
OUTPUT
VID = VA– VB
SM
EN
EN
S1
S0
AY
AZ
BY
BZ
CY
CZ
DY
DZ
X
H
L
X
X
X
Z
Z
Z
Z
Z
Z
Z
Z
VID ≥ 100 mV
H
H
L
X
X
H
L
H
L
H
L
H
L
–100 mV < VID < 100 mV
H
H
L
X
X
?
?
?
?
?
?
?
?
VID ≤ –100 mV
H
H
L
X
X
L
H
L
H
L
H
L
H
X
H
X
H
X
X
Z
Z
Z
Z
Z
Z
Z
Z
VID ≥ 100 mV
L
X
X
L
L
H
L
Z
Z
Z
Z
Z
Z
–100 mV < VID < 100 mV
L
X
X
L
L
?
?
Z
Z
Z
Z
Z
Z
VID ≤ –100 mV
L
X
X
L
L
L
H
Z
Z
Z
Z
Z
Z
VID ≥ 100 mV
L
X
X
L
H
Z
Z
H
L
Z
Z
Z
Z
–100 mV < VID < 100 mV
L
X
X
L
H
Z
Z
?
?
Z
Z
Z
Z
VID ≤ –100 mV
L
X
X
L
H
Z
Z
L
H
Z
Z
Z
Z
VID ≥ 100 mV
L
X
X
H
L
Z
Z
Z
Z
H
L
Z
Z
–100 mV < VID < 100 mV
L
X
X
H
L
Z
Z
Z
Z
?
?
Z
Z
VID ≤ –100 mV
L
X
X
H
L
Z
Z
Z
Z
L
H
Z
Z
VID ≥ 100 mV
L
X
X
H
H
Z
Z
Z
Z
Z
Z
H
L
–100 mV < VID < 100 mV
L
X
X
H
H
Z
Z
Z
Z
Z
Z
?
?
VID ≤ –100 mV
L
X
X
H
H
Z
Z
Z
Z
Z
Z
L
H
H = high level, L = low level, Z = high impedance, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
VCC
300 kΩ
(EN and SM Only)
300 kΩ
300 kΩ
Enable
Inputs
A Input
B Input
50 Ω
10 kΩ
7V
5Ω
Y or Z
Output
7V
300 kΩ
7V
7V
(EN, S0, and S1 Only)
3
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage range (2)
Input voltage range
Electrostatic discharge
–0.5 V to 4 V
Enable inputs
–0.5 V to 6 V
A, B, Y, or Z
–0.5 V to 4 V
A, B, Y, Z, and GND (3)
Class 3, A:12 kV, B: 500 V
Continuous power dissipation
See Dissipation Rating Table
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DGG
2094 mW
16.7 mW/°C
1089 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
VIH
High-level input voltage
2
VIL
Low-level input voltage
VI or VIC
Voltage at any bus terminal (separately or common-mode)
TA
Operating free-air temperature
4
UNIT
V
V
0.8
V
0
VCC–0.8
V
40
85
°C
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VITH+
Positive-going differential input voltage threshold
VITH–
Negative-going differential input voltage threshold
|VOD|
Differential output voltage magnitude
∆|VOD|
Change in differential output voltage magnitude between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
ICC
Supply current
II
Input current (A or B inputs) (2)
II(OFF)
Power-off input current (A or B inputs)
See Figure 1 and Table 1
RL = 100 Ω, VID = ±100 mV,
See Figure 1 and Figure 2
MIN TYP (1)
100
–100
247
340
50
1.125
1.375
50
50
See Figure 3
50
150
Enabled, RL = 100 Ω
84
115
Disabled, ENx = VCC or ENx = 0 V
3.2
6
–2
VI = 2.4 V
–20
–1.2
VCC = 1.5 V, VI = 2.4 V
20
20
mV
mV
V
mV
mA
µA
µA
IIH
High-level input current
IIL
Low-level input current
IOS
Short-circuit output current
IOZ
High-impedance output current
VO = 0 V or VCC
±1
µA
IO(OFF)
Power-off output current
VCC = 1.5 V, VO = 3.6 V
±1
µA
CIN
Input capacitance (A or B inputs)
VI = 0.4 sin (4E6πt) + 0.5 V
5
CO
Output capacitance (Y or Z outputs)
VI = 0.4 sin (4E6πt) + 0.5 V
9.4
(1)
(2)
ENx, SM
ENx, S0, S1
ENx, SM
VIH = 2 V
UNIT
454
–50
VI = 0 V
ENx, S0, S1
MAX
–20
10
VIL = 0.8 V
–10
VOY or VOZ = 0 V
±24
VOD = 0 V
±12
µA
µA
mA
pF
All typical values are at 25°C and with a 3.3-V supply.
The non-algebraic convention, where the more positive (least negative) limit is designated minimum, is used in this data sheet for the
input current (II) only.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
2.2
3.1
4.7
ns
tPHL
Propagation delay time, high-to-low-level output
2.2
3.1
4.7
ns
tr
Differential output signal rise time
0.3
0.8
1.2
ns
tf
Differential output signal fall time
0.8
1.2
ns
tsk(p)
Pulse skew (|tPHL– tPLH|) (2)
140
500
ps
tsk(o)
Output skew, channel-to-channel (3)
100
300
ps
RL = 100 Ω, CL = 10 pF,
See Figure 4
0.3
skew (4)
tsk(pp)
Part-to-part
1.5
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
5.7
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
7.7
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
3.2
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
3.2
15
ns
(1)
(2)
(3)
(4)
See Figure 5
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL measured at any two outputs.
tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
IOY
IIA
IIB
VID
A
Y
B
Z
IOZ
VOD
VOY
GND
VIA
VOC
VOZ
VIB
(VOY + VOZ)/2
Figure 1. Voltage and Current Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
APPLIED VOLTAGES
RESULTING COMMONMODE INPUT VOLTAGE
VIA
VIB
VID
VIC
1.25 V
1.15 V
100 mV
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
3.75 kΩ
Y
VOD
Input
Z
100 Ω
3.75 kΩ
±
Figure 2. VOD Test Circuit
6
0 V ≤ VTEST ≤ 2.4 V
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
Y
49.9 Ω ± 1% (2 Places)
Input
Input
VI
1.4 V
VI
1V
Z
50 pF
VOC(PP)
VOC(SS)
VOC
VO
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A
Y
B
Z
Input
1.4 V
1.2 V
1V
VIB
Input
VIA
tPLH
VOD
tPHL
100 Ω ± 1 %
100%
80%
VOD(H)
Output
CL = 10 pF
(2 Places)
0V
VOD(L)
tf
A.
20%
0%
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
7
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
Y
1 V or 1.4 V
49.9 Ω ± 1% (2 Places)
Z
1.4 V or 1 V
+
EN
EN
S0
S1
SM
Inputs
CL = 10 pF
(2 Places)
VOY
tPZH
tPHZ
VOY
or
VOZ
100%, ≅ 1.4 V
1.3 V
0%, 1.2 V
tPZL
A.
tPLZ
100%, 1.2 V
1.1 V
0%, ≅ 1 V
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
8
1.2 V
–
2V
1.4 V
0.8 V
Input
VOZ
or
VOY
VOZ
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PLH − Low-To-High Propagation Delay Time − ns
220
I CC − Supply Current − mA
200
180
VCC = 3.6 V
160
VCC = 3.3 V
140
VCC = 3 V
120
100
All Outputs Loaded
and Enabled
80
0
50
100
150
200
250
300
350
400
3.8
3.7
3.6
3.5
VCC = 3.3 V
3.4
VCC = 3 V
VCC = 3.6 V
3.3
3.2
3.1
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
f − Frequency − MHz
Figure 6.
Figure 7.
t PHL − High-To-Low Propagation Delay Time − ns
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.7
3.6
3.5
3.4
3.3
VCC = 3.3 V
VCC = 3.6 V
VCC = 3 V
3.2
3.1
3.0
2.9
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 8.
Figure 9. Typical Differential Eye Pattern at 400 Mbps
9
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS (continued)
P-P EYE-PATTERN JITTER
vs
PRBS SIGNALING RATE
900
TA = 25C
800
VCC = 3.6 V
Peak-to-Peak Jitter − ps
700
600
VCC = 3 V
500
400
300
200
100
0
0
100
200
300
400
500
600
Signaling Rate − Mbps
NOTES: Input: 215 PRBS with peak-to-peak jitter < 115 ps at 100 Mbps, all outputs enabled and loaded with differential
100-Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF ceramic 0805-style capacitors 1 cm from
the device.
Figure 10.
P-P PERIOD JITTER
vs
CLOCK FREQUENCY
20
VCC = 3.6 V
TA = 25C
18
Peak-to-Peak Jitter − ps
16
14
VCC = 3 V
12
10
8
6
4
2
0
0
100
200
300
400
500
600
Clock Frequency − MHz
NOTES: Input: 50% duty cycle square wave with period jitter < 10 ps at 100 MHz, all outputs enabled and loaded with
differential 100-Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF ceramic 0805-style capacitors
1 cm from the device.
Figure 11.
10
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
APPLICATION INFORMATION
FAIL SAFE
A common problem with differential signaling applications is how the system responds when no differential
voltage is present on the signal pair. The SN65LVDS116 receiver is like most differential line receivers, in that its
output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and
within its recommended input common-mode voltage range. Hovever, TI LVDS receivers handle the open-input
circuit situation differently.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 12. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 12. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in Figure 12. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
INPUT LEVEL TRANSLATION
An LVDS receiver can be used to receive various other types of logic signals. Figure 13 through Figure 21 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
VDD
25 Ω
50 Ω
A
50 Ω
B
1/2 VDD
0.1 µF
LVDS Receiver
Figure 13. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
11
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
APPLICATION INFORMATION (continued)
VDD
50 Ω
A
50 Ω
B
1.35 V < VTT < 1.65 V
0.1 µF
LVDS Receiver
Figure 14. Center-Tap Termination (CTT)
1.14 V < VTT < 1.26 V
VDD
50 Ω
1 kΩ
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 15. Gunning Transceiver Logic (GTL)
Z0
Z0
A
B
1.47 V < VTT < 1.62 V
0.1 µF
Figure 16. Backplane Transceiver Logic (BTL)
12
LVDS Receiver
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
APPLICATION INFORMATION (continued)
3.3 V
3.3 V
50 Ω
120 Ω
120 Ω
33 Ω
ECL
A
50 Ω
33 Ω
B
51 Ω
51 Ω
LVDS Receiver
Figure 17. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
5V
5V
50 Ω
82 Ω
82 Ω
100 Ω
ECL
A
50 Ω
100 Ω
33 Ω
B
33 Ω
LVDS Receiver
Figure 18. Positive Emitter-Coupled Logic (PECL)
13
SN65LVDS116
www.ti.com
SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005
APPLICATION INFORMATION (continued)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 19. 3.3-V CMOS
5V
5V
10 kΩ
560 Ω
A
B
560 Ω
3.3 kΩ
0.1 µF
LVDS Receiver
Figure 20. 5-V CMOS
5V
5V
10 kΩ
470 Ω
A
B
3.3 V
4 kΩ
Figure 21. TTL
14
0.1 µF
LVDS Receiver
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65LVDS116DGG
ACTIVE
TSSOP
DGG
64
25
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDS116
Samples
SN65LVDS116DGGR
ACTIVE
TSSOP
DGG
64
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDS116
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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