TAS5717
TAS5719
SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
www.ti.com
10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier
Check for Samples: TAS5717, TAS5719
FEATURES
1
•
2
•
•
Audio Input/Output
– TAS5717 Supports 2×10 W and TAS5719
Supports 2×15 W Output
– Wide PVDD Range, From 4.5 V to 26 V
– Efficient Class-D Operation Eliminates
Need for Heatsinks
– Requires Only 3.3 V and PVDD
– One Serial Audio Input (Two Audio
Channels)
– I2C Address Selection via PIN (Chip Select)
– Supports 8-kHz to 48-kHz Sample Rate
(LJ/RJ/I2S)
– External Headphone-Amplifier Shutdown
Signal
– Integrated CAP-Free Headphone Amplifier
– Stereo Headphone (Stereo 2-V RMS Line
Driver) Outputs
Audio/PWM Processing
– Independent Channel Volume Controls With
24-dB to Mute
– Programmable Two-Band Dynamic Range
Control
– 14 Programmable Biquads for Speaker EQ
– Programmable Coefficients for DRC Filters
– DC Blocking Filters
– 0.125-dB Fine Volume Support
General Features
– Serial Control Interface Operational Without
MCLK
– Factory-Trimmed Internal Oscillator for
Automatic Rate Detection
– Surface Mount, 48-Pin, 7-mm × 7-mm
HTQFP Package
– AD, BD, and Ternary PWM-Mode Support
– Thermal and Short-Circuit Protection
•
Benefits
– EQ: Speaker Equalization Improves Audio
Performance
– DRC: Dynamic Range Compression. Can
Be Used As Power Limiter. Enables
Speaker Protection, Easy Listening,
Night-Mode Listening
– DirectPath Technology: Eliminates Bulky
DC Blocking Capacitors
– Stereo Headphone/Stereo Line Drivers:
Adjust Gain via External Resistors,
Dedicated Active Headpone Mute Pin, High
Signal-to-Noise Ratio
– Two-Band DRC: Set Two Different
Thresholds for Low- and High-Frequency
Content
DESCRIPTION
The TAS5717/TAS5719 is a 10-W/15-W, efficient,
digital audio-power amplifier for driving stereo
bridge-tied speakers. One serial data input allows
processing of up to two discrete audio channels and
seamless integration to most digital audio processors
and MPEG decoders. The device accepts a wide
range of input data and data rates. A fully
programmable data path routes these channels to the
internal speaker drivers.
The TAS5717/9 is a slave-only device receiving all
clocks from external sources. The TAS5717/TAS5719
operates with a PWM carrier between a 384-kHz
switching rate and a 352-KHz switching rate,
depending on the input sample rate. Oversampling
combined with a fourth-order noise shaper provides a
flat noise floor and excellent dynamic range from
20 Hz to 20 kHz.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2010–2011, Texas Instruments Incorporated
TAS5717
TAS5719
SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM
3.3 V
4.5 V–26 V
AVDD/DVDD/
HP_VDD
PVDD
OUT_A
LRCLK
Digital
Audio
Source
SCLK
BST_A
MCLK
SDIN
LCBTL
BST_B
OUT_B
2
I C
Control
SDA
OUT_C
SCL
BST_C
Control
Inputs
RESET
LCBTL
BST_D
PDN
OUT_D
Loop
Filter
PLL_FLTP
(1)
PLL_FLTM
HPL_OUT
Headphone IN
(Single-Ended)
HPL_IN
HPR_OUT
HPL_OUT
HP_SD
B0264-13
(1)
See the TAS5717/9 User's Guide for loop-filter values.
2
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TAS5717
TAS5719
SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
www.ti.com
FUNCTIONAL VIEW
OUT_A
th
SDIN
Serial
Audio
Port
S
R
C
Digital Audio Processor
(DAP)
4
Order
Noise
Shaper
and
PWM
2´ HB
FET Out
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Click and Pop
Control
Sample Rate
Autodetect
and PLL
Serial
Control
Microcontroller
Based
System
Control
Terminal Control
HPL_IN
HPL_OUT
HPR_IN
HPR_OUT
Charge Pump
Headphone Amp/Line Driver
B0262-08
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3
4
R
L
1BQ
30
1BQ
26
0x77
0x76
0x73
0x72
9BQ
31–39
9BQ
27–2F
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2BQ
5A, 5B
2BQ
5E, 5F
2BQ
5C, 5D
2BQ
58, 59
0x75
0x74 v2im1
0x71
0x70
2
Vol
Vol
Vol2
Vol1
0x46[1]
0x46[0]
Vol Config Reg 0x0E
AGL
AGL
I C Subaddress in Red
0x52[0]
0x52[1]
0x51[0]
0x51[1]
2
2
32
Level
Meter
clip24
clip24
2
I C:0x6B (32Bit-Left Level)
32
32
32
I C:0x6C (32 Bit-Right Level)
I C:57
VDISTB
2
I C:56
VDISTA
B0321-11
24
24
TAS5717
TAS5719
SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
www.ti.com
DAP PROCESS STRUCTURE
© 2010–2011, Texas Instruments Incorporated
TAS5717
TAS5719
SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
www.ti.com
PIN ASSIGNMENT AND DESCRIPTIONS
PGND_CD
OUT_D
BST_C
OUT_C
BST_B
OUT_B
OUT_A
PGND_AB
BST_A
PVDD_AB
HP_PWMR
HP_PWML
PHP Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
HPL_IN
1
36
BST_D
HPL_OUT
2
35
PVDD_CD
HPR_OUT
3
34
GVDD_OUT
HPR_IN
4
33
HP_SD
HPVSS
5
32
SSTIMER
CPN
6
31
VREG
CPP
7
30
AGND
HPVDD
8
29
GND
AVSS
9
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
TAS5717
(TAS5719)
SCL
SDA
SDIN
SCLK
LRCLK
PDN
VR_DIG
DVSSO
MCLK
OSC_RES
A_SEL
AVDD
13 14 15 16 17 18 19 20 21 22 23 24
P0075-11
PIN FUNCTIONS
PIN
NAME
NO.
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
AGND
30
P
A_SEL
14
DIO
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
45
P
High-side bootstrap supply for half-bridge A
BST_B
41
P
High-side bootstrap supply for half-bridge B
BST_C
40
P
High-side bootstrap supply for half-bridge C
BST_D
36
P
High-side bootstrap supply for half-bridge D
CPN
6
IO
Charge-pump flying-capacitor negative connection
CPP
7
IO
Charge-pump flying-capacitor positive connection
DVDD
27
P
3.3-V digital power supply
DVSS
28
P
Digital ground
DVSSO
17
P
Oscillator ground
GND
29
P
Analog ground for power stage
(1)
(2)
Analog ground for power stage
This pin is monitored on the rising edge of RESET. A value of 0
makes the I2C dev address 0x54, and a value of 1 makes it 0x56.
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
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SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
GVDD_OUT
34
P
Gate drive internal regulator output
HPL_IN
1
AI
Headphone left IN (single-ended, analog IN)
HPL_OUT
2
AO
Headphone left OUT (single-ended, analog OUT)
HP_PWML
48
DO
PWM left-channel headphone out
HP_PWMR
47
DO
PWM right-channel headphone out
HPR_IN
4
AI
Headphone right IN (single-ended, analog IN)
HPR_OUT
3
AO
Headphone right OUT (single-ended, analog OUT)
HP_SD
33
AI
Headphone shutdown (active-low)
HPVDD
8
P
Headphone supply
HPVSS
5
P
Headphone ground
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
OSC_RES
16
AO
OUT_A
44
O
Output, half-bridge A
OUT_B
42
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
37
O
PDN
19
DI
PGND_AB
43
P
Power ground for half-bridges A and B
PGND_CD
38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop-filter terminal
PLL_FLTP
11
AO
PLL positive loop-filter terminal
PVDD_AB
46
P
PVDD_CD
35
P
RESET
25
DI
5-V
SCL
24
DI
5-V
SCLK
21
DI
5-V
SDA
23
DIO
5-V
SDIN
22
DI
5-V
SSTIMER
32
AI
Controls ramp time of OUT_X to minimize pop. Leave this pin floating
for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The
capacitor determines the ramp time.
STEST
26
DI
Factory test pin. Connect directly to DVSS.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG
31
P
Digital regulator output. Not to be used for powering external circuitry.
6
Oscillator trim resistor. Connect an 18-kΩ 1% resistor to DVSSO.
Output, half-bridge D
5-V
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating the PWM
stop sequence.
Power-supply input for half-bridge output A
Power-supply input for half-bridge output C
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard-mute
(high-impedance) state.
I2C serial control clock input
Pulldown
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
I2C serial control data interface input/output
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Input voltage
VALUE
UNIT
DVDD, AVDD, HPVDD
–0.3 to 3.6
V
PVDD_X
–0.3 to 30
V
HPL_IN, HPR_IN
–0.3 to 4.2
V
3.3-V digital input
–0.5 to DVDD + 0.5
V
(3)
V
–0.5 to AVDD + 2.5 (3)
V
OUT_x to PGND_x
22 (4)
V
BST_x to PGND_x
32
(4)
Input clamp current, IIK
±20
mA
Output clamp current, IOK
±20
mA
Operating free-air temperature
0 to 85
°C
Operating junction temperature range
0 to 150
°C
–40 to 125
°C
5-V tolerant
(2)
digital input (except MCLK)
5-V tolerant MCLK input
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
–0.5 to DVDD + 2.5
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6 V.
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
THERMAL INFORMATION
TAS5717
THERMAL METRIC (1)
PHP
UNIT
48 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
35.2
°C/W
θJB
Junction-to-board thermal resistance
10.9
°C/W
θJC(bottom)
Junction-to-case (bottom) thermal resistance (4)
1.6
°C/W
θJC(top)
Junction-to-case (top) thermal resistance (5)
19.7
°C/W
3.4
°C/W
10.1
°C/W
(6)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
3
3.3
3.6
UNIT
Digital/analog supply voltage
DVDD, AVDD
Half-bridge supply voltage
PVDD_X
VIH
High-level input voltage
5-V tolerant
VIL
Low-level input voltage
5-V tolerant
0.8
V
TA
Operating ambient temperature range
0
85
°C
Operating junction temperature range
0
125
°C
TJ
(1)
RL (BTL)
LO (BTL)
(1)
Load impedance
Output filter: L = 15 μH, C = 680 nF
Output-filter inductance
Minimum output inductance under
short-circuit condition
V
4.5
V
2
V
4
Ω
8
4.7
μH
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS FOR HEADPHONE/LINE DRIVER
Digital/analog supply voltage
HPVDD
MIN
NOM
MAX
3
3.3
3.6
R_hp_L
Headphone-mode load imedance
(HPL/HPR)
16
R_ln_L
Line-diver-mode load impedance
(HPL/HPR)
0.6
UNIT
V
32
Ω
10
kΩ
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate
VALUE
UNIT
11.025/22.05/44.1-kHz data rate ±2%
TEST CONDITIONS
352.8
kHz
48/24/12/8/16/32-kHz data rate ±2%
384
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
fMCLKI
tr /
tf(MCLK)
TEST CONDITIONS
MIN
MCLK Frequency
2.8224
MCLK duty cycle
40%
TYP
50%
Rise/fall time for MCLK
LRCLK allowable drift before LRCLK reset
Fcp
8
MAX
UNIT
24.576
MHz
60%
5
ns
4
MCLKs
External PLL filter capacitor C1
SMD 0603 Y5V
47
nF
External PLL filter capacitor C2
SMD 0603 Y5V
4.7
nF
External PLL filter resistor R
SMD 0603, metal film
Charge Pump Switching Frequency
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Ω
470
500
700
KHz
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TAS5719
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ELECTRICAL CHARACTERISTICS
DC Characteristics
TA = 25°, PVCC_X = 13 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD Mode, fS = 48 KHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VOH
High-level output voltage
FAULTZ and SDA
IOH = –4 mA
DVDD = 3 V
VOL
Low-level output voltage
FAULTZ and SDA
IOL = 4 mA
DVDD = 3 V
0.5
IIL
Low-level input current
VI < VIL ; DVDD = AVDD
= 3.6V
75
IIH
High-level input current
VI > VIH ; DVDD =
AVDD = 3.6V
75
IDD
3.3 V supply current
3.3 V supply voltage (DVDD,
AVDD)
IPVDD
Half-bridge supply current
No load (PVDD_X)
rDS(on)
(1)
UNIT
2.4
V
Normal mode
48
70
Reset (RESET = low,
PDN = high)
21
32
Normal mode
20
34
5
13
Reset (RESET = low,
PDN = high)
Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance
200
Drain-to-source resistance,
HS
TJ = 25°C, includes metallization resistance
200
3.5
V
μA
μA
mA
mA
mΩ
I/O Protection
Vuvp
Undervoltage protection limit
PVDD falling
Vuvp,hyst
Undervoltage protection limit
PVDD rising
OTE (2)
Overtemperature error
OTEHYST
(2)
Extra temperature drop
required to recover from error
V
4.5
V
150
°C
30
°C
IOC
Overcurrent limit protection
4.5
A
IOCT
Overcurrent response time
150
ns
RPD
Internal pulldown resistor at
the output of each half-bridge
3
kΩ
(1)
(2)
Connected when drivers are tristated to provide bootstrap
capacitor charge.
This does not include bond-wire or pin resistance.
Specified by design
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AC Characteristics (BTL)
PVDD_X = 12 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, audio frequency = 1 kHz, (unless otherwise noted). All performance
is in accordance with recommended operating conditions, unless otherwise specified.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
10
PVDD = 8 V, 10% THD, 1-kHz input signal
4.1
PVDD = 18 V, 10% THD, 1-kHz input
signal
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise (rms)
SNR
(1)
(2)
Signal-to-noise ratio
15
0.13%
PVDD = 8 V; PO = 1 W
0.2%
UNIT
W
μV
56
PO = 0.25 W, f = 1 kHz (BD mode)
–82
PO = 0.25 W, f = 1 kHz (AD mode)
–69
A-weighted, f = 1 kHz, maximum power at
THD < 1%
(2)
MAX
(1)
PVDD = 13 V; PO = 1 W
A-weighted
Crosstalk
TYP
PVDD = 13 V, 10% THD, 1-kHz input
signal
dB
–105
dB
15 W is supported only in the TAS5719.
SNR is calculated relative to 0-dBFS input level.
AC Characteristics (Headphone/Line Driver)
PVDD_X = 12 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, audio frequency = 1 kHz, (unless otherwise noted). All performance
is in accordance with recommended operating conditions, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
Po(hp)
Headphone power output per channel
HP_VDD = 3.3 V (Rhp = 32 Ω; THD 1%)
HP_gain
Headphone gain
Adjustable via Rin and Rfb
SNR_hp
Sgnal-to-noise ratio (headphone mode)
SNR_ln
Sgnal-to-noise ratio (line driver mode)
10
TYP
MAX
UNIT
25
mW
Rhp = 32 Ω
101
dB
2-V rms output
105
dB
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
CL = 30 pF
1.024
LRCLK frequency
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
tr /
tf(SCLK/LRCLK)
Rise/fall time for SCLK/LRCLK
kHz
32
64
SCLK
edges
–1/4
1/4
SCLK
period
8
tr
ns
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 1. Slave Mode Serial Data Interface Timing
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I2C SERIAL CONTROL PORT OPERATION
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
No wait states
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
tf
Fall time, SCL and SDA
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
tsu2
MAX
UNIT
400
kHz
μs
μs
300
ns
300
ns
100
ns
0
ns
Bus free time between stop and start condition
1.3
μs
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
μs
400
tw(H)
tw(L)
pF
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
12
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RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER
tw(RESET)
MIN
Pulse duration, RESET active
TYP
2
td(I2C_ready)
MAX
UNIT
μs
100
Time to enable I C
12
ms
RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTES: 1. On power up, it is recommended that the TAS5717/9 RESET be held LOW for at least 100 μs after DVDD has
reached 3 V.
2. If RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs
after PDN is deasserted (HIGH).
Figure 4. Reset Timing
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
10
PVDD = 8V
RL = 8Ω
TA = 25°C
PVDD = 12V
RL = 8Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
PO = 1W
PO = 2.5W
PO = 5W
0.001
20
100
PO = 1W
PO = 2.5W
PO = 5W
1k
Frequency (Hz)
10k
0.001
20k
20
SPACER
SPACER
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SPACER
SPACER
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
20k
10
PVDD = 24V
RL = 8Ω
TA = 25°C
1
THD+N (%)
1
THD+N (%)
10k
Figure 6.
PVDD = 18V
RL = 8Ω
TA = 25°C
0.1
0.01
0.1
0.01
PO = 1W
PO = 2.5W
PO = 5W
20
100
PO = 1W
PO = 2.5W
PO = 5W
1k
Frequency (Hz)
10k
20k
0.001
20
Figure 7.
14
1k
Frequency (Hz)
Figure 5.
10
0.001
100
100
1k
Frequency (Hz)
10k
20k
Figure 8.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued)
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
10
PVDD = 8V
RL = 8Ω
TA = 25°C
PVDD = 12V
RL = 8Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
f = 20Hz
f = 1kHz
0.001
0.01
0.1
1
Output Power (W)
10
f = 20Hz
f = 1kHz
0.001
0.01
40
1
Output Power (W)
10
Figure 9.
Figure 10.
SPACER
SPACER
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
SPACER
SPACER
SPACER
SPACER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
40
10
PVDD = 18V
RL = 8Ω
TA = 25°C
PVDD = 24V
RL = 8Ω
TA = 25°C
1
THD+N (%)
1
THD+N (%)
0.1
0.1
0.01
0.1
0.01
f = 20Hz
f = 1kHz
f = 10kHz
0.001
0.01
0.1
1
Output Power (W)
10
40
f = 20Hz
f = 1kHz
0.001
0.01
Figure 11.
0.1
1
Output Power (W)
10
40
Figure 12.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued)
SPACER
TAS5717
OUTPUT POWER
vs
SUPPLY VOLTAGE
SPACER
TAS5717
EFFICIENCY
vs
OUTPUT POWER
40
100
RL = 8Ω
T A = 25°C
35
90
80
30
Efficiency (%)
Output Power (W)
70
25
20
15
60
50
40
30
10
20
5
PVDD = 8V
PVDD = 12V
PVDD = 18V
PVDD = 24V
10
THD+N = 1%
THD+N = 10%
0
RL = 8Ω
T A = 25°C
0
8
10
12
14
16
18
20
Supply Voltage (V)
22
24
26
NOTE: Dashed lines represent thermally limited region.
Figure 13.
0
5
10
15
20
25
Total Output Power (W)
30
35
NOTE: Dashed lines represent thermally limited region.
Figure 14.
SPACER
SPACER
SPACER
TAS5719
OUTPUT POWER
vs
SUPPLY VOLTAGE
SPACER
SPACER
SPACER
TAS5719
EFFICIENCY
vs
OUTPUT POWER
40
100
RL = 8Ω
T A = 25°C
35
90
80
30
25
Efficiency (%)
Output Power (W)
70
20
15
60
50
40
30
10
20
5
THD+N = 1%
THD+N = 10%
0
10
RL = 8Ω
T A = 25°C
0
8
10
12
14
16
18
20
Supply Voltage (V)
22
NOTE: Dashed lines represent thermally limited region.
Figure 15.
16
PVDD = 8V
PVDD = 12V
PVDD = 18V
PVDD = 24V
24
26
0
5
10
15
20
25
Total Output Power (W)
30
35
NOTE: Dashed lines represent thermally limited region.
Figure 16.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued)
SPACER
SPACER
CROSSTALK
vs
FREQUENCY
SPACER
SPACER
CROSSTALK
vs
FREQUENCY
0
0
PO = 1W
PVDD = 8V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
PO = 1W
PVDD = 12V
RL = 8Ω
TA = 25°C
−10
20
100
1k
Frequency (Hz)
10k
20k
−100
20
100
1k
Frequency (Hz)
Figure 17.
Figure 18.
SPACER
SPACER
SPACER
SPACER
CROSSTALK
vs
FREQUENCY
SPACER
SPACER
SPACER
SPACER
CROSSTALK
vs
FREQUENCY
10k
20k
0
0
PO = 1W
PVDD = 18V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
PO = 1W
PVDD = 24V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−30
−40
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−50
−60
−70
−80
−70
−90
−80
−100
−90
−100
−110
20
100
1k
Frequency (Hz)
10k
20k
−120
20
Figure 19.
100
1k
Frequency (Hz)
10k
20k
Figure 20.
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TYPICAL CHARACTERISTICS, HEADPHONE TESTS, SE CONFIGURATION, 32Ω
SPACER
ANALOG IN
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SPACER
PWM IN
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
10
HPVDD = 3.3V
RL = 32Ω
TA = 25°C
HPVDD = 3.3V
RL = 32Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
PO = 10mW
0.001
20
100
PO = 10mW
1k
Frequency (Hz)
10k
20k
0.001
20
Figure 21.
18
100
1k
Frequency (Hz)
10k
20k
Figure 22.
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TYPICAL CHARACTERISTICS, LINE DRIVER TESTS, SE CONFIGURATION, 5kΩ
SPACER
ANALOG IN
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SPACER
PWM IN
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
10
10
HPVDD = 3.3V
RL = 5kΩ
TA = 25°C
PVDD =3.3V
RL = 5kΩ
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
VO = 1Vrms
0.001
20
100
f = 1kHz
1k
Frequency (Hz)
10k
20k
0.001
10m
100m
Output Voltage (V)
Figure 23.
1
4
Figure 24.
SPACER
SPACER
SPACER
ANALOG IN
CROSSTALK
vs
FREQUENCY
0
VO = 1Vrms
PVDD = 3.3V
RL = 5kΩ
TA = 25°C
−10
−20
Right to Left
Left to Right
Crosstalk (dB)
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
Frequency (Hz)
10k
20k
Figure 25.
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DETAILED DESCRIPTION
POWER SUPPLY
To facilitate system design, the TAS5717/9 needs only a 3.3-V supply in addition to the (typical) 13-V
power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry.
Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by
built-in bootstrap circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_X) and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are
derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The TAS5717/9 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
I2C CHIP SELECT/HP_SHUTDOWN
A_SEL/HP_SD is an input pin during power up. It can be pulled high or low. HIGH indicates an I2C subaddress
of 0x56, and LOW a subaddress of 0x54.
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored a protection system. If the high-current condition situation persists, i.e.,
the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power
stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D are shut down.
Overtemperature Protection
The TAS5717/9 has an overtemperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5717/9 recovers automatically once the
temperature drops approximately 30°.
20
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Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5717/9 fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the PVDD and AVDD supply voltages reach 4.5 V and 2.7 V, respectively. Although PVDD
and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or on either
PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT
being asserted low.
CLOCK, AUTO DETECTION, AND PLL
The TAS5717/9 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register
.
The TAS5717/9 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1
× fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock-control logic to the appropriate settings for all supported clock
rates as defined in the clock control register.
TAS5717/9 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)
and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system autodetects the new rate and reverts to normal operation. During this process, the default volume is
restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly
(also called soft unmute) as defined in volume register (0x0E).
SERIAL DATA INTERFACE
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5717/9 DAP accepts serial data
in 16-, 20-, or 24-bit left-justified, right-justified, or I2S serial data format.
PWM Section
The TAS5717/9 DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve
high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise
shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from
the DAP and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1- and 48-kHz are included and can be
enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC and EQ, see the User's Guide and
TAS570X GDE software development tool documentation. Also see the GDE software development tool for the
device data path.
I2C COMPATIBLE SERIAL CONTROL INTERFACE
The TAS5717/9 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multiple-byte read and write operations for status
registers and the general control registers associated with the PWM.
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SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data-bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 26. I2S 64-fS Format
22
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2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 27. I2S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 28. I2S 32-fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data-bit positions.
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2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 29. Left-Justified 64-fS Format
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 30. Left-Justified 48-fS Format
24
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2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 31. Left-Justified 32-fS Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks
unused leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 32. Right-Justified 64-fS Format
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 33. Right-Justified 48-fS Format
Figure 34. Right-Justified 32-fS Format
26
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I2C SERIAL CONTROL INTERFACE
The TAS5717/9 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-yte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 35. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5717/9 holds SDA low during the acknowledge
clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 35. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 35.
The 7-bit address for TAS5717/9 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for
0x54 and pullup for 0x56).Stero device with Headphone should use 0x54 as its device address.
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
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Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5717/9 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by
data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS5717/9. For I2C sequential write
transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,
before a stop or start is transmitted, determines how many subaddresses are written. As was true for random
addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data
is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is
accepted; only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 36, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5717/9 internal memory address being accessed. After receiving the address
byte, the TAS5717/9 again responds with an acknowledge bit. Next, the master device transmits the data byte to
be written to the memory address being accessed. After receiving the data byte, the TAS5717/9 again responds
with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte
data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 36. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 37. After receiving each data byte, the
TAS5717/9 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
Subaddress
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 37. Multiple-Byte Write Transfer
28
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Single-Byte Read
As shown in Figure 38, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5717/9 address
and the read/write bit, TAS5717/9 responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5717/9
address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After
receiving the address and the read/write bit, the TAS5717/9 again responds with an acknowledge bit. Next, the
TAS5717/9 transmits the data byte from the memory address being read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read
transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A0 R/W ACK D7
A1
D6
2
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
T0036-03
Figure 38. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5717/9 to the master device as shown in Figure 39. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
Subaddress
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 39. Multiple-Byte Read Transfer
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Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
high-band left/right channels and one DRC for the low-band left/right channels.
The DRC input/output diagram is shown in Figure 40.
See the GDE software tool for more description on the T, K, and O parameters.
Output Level (dB)
K
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0091-03
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each DRC has adjustable threshold levels.
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 40. Dynamic Range Control
Energy
Filter
Threshold
Detect
Attack
and
Decay
Filters
a, w
T
aa, wa / ad, wd
DRC1
0x3B
0x40
0x3C
DRC2
0x3E
0x43
0x3F
Audio Input
DRC Coefficient
Alpha Filter Structure
S
a
w
–1
Z
B0265-04
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 41. DRC Structure
30
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PWM LEVEL METER
The structure in Figure 42 shows the PWM level meter that can be used to study the power profile.
Post-DAP Processing
1–a
–1
Z
Ch1
a
ABS
32-Bit Level
rms
ADDR = 0x6B
2
I C Registers
(PWM Level Meter)
1–a
–1
Z
Ch2
a
ABS
32-Bit Level
rms
ADDR = 0x6C
B0396-01
Figure 42. PWM Level Meter Structure
26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This
is shown in Figure 43 .
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 43. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 43. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 44 applied to obtain the magnitude
of the negative number.
1
0
2 Bit
2 Bit
1
2
0
–1
Bit
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 44. Conversion Weighting Factors—3.23 Format to Floating Point
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Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 45
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
Figure 45. Alignment of 3.23 Coefficient in 32-Bit I2C Word
Table 1. Sample Calculation for 3.23 Format
db
Linear
Decimal
Hex (3.23 Format)
0
1
8,388,608
80 0000
5
1.77
14,917,288
00E3 9EA8
–5
0.56
4,717,260
0047 FACC
X
L = 10(X/20)
D = 8388608 × L
H = dec2hex (D, 8)
Table 2. Sample Calculation for 9.17 Format
32
db
Linear
Decimal
0
1
131,072
Hex (9.17 Format)
20 000
5
1.77
231,997
38 A3D
–5
0.56
73,400
11 EB8
X
L = 10(X/20)
D = 131,072 × L
H = dec2hex (D, 8)
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Table 3. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
INITIALIZATION
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0xC1
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
2
Description shown in subsequent section
0x03FF (mute)
0x08
Channel 1 vol
2
Description shown in subsequent section
0x00C0 (0 dB)
0x09
Channel 2 vol
2
Description shown in subsequent section
0x00C0 (0 dB)
0x0A
Channel 3 vol
2
Description shown in subsequent section
0x00C0 (0 dB)
1
Reserved (1)
1
Description shown in subsequent section
0x0B–0x0D
0x0E
Volume configuration register
0x0F
1
Reserved
0x10
Modulation limit register
1
Description shown in subsequent section
0x01
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
1
Reserved (1)
0x15–0x19
0x1A
Start/stop period register
1
0x68
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x1D–0x1F
0x57
(1)
1
Reserved
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
0x22–0x24
(1)
4
Reserved
0x25
PWM MUX register
4
Description shown in subsequent section
0x0102 1345
0x26
ch1_bq[0]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x27
0x28
(1)
0xF0
(1)
ch1_bq[1]
ch1_bq[2]
20
20
Reserved registers should not be accessed.
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
34
REGISTER NAME
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch1_bq[7]
ch1_bq[8]
ch1_bq[9]
ch2_bq[0]
ch2_bq[1]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
REGISTER NAME
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
ch2_bq[7]
ch2_bq[8]
ch2_bq[9]
0x3A
0x3B
DRC1 softening filter alpha
NO. OF
BYTES
20
20
20
20
20
20
20
20
DRC1 attack rate
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
(2)
Reserved
8
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0x0078 0000
8
DRC1 release rate
(2)
INITIALIZATION
VALUE
4
DRC1 softening filter omega
0x3C
CONTENTS
0x0000 0100
0xFFFF FF00
Reserved registers should not be accessed.
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
REGISTER NAME
0x3D
0x3E
DRC2 softening filter alpha
NO. OF
BYTES
8
Reserved (3)
8
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0xFFF8 0000
DRC2 softening filter omega
0x3F
DRC2 attack rate
8
u[31:26], at[25:0]
0x0008 0000
u[31:26], rt[25:0]
0xFFF8 0000
4
T1[31:0] (9.23 format)
0x0800 0000
4
Reserved
(3)
4
T2[31:0] (9.23 format)
4
Reserved (3)
4
Description shown in subsequent section
DRC2 release rate
0x40
DRC1 attack threshold
0x41–0x42
0x43
DRC2 attack threshold
0x44–0x45
0x46
DRC control
0x47–0x4E
0x0002 0000
(3)
4
Reserved
PWM switching rate control
4
u[31:4], src[3:0]
0x0000 0008
0x50
EQ control
4
Description shown in subsequent section
0x0F70 8000
0x51
Ch 1 output mixer
8
Ch 1 output mix1[1]
0x0080 0000
Ch 2 output mixer
8
Ch 1 output mix1[0]
0x0000 0000
Ch 2 output mix2[1]
0x0080 0000
Ch 2 output mix2[0]
0x0000 0000
0x53
16
Reserved (3)
0x54
16
Reserved (3)
4
u[31:26], post[25:0]
0x0080 0000
0x56
Output post-scale
0x57
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
0x58
ch1_bq[10]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x59
0x5A
0x5B
36
0x0074 0000
0x4F
0x52
(3)
INITIALIZATION
VALUE
CONTENTS
ch1_bq[11]
ch4_bq[0]
ch4_bq[1]
20
20
20
Reserved registers should not be accessed.
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x5C
0x5D
0x5E
0x5F
NO. OF
BYTES
REGISTER NAME
ch2_bq[10]
20
ch2_bq[11]
20
ch3_bq[0]
20
ch3_bq[1]
20
0x60–0x61
0x62
4
IDF post scale
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Reserved
(4)
4
0x0000 0080
Reserved (4)
0x63–0x6A
0x6B
Left channel PWM level meter
4
Data[31:0]
0x0000 0000
0x6C
Right channel PWM level meter
4
Data[31:0]
0x0000 0000
Reserved (4)
0x6D–0x6F
0x70
ch1 inline mixer
4
u[31:26], in_mix1[25:0]
0x0080 0000
0x71
inline_DRC_en_mixer_ch1
4
u[31:26], in_mixdrc_1[25:0]
0x0000 0000
0x72
ch1 right_channel mixer
4
u[31:26], right_mix1[25:0]
0x0000 0000
0x73
ch1 left_channel_mixer
4
u[31:26], left_mix_1[25:0]
0x0080 0000
0x74
ch2 inline mixer
4
u[31:26], in_mix2[25:0]
0x0080 0000
0x75
inline_DRC_en_mixer_ch2
4
u[31:26], in_mixdrc_2[25:0]
0x0000 0000
0x76
ch2 left_chanel mixer
4
u[31:26], left_mix1[25:0]
0x0000 0000
0x77
ch2 right_channel_mixer
4
u[31:26], right_mix_1[25:0]
0x0080 0000
Reserved (4)
0x78–0xF7
0xF8
Update dev address key
4
Dev Id Update Key[31:0] (Key =
0xF9A5A5A5)
0x0000 0000
0xF9
Update dev address reg
4
u[31:8],New Dev Id[7:0] (New Dev Id = 0x38
for TAS5717/9)
0x0000 0054
4
Reserved (4)
0xFA–0xFF
(4)
INITIALIZATION
VALUE
CONTENTS
Reserved registers should not be accessed.
All DAP coefficients are 3.23 format unless specified otherwise.
Registers 0x3B through 0x46 should be altered only during the initialization phase.
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CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5717/9. The clock control register contains
the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
Table 4. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved
0
1
0
–
–
–
–
–
Reserved
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate (1)
1
0
0
–
–
–
–
–
fS = 16-kHz sample rate
1
0
1
–
–
–
–
–
fS = 22.05/24-kHz sample rate
1
1
0
–
–
–
–
–
fS = 8-kHz sample rate
1
1
1
–
–
–
–
–
fS = 11.025/12-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (2)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (2)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS (3)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved
–
–
–
1
1
1
–
–
Reserved
–
–
–
–
–
–
0
–
Reserved (1)
–
–
–
–
–
–
–
0
Reserved (1)
(1)
(2)
(3)
(4)
FUNCTION
(1) (4)
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates
Rate only available for 32/44.1/48-KHz sample rates
Not available at 8 kHz
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 5. General Status Register (0x01)
D7
0
(1)
38
D6
0
D5
0
D4
D3
0
0
D2
0
D1
0
D0
0
FUNCTION
Identification code
(1)
Default values are in bold.
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ERROR STATUS REGISTER (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error definitions:
• MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK error: The number of SCLKs per LRCLK is changing.
• LRCLK error: LRCLK frequency is changing.
• Frame slip: LRCLK phase is drifting with respect to internal frame sync.
Table 6. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, overvoltage, or undervoltage error
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
No errors
(1)
FUNCTION
(1)
Default values are in bold.
SYSTEM CONTROL REGISTER 1 (0x03)
System control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff
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