TPS53353
SLUSAK2D – AUGUST 2011 – REVISEDTPS53353
APRIL 2021
SLUSAK2D – AUGUST 2011 – REVISED APRIL 2021
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TPS53353 High-Efficiency 20-A Synchronous Buck SWIFT™ Converter With Ecomode™
1 Features
2 Applications
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New product available: TPS548B28 16-V, 20-A
synchronous-buck converter with remote sense
Conversion input voltage range: 1.5 V to 15 V
VDD input voltage range: 4.5 V to 25 V
92% efficiency from 12 V to 1.5 V at 20 A
Output voltage range: 0.6 V to 5.5 V
5-V LDO output
Supports single-rail input
Integrated power MOSFETs with 20 A of
continuous output current
Auto-skip Eco-mode™ for light-load efficiency
< 10-μA shutdown current
D-CAP™ mode with fast transient response
Selectable switching frequency from 250 kHz to 1
MHz with external resistor
Selectable auto-skip or PWM-only operation
Built-in 1% 0.6-V reference
0.7-ms, 1.4-ms, 2.8-ms, and 5.6-ms selectable
internal voltage servo soft start
Integrated boost switch
Precharged start-up capability
Adjustable overcurrent limit with thermal
compensation
Overvoltage, undervoltage, UVLO, and
overtemperature protection
Supports all ceramic output capacitors
Open-drain power-good indication
Incorporates NexFET™ power block technology
22-pin QFN package with PowerPAD™
For SWIFT™ power products documentation, see
http://www.ti.com/swift
Enterprise rack Servers and storage
Wired networking switches and routers
ASIC, SoC, FPGA, DSP core, and I/O voltage
3 Description
TPS53353 is a D-CAP™ mode, 20-A synchronous
switcher with integrated MOSFETs. It is designed
for ease of use, low external component count, and
space-conscious power systems.
This device features 5.5-mΩ / 2.2-mΩ integrated
MOSFETs, accurate 1%, 0.6-V reference, and
integrated boost switch. A sample of competitive
features include: a conversion input voltage range
from 1.5 V to 15 V, very low external component
count, D-CAP™ mode control for super fast transient,
auto-skip mode operation, internal soft-start control,
selectable frequency, and no need for compensation.
The conversion input voltage ranges from 1.5 V to 15
V, the supply voltage range is from 4.5 V to 25 V, and
the output voltage range is from 0.6 V to 5.5 V.
The device is available in 5-mm × 6-mm, 22-pin QFN
package and is specified from –40°C to 85°C.
The TPS548B28 is a newer 20A device designed
for data center applications with a smaller, Pb-free
package.
Device Information(1)
PART NUMBER
TPS53353
(1)
PACKAGE
BODY SIZE (NOM)
LSON-CLIP (22)
6.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VVDD
20
19
18
17
16
15
14
13
VDD
VREG
VIN
VIN
VIN
VIN
VIN
LL
LL
4
5
6
7
LL
N/C
3
LL
VBST
2
LL
PGOOD
1
LL
EN
GND
VFB
TPS53353
VREG
12
VIN
21
TRIP
RF
22
MODE
VIN
8
9
10
11
VOUT
PGOOD
EN
UDG-11047
Copyright © 2016, Texas Instruments Incorporated
Simplified Application
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings(1) .................................... 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 20
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 Receiving Notification of Documentation Updates.. 32
11.3 Support Resources................................................. 32
11.4 Trademarks............................................................. 32
11.5 Electrostatic Discharge Caution.............................. 32
11.6 Glossary.................................................................. 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2016) to Revision D (April 2021)
Page
• Added TPS548B28 information to Section 1 as a newer 20A device in a smaller package...............................1
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Added TPS548B28 information to Section 3 as a newer 20A device in a smaller package...............................1
• Changed the EN waveform and overall delay time on Figure 7-1 and updated and moved the Figure 7-1 note
into the Section 7.3.1 description .....................................................................................................................14
• Added BST Resistor Selection to Section 8.2.2.2.1 ........................................................................................ 24
• Added Equation 19 and supporting information................................................................................................25
• MODE and RF pins updated in Figure 10-1 .................................................................................................... 31
Changes from Revision B (February 2015) to Revision C (February 2016)
Page
• Changed the datasheet Title From: "TPS53353 High-Efficiency 20-A Synchronous Buck Converter With Ecomode™" To: "TPS53353 High-Efficiency 20-A Synchronous Buck SWIFT™ Converter With Eco-mode™"..... 1
• Added Section 1: "For SWIFT™ Power Product Documentation..."...................................................................1
Changes from Revision A (April 2012) to Revision B (February 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision Original (August 2011) to Revision A (April 2012)
Page
• Changed conversion input voltage from "3 V" to "1.5 V".................................................................................... 1
• Changed VIN input voltage range minimum from "3 V" to "1.5 V"...................................................................... 3
• Changed to correct typographical error in THERMAL INFORMATION table......................................................4
• Changed VIN (main supply) input voltage range minimum from "3 V' to "1.5 V" in Section 6.3 ........................ 4
• Changed conversion input voltage range from "3 V" to "1.5" in Section 7.1 ....................................................13
• Added note to the Section 7.3 ......................................................................................................................... 13
• Changed "ripple injection capacitor" to "ripple injection resistor" in the last bullet of the Layout Guidelines
section.............................................................................................................................................................. 30
2
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5 Pin Configuration and Functions
A.
VFB
1
22
RF
EN
2
21
TRIP
PGOOD
3
20
MODE
VBST
4
19
VDD
N/C
5
18
VREG
LL
6
17
VIN
LL
7
16
VIN
LL
8
15
VIN
LL
9
14
VIN
LL
10
13
VIN
LL
11
12
VIN
GND
PowerPad
TM
N/C = no connection
Figure 5-1. 22-Pins LSON-CLIP DQP Package (Top View)
Table 5-1. Pin Functions
PIN
NAME
EN
NO.
2
GND
TYPE(1)
DESCRIPTION
I
Enable pin.Typical turnon threshold voltage is 1.2 V. Typical turnoff threshold voltage is 0.95 V.
G
Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
B
Output of converted power. Connect this pin to the output Inductor.
I
Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 7-3. The softstart time is detected and stored into internal register during start-up.
6
7
8
LL
9
10
11
MODE
20
N/C
5
PGOOD
3
O
Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB
goes out of the specified limits PGOOD goes low after a 2-µs delay
RF
22
I
Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using
Table 7-1. The switching frequency is detected and stored during the startup.
TRIP
21
I
No connect.
OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 4700 ppm/°C current is sourced
and set the OCL trip voltage as follows.
space VOCL=VTRIP/32
(VTRIP ≤ 1.2 V, VOCL ≤ 37.5 mV)
VBST
4
P
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node.
Internally connected to VREG via bootstrap MOSFET switch.
VDD
19
P
Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.
1
I
Output feedback input. Connect this pin to Vout through a resistor divider.
P
Conversion power input.The conversion input voltage range is from 1.5 V to 15 V.
P
5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry.
VFB
12
13
14
VIN
15
16
17
VREG
(1)
18
I=Input, O=Output, B=Bidirectional, P=Supply, G=Ground
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6 Specifications
6.1 Absolute Maximum Ratings(1)
Input voltage range
MIN
MAX
VIN (main supply)
–0.3
25
VDD
–0.3
28
VBST
–0.3
32
VBST(with respect to LL)
–0.3
7
EN, TRIP, VFB, RF, MODE
–0.3
7
DC
–2
25
Pulse < 20ns, E=5 μJ
–7
27
PGOOD, VREG
–0.3
7
GND
–0.3
0.3
LL
Output voltage range
Source/Sink current
VBST
50
V
V
mA
Operating free-air temperature, TA
–40
Junction temperature, TJ
–40
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
85
°C
150
300
Storage temperature, Tstg
(1)
UNIT
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage range
MIN
MAX
VIN (main supply)
1.5
15
VDD
4.5
25
VBST
4.5
28
VBST(with respect to LL)
EN, TRIP, VFB, RF, MODE
Output voltage range
LL
PGOOD, VREG
Junction temperature range, TJ
4
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4.5
6.5
–0.1
6.5
–1
22
–0.1
6.5
–40
125
UNIT
V
V
°C
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6.4 Thermal Information
TPS53353
THERMAL
METRIC(1)
DQP (LSON-CLIP)
UNIT
22 PINS
θJA
Junction-to-ambient thermal resistance
27.2
θJCtop
Junction-to-case (top) thermal resistance
17.1
θJB
Junction-to-board thermal resistance
5.9
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
5.8
θJCbot
Junction-to-case (bottom) thermal resistance
1.2
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VVIN
VIN pin power conversion input
voltage
VVDD
Supply input voltage
IVIN(leak)
VIN pin leakage current
1.5
15
4.5
25
V
1
µA
VEN = 0 V
IVDD
VDD supply current
TA = 25°C, No load, VEN = 5 V, VVFB = 0.630 V
IVDDSDN
VDD shutdown current
TA = 25°C, No load, VEN = 0 V
420
V
590
µA
10
µA
INTERNAL REFERENCE VOLTAGE
CCM condition(1)
VVFB
VFB regulation voltage
VVFB
VFB regulation voltage
0°C ≤ TA ≤ 85°C
IVFB
VFB input current
VVFB = 0.630 V, TA = 25°C
TA = 25°C
–40°C ≤ TA ≤ 85°C
0.6
V
0.597
0.6
0.603
0.5952
0.6
0.6048
0.594
V
0.6
0.606
0.01
0.2
µA
5
5.36
V
LDO OUTPUT
VVREG
LDO output voltage
current(1)
IVREG
LDO output
VDO
Low drop out voltage
0 mA ≤ IVREG ≤ 30 mA
4.77
Maximum current allowed from LDO
30
mA
230
mV
0.1
0.2
V
0.01
1.5
µA
260
400
ns
VVDD = 4.5 V, IVREG = 30 mA
BOOT STRAP SWITCH
VFBST
Forward voltage
VVREG-VBST, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VVBST = 23 V, VSW = 17 V, TA = 25°C
DUTY AND FREQUENCY CONTROL
tOFF(min)
tON(min)
Minimum off time
TA = 25°C
Minimum on time
VIN = 17 V, VOUT = 0.6 V, RRF = 39 kΩ,
TA = 25 °C(1)
150
35
ns
SOFT START
tSS
Internal soft-start time from
VOUT = 0 V to 95% of VOUT
RMODE = 39 kΩ
0.7
RMODE = 100 kΩ
1.4
RMODE = 200 kΩ
2.8
RMODE = 470 kΩ
5.6
ms
INTERNAL MOSFETs
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Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
RDS(on)H
High-side MOSFET on-resistance
TA = 25 °C
5.5
RDS(on)L
Low-side MOSFET on-resistance
TA = 25 °C
2.2
MAX
UNIT
mΩ
POWERGOOD
VTHPG
PG threshold
PG in from lower
92.5%
PG in from higher
107.5%
PG hysteresis
RPG
PG transistor on-resistance
tPGDEL
PG delay
Delay for PG in
95%
98.5%
110% 112.5%
2.5%
5%
7.5%
15
30
55
Ω
0.8
1
1.2
ms
LOGIC THRESHOLD AND SETTING CONDITIONS
VEN
EN Voltage
IEN
EN Input current
Enable
1.8
Disable
0.6
VEN = 5 V
RRF = 0 Ω to GND, TA =
1
25°C(2)
200
250
300
RRF = 187 kΩ to GND, TA = 25°C(2)
250
300
350
25°C(2)
350
400
450
450
500
550
25°C(2)
580
650
720
RRF = 309 kΩ to VREG, TA = 25°C(2)
670
750
820
25°C(2)
RRF = 619 kΩ, to GND, TA =
fSW
Switching frequency
RRF = Open, TA= 25°C(2)
RRF = 866 kΩ to VREG, TA =
RRF = 124 kΩ to VREG, TA =
770
850
930
RRF = 0 Ω to VREG, TA = 25°C(2)
880
970
1070
9.4
10
10.6
V
µA
kHz
PROTECTION: CURRENT SENSE
ITRIP
TRIP source current
VTRIP = 1 V, TA = 25°C
TCITRIP
TRIP current temperature
coeffficient
On the basis of 25°C(1)
VTRIP
Current limit threshold setting range VTRIP-GND
VOCL
Current limit threshold
VOCLN
Negative current limit threshold
VAZCADJ
Auto zero cross adjustable range
4700
ppm/°C
0.4
1.2
VTRIP = 1.2 V
32
37.5
43
VTRIP = 0.4
7.5
12.5
17.5
VTRIP = 1.2 V
–160
–150
–140
VTRIP = 0.4 V
–58
–50
–42
3
15
Positive
Negative
µA
–15
–3
120%
125%
V
mV
mV
mV
PROTECTION: UVP and OVP
VOVP
OVP trip threshold
OVP detect
tOVPDEL
OVP proprogation delay
VFB delay with 50-mV overdrive
VUVP
Output UVP trip threshold
UVP detect
tUVPDEL
Output UVP proprogation delay
tUVPEN
Output UVP enable delay
From enable to UVP workable
115%
1
µs
65%
70%
75%
0.8
1
1.2
ms
1.8
2.6
3.2
ms
4
4.2
4.33
UVLO
VUVVREG
VREG UVLO threshold
Wake up
Hysteresis
0.25
Shutdown temperature(1)
145
V
THERMAL SHUTDOWN
TSDN
(1)
(2)
6
Thermal shutdown threshold
Hysteresis(1)
10
°C
Ensured by design. Not production tested.
Not production tested. Test condition is VIN= 12 V, VOUT= 1.1 V, IOUT = 10 A using application circuit shown in Figure 8-1.
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700
7
600
6
VDD Shutdown Current (µA)
VDD Supply Current (µA)
6.6 Typical Characteristics
500
400
300
200
VEN = 5V
VVDD = 12 V
VVFB = 0.63 V
No Load
100
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
4
3
2
VEN = 0 V
VVDD = 12 V
No Load
1
0
−40 −25 −10
110 125
Figure 6-1. VDD Supply Current vs. Junction
Temperature
16
140
14
120
12
10
8
6
4
5
20 35 50 65 80
Junction Temperature (°C)
95
100
80
60
40
20
2
OVP
UVP
VVDD = 12 V
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
0
−40 −25 −10
110 125
Figure 6-3. TRIP Pin Current vs. Junction
Temperature
95
110 125
1000
Switching Frequency (kHz)
Switching Frequency (kHz)
5
20 35 50 65 80
Junction Temperature (°C)
Figure 6-4. OVP/UVP Trip Threshold vs. Junction
Temperature
1000
100
FCCM
Skip Mode
10
VIN = 12 V
VOUT = 1.1 V
fSW = 300 kHz
1
0.01
110 125
Figure 6-2. VDD Shutdown Current vs. Junction
Temperature
OVP/UVP Trip Threshold (%)
TRIP Pin Current (µA)
5
0.1
1
Output Current (A)
10
20
100
FCCM
Skip Mode
10
VIN = 12 V
VOUT = 1.1 V
fSW = 500 kHz
1
0.01
G001
Figure 6-5. Switching Frequency vs. Output
Current
0.1
1
Output Current (A)
10
20
G001
Figure 6-6. Switching Frequency vs. Output
Current
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1000
Switching Frequency (kHz)
Switching Frequency (kHz)
1000
100
10
VIN = 12 V
VOUT = 1.1 V
fSW = 750 kHz
FCCM
Skip Mode
1
0.01
0.1
1
Output Current (A)
10
10
VIN = 12 V
VOUT = 1.1 V
fSW = 1 MHz
FCCM
Skip Mode
1
0.01
20
0.1
G001
Figure 6-7. Switching Frequency vs. Output
Current
1
Output Current (A)
900
600
300
1.110
1.105
1.100
1.095
1.090
Skip Mode
FCCM
1.085
0
1
2
3
4
Output Voltage (V)
5
1.080
6
Figure 6-9. Switching Frequency vs. Output
Voltage
2
4
6
8
10
12
14
Output Current (A)
16
18
20
G001
100
fSW = 500 kHz
VIN = 12 V
1.115
90
80
Efficiency (%)
1.110
Output Voltage (V)
0
Figure 6-10. Output Voltage vs. Output Current
1.120
1.105
1.100
1.095
70
60
50
VIN = 12 V
VVDD = 5 V
VOUT = 1.1 V
40
30
1.090
FCCM, IOUT = 0 A
Skip Mode, IOUT = 0 A
FCCM and Skip Mode, IOUT = 20 A
1.085
4
6
8
10
12
Input Voltage (V)
14
16
Figure 6-11. Output Voltage vs. Input Voltage
8
G001
fSW = 500 kHz
VIN = 12 V
VOUT = 1.1 V
1.115
Output Voltage (V)
1200
1.080
20
1.120
fSET = 300 kHz
fSET = 500 kHz
fSET = 750 kHz
fSET = 1 MHz
VIN = 12 V
IOUT = 10 A
0
10
Figure 6-8. Switching Frequency vs. Output
Current
1500
Switching Frequency (kHz)
100
Skip Mode, fSW = 500 kHz
FCCM, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCCM, fSW = 300 kHz
20
10
0
0.01
0.1
1
Output Current (A)
10
20
G001
Figure 6-12. Efficiency vs Output Current
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VIN = 12 V
VIN = 12 V
IOUT = 20 A
EN (5 V/div)
EN (5 V/div)
IOUT = 0 A
VOUT (0.5 V/div)
VOUT (0.5 V/div)
0.5 V pre-biased
VREG(5 V/div)
VREG(5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (1 ms/div)
Time (1 ms/div)
Figure 6-13. Start-Up Waveforms
Figure 6-14. Prebias Start-Up Waveforms
VIN = 12 V
VEN = 5 V
IOUT = 20 A
EN (5 V/div)
VIN (5 V/div)
VDD = VIN
IOUT = 20 A
VOUT (0.5 V/div)
VOUT (0.5 V/div)
VREG(5 V/div)
VREG(5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (20 ms/div)
Time (2 ms/div)
Figure 6-15. Shutdown Waveforms
Figure 6-16. UVLO Start-Up Waveforms
Skip Mode
VIN = 12 V
IOUT = 0 A
FCCM
VIN = 12 V
IOUT = 0 A
VOUT (20 mV/div)
VOUT (20 mV/div)
LL (5 V/div)
LL (5 V/div)
IL (5 A/div)
IL (5 A/div)
Time (2 ms/div)
Time (1 ms/div)
Figure 6-17. 1.1-V Output FCCM Mode Steady-State
Operation
Figure 6-18. 1.1-V Output Skip Mode Steady-State
Operation
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Skip Mode
VIN = 12 V
VOUT = 1.1 V
Skip Mode
VIN = 12 V
VOUT = 1.1 V
VOUT (20 mV/div)
VOUT (20 mV/div)
LL (5 V/div)
LL (5 V/div)
IL (5 A/div)
IL (5 A/div)
Time (200 ms/div)
Time (200 ms/div)
Figure 6-19. CCM-to-DCM Transition Waveforms
Figure 6-20. DCM-to-CCM Transition Waveforms
FCCM
VIN = 12 V, VOUT = 1.1 V
Skip Mode
VIN = 12 V, VOUT = 1.1 V
IOUT from 0 A to 10 A, 2.5 A/ms
IOUT from 0 A to 10 A, 2.5 A/ms
VOUT (20 mV/div)
VOUT (20 mV/div)
IOUT (5 A/div)
IOUT (5 A/div)
Time (100 ms/div)
Time (100 ms/div)
Figure 6-21. FCCM Load Transient
IOUT from 20 A to 25 A
VOUT (1 V/div)
Figure 6-22. Skip Mode Load Transeint
VOUT (1 V/div)
IOUT 2 A then Short Output
VIN = 12 V
VIN = 12 V
LL (10 V/div)
LL (10 V/div)
IL (10 A/div)
IL (10 A/div)
IOUT (25 A/div)
PGOOD (5 V/div)
10
Time (10 ms/div)
Time (10 ms/div)
Figure 6-23. Overcurrent Protection Waveforms
Figure 6-24. Output Short-Circuit Protection
Waveforms
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90
Ambient Temperature (°C)
EN (5 V/div)
VOUT (1 V/div)
VIN = 12 V
IOUT = 20 A
80
70
60
50
40
30
PGOOD (5 V/div)
All Levels of Air Flow
20
Time (1 s/div)
0
2
4
6
8
10
12
14
Output Current (A)
VIN = 12 V
VOUT = 1.2 V
fSW = 500 kHz
16
18
20
G000
Figure 6-26. Safe Operating Area
Figure 6-25. Overtemperature Protection
Waveforms
Ambient Temperature (°C)
90
80
70
60
50
40
400 LFM
200 LFM
100 LFM
Natural Convection
30
20
0
2
4
6
8
10
12
14
Output Current (A)
VIN = 12 V
VOUT = 5 V
fSW = 500 kHz
16
18
20
G000
Figure 6-27. Safe Operating Area
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100
100
95
95
90
90
85
80
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
75
70
0
2
4
6
8
10
12
14
Output Current (A)
Efficiency (%)
Efficiency (%)
For VOUT = 5 V, an SC5026-1R0 inductor is used. For 1 ≤ VOUT ≤ 3.3 V, a PA0513.441 inductor is used
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
16
18
95
90
90
70
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
0
2
4
6
Efficiency (%)
Efficiency (%)
95
80
8
10
12
14
Output Current (A)
16
18
70
20
90
90
Efficiency (%)
95
85
0
2
4
6
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
8
10
12
14
Output Current (A)
16
18
16
18
20
G000
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
0
2
4
6
8
10
12
14
Output Current (A)
16
18
20
G000
85
Skip Mode
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
75
20
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
80
70
0
G001
Figure 6-32. Efficiency vs Output Current
8
10
12
14
Output Current (A)
Figure 6-31. Efficiency vs Output Current
95
70
6
G000
100
75
4
80
100
FCCM
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
2
85
75
Figure 6-30. Efficiency vs Output Current
80
0
Figure 6-29. Efficiency vs Output Current
100
85
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
G001
100
75
Efficiency (%)
70
20
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
80
75
Figure 6-28. Efficiency vs Output Current
12
85
2
4
6
8
10
12
14
Output Current (A)
16
18
20
G001
Figure 6-33. Efficiency vs Output Current
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7 Detailed Description
7.1 Overview
The TPS53353 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage
point-of-load applications in computing and similar digital consumer applications. The device features proprietary
D-CAP™ mode control combined with an adaptive on-time architecture. This combination is ideal for building
modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6
V to 5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from
4.5 V to 25 V. The D-CAP™ mode uses the equivalent series resistance (ESR) of the output capacitor(s) to
sense the device current . One advantage of this control scheme is that it does not require an external phase
compensation network. This allows a simple design with a low external component count. Eight preset switching
frequency values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive
on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing
the switching frequency to increase at the step-up of the load.
The TPS53353 has a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms as shown in Table 7-3.
7.2 Functional Block Diagram
0.6 V +10/15%
0.6 V –30%
+
UV
PGOOD
+
Delay
Delay
+
0.6 V –5/10%
Ramp
Compensation
Control Logic
+
+20%
+
VFB
VREG
0.6 V
SS
OV
UVP/OVP
Logic
RF
VBST
+
+ PWM
VIN
10 mA
GND
TRIP
tON
OneShot
+
+ OCP
LL
LL
XCON
+
GND
ZC
Control
Logic
SS
FCCM/
Skip
Decode
MODE
EN
·
·
·
·
·
+
1.2 V/0.95 V
GND
On/Off time
Minimum On /Off
Light load
OVP/UVP
FCCM/Skip
VDDOK
LL
Fault
Shutdown
+
TPS53353
LDO
VDD
4.2 V/
3.95 V
Enable
THOK
VREG
+
EN
145°C/
135°C
UDG-11048
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Note
The thresholds in this block diagram are typical values. Refer to the Section 6.5 table for threshold
limits.
7.3 Feature Description
7.3.1 5-V LDO and VREG Start-Up
TPS53353 provides an internal 5V LDO function using input from VDD and output to VREG. The 5V LDO is
gated by the EN pin. The LDO starts-up when EN is approximately 1.8V and VDD is approximately 2V. (See
Figure 7-1) The LDO outputs its voltage to the VREG pin. The VREG voltage provides the bias voltage for the
internal analog circuitry and also provides the supply voltage for the gate drives.
Figure 7-1. Power Up Sequence
7.3.2 Adaptive On-Time D-CAP™ Control and Frequency Selection
The TPS53353 does not have a dedicated oscillator to determine switching frequency. However, the device
operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time
one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage
and proportional to the output voltage (tON ∝ VOUT/VIN).
This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 7-1. (Maintaining open resistance sets the
switching frequency to 500 kHz.)
Table 7-1. Resistor and Switching Frequency
RESISTOR (RRF)
CONNECTIONS
14
VALUE (kΩ)
CONNECT TO
SWITCHING
FREQUENCY
(fSW)
(kHz)
0
GND
250
187
GND
300
619
GND
400
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Table 7-1. Resistor and Switching Frequency
(continued)
RESISTOR (RRF)
CONNECTIONS
CONNECT TO
SWITCHING
FREQUENCY
(fSW)
(kHz)
OPEN
n/a
500
866
VREG
650
309
VREG
750
124
VREG
850
0
VREG
970
VALUE (kΩ)
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts a set signal to terminate the off time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time
is extended until the current level falls below the threshold.
Figure 7-2 and Figure 7-3 show two on-time control schemes.
VFB
VFB
VREF
VREF
tON
Compensation
Ramp
PWM
PWM
tON
tOFF
UDG-10208
Figure 7-2. On-Time Control Without Ramp
Compensation
tOFF
UDG-10209
Figure 7-3. On-Time Control With Ramp
Compensation
7.3.3 Ramp Signal
The TPS53353 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in
the previous section, the feedback voltage is compared with the reference information to keep the output voltage
in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in
steady state.
During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than
the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the
ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset.
7.3.4 Adaptive Zero Crossing
The TPS53353 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too
early detection. As a result, better light load efficiency is delivered.
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7.3.5 Power-Good
The TPS53353 has power-good output that indicates high when switcher output is within the target. The powergood function is activated after soft-start has finished. If the output voltage becomes within +10% and –5% of
the target value, internal comparators detect power-good state and the power-good signal becomes high after
a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good
signal becomes low after two microsecond (2-μs) internal delay. The power-good output is an open drain output
and must be pulled up externally.
The power-good MOSFET is powered through the VDD pin. VVDD must be >1 V in order to have a valid
power-good logic. It is recommended to pull PGOOD up to VREG (or a voltage divided from VREG) so that the
power-good logic is still valid even without VDD supply.
7.3.6 Current Sense, Overcurrent and Short Circuit Protection
TPS53353 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period in that the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53353 supports
temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the
trip voltage setting resistor, RTRIP. The TRIP terminal sources current (ITRIP) which is 10 μA typically at room
temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 1.
VTRIP (mV ) = RTRIP (kW )´ ITRIP (mA )
(1)
The inductor current is monitored by the LL pin. The GND pin is used as the positive current sensing node and
the LL pin is used as the negative current sense node. The trip current, ITRIP has 4700ppm/°C temperature slope
to compensate the temperature dependency of the RDS(on).
As the comparison is made during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the
load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 2.
IOCP =
VTRIP
(32 ´ RDS(on) )
+
IIND(ripple)
2
=
VTRIP
(32 ´ RDS(on) )
+
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
(2)
In an overcurrent or short circuit condition, the current to the load exceeds the current to the output capacitor
thus the output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts
down. After a hiccup delay (16 ms with 0.7 ms sort-start), the controller restarts. If the overcurrent condition
remains, the procedure is repeated and the device enters hiccup mode.
Hiccup time calculation:
tHIC(wait) = (2n + 257) × 4 μs
(3)
where
•
N = 8, 9, 10, or 11 depending on soft start time selection
tHIC(dly) = 7 × (2n + 257) × 4 μs
(4)
Table 7-2. Hiccup Time Calculation
SELECTED SOFT-START TIME
(tSS) (ms)
n
HICCUP WAIT TIME (tHIC(wait)) (ms)
HICCUP DELAY TIME (tHIC(dly)) (ms)
0.7
8
2.052
14.364
1.4
9
3.076
21.532
2.8
10
5.124
35.868
5.6
11
9.22
64.54
16
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7.3.7 Overvoltage and Undervoltage Protection
TPS53353 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal
UVP delay counter begins counting. After 1ms, TPS53353 latches OFF both high-side and low-side MOSFETs
drivers. The controller restarts after a hiccup delay (16 ms with 0.7 ms soft-start). This function is enabled 1.5-ms
after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver.
The output voltage decreases. If the output voltage reaches UV threshold, then both high-side MOSFET and
low-side MOSFET driver will be OFF and the device restarts after a hiccup delay. If the OV condition remains,
both high-side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed.
7.3.8 UVLO Protection
The TPS53353 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than 3.95
V, the device shuts off. When the VREG voltage is higher than 4.2V, the device restarts. This is a non-latch
protection.
7.3.9 Thermal Shutdown
TPS53353 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 145°C),
TPS53353 is shut off. When the temperature falls about 10°C below the threshold value, the device will turn
back on. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure
7-4.
TPS53353
Switching Modulator
VIN
VIN
R1
VFB
PWM
1
R2
+
+
Control
Logic
and
Divider
LL
L
VOUT
IIND
IC
IOUT
0.6 V
ESR
R LOAD
Voltage
Divider
VC
COUT
Output
Capacitor
UDG-11193
Copyright © 2016, Texas Instruments Incorporated
Figure 7-4. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
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H (s ) =
1
s ´ ESR ´ COUT
(5)
For loop stability, the 0-dB frequency, ƒ0, defined in Equation 6 needs to be lower than 1/4 of the switching
frequency.
f0 =
f
1
£ SW
2p ´ ESR ´ COUT
4
(6)
According to Equation 6, the loop stability of D-CAPTM mode modulator is mainly determined by the capacitor's
chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance in the order of
several 100 µF and ESR in range of 10 mΩ. These makes ƒ0 on the order of 100 kHz or less, creating a stable
loop. However, ceramic capacitors have an ƒ0 at more than 700 kHz, and need special care when used with this
modulator. An application circuit for ceramic capacitor is described in Section 8.2.2.2.2.
7.4.2 Enable, Soft Start, and Mode Selection
When the EN pin voltage rises above the enable threshold voltage (typically 1.2 V), the controller enters its
start-up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The
controller then uses the first 250 μs to calibrate the switching frequency setting resistance attached to the RF
pin and stores the switching frequency code in internal registers. During this period, the MODE pin also senses
the resistance attached to this pin and determines the soft-start time. Switching is inhibited during this phase.
In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on
the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
Table 7-3. Soft-Start and MODE Settings
MODE SELECTION
Auto-skip
Forced CCM(1)
(1)
ACTION
SOFT-START TIME (ms)
RMODE (kΩ)
0.7
39
1.4
100
2.8
200
Pulldown to GND
Connect to PGOOD
5.6
475
0.7
39
1.4
100
2.8
200
5.6
475
Device enters FCCM after the PGOOD pin goes high when MODE is connected to PGOOD through
the resistor RMODE.
After soft-start begins, the MODE pin becomes the input of an internal comparator which determines auto-skip or
FCCM mode operation. If MODE voltage is higher than 1.3 V, the converter enters into FCCM mode. Otherwise
it will be in auto-skip mode at light load condition. Typically, when FCCM mode is selected, the MODE pin is
connected to PGOOD through the RMODE resistor, so that before PGOOD goes high the converter remains in
auto-skip mode.
7.4.3 Auto-Skip Eco-mode™ Light Load Operation
While the MODE pin is pulled low via RMODE, TPS53353 automatically reduces the switching frequency at light
load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As
the load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time
is kept almost the same as it was in the continuous conduction mode so that it takes longer to discharge
the output capacitor with smaller load current to the level of the reference voltage. The transition point to the
18
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light-load operation IOUT(LL) (that is, the threshold between continuous and discontinuous conduction mode) can
be calculated as shown in Equation 7.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
(7)
where
•
ƒSW is the PWM switching frequency
Switching frequency versus output current in the light load condition is a function of L, VIN, and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 7. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
7.4.4 Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load
range which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS53353 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage
point-of-load applications in computing and similar digital consumer applications. The device features proprietary
D-CAP mode control combined with an adaptive on-time architecture. This combination is ideal for building
modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V
to 5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from 4.5 V
to 25 V. The D-CAP mode uses the equivalent series resistance (ESR) of the output capacitor(s) to sense the
device current. One advantage of this control scheme is that it does not require an external phase compensation
network. This allows a simple design with a low external component count. Eight preset switching frequency
values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive on-time control
tracks the preset switching frequency over a wide input and output voltage range while allowing the switching
frequency to increase at the step-up of the load.
8.2 Typical Applications
8.2.1 Typical Application Circuit Diagram
C3
1 mF
C4
4.7 mF
R4
NI
R6
200 kW
R8
110 kW
VVDD
4.5 V to 25 V
22
21
20
19
18
RF
TRIP
MODE
VDD
17
VREG VIN
C IN
22 mF
16
15
14
13
12
VIN
VIN
VIN
VIN
VIN
TPS53353
C IN
22 mF
C IN
22 mF
C IN
22 mF
GND
VOUT
L1
0.44 mH
PA 0513.441
VREG
R10
100 kW
VFB
EN
PGOOD
VBST
N/C
LL
LL
LL
LL
LL
LL
1
2
3
4
5
6
7
8
9
10
11
R11
NI
R9
2W
PGOOD
EN
R2
10 kW
VIN 8 V
to
14 V
C6
NI
C5
0.1 mF
C OUT
330 mF
C OUT
330 mF
15 kW
UDG-11049
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Typical Application Circuit Diagram
20
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8.2.1.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
12
14
V
INPUT CHARACTERISTICS
VIN
Voltage range
IMAX
Maximum Input current
VIN = 8 V, IOUT = 20 A
No load input current
VIN = 14 V, IOUT = 0 A with auto-skip mode
4.1
A
1
mA
1.5
V
OUTPUT CHARACTERISTICS
Output voltage
VOUT
Line regulation, 8 V ≤ VIN ≤ 15 V
0.1%
Output voltage regulation
Load regulation, VIN = 12 V, 0 A ≤ IOUT ≤ 20 A
with FCCM
0.2%
VIN = 12 V, IOUT = 20 A with FCCM
VRIPPLE
Output voltage ripple
ILOAD
Output load current
20
IOCP
Output overcurrent
threshold
26
A
tSS
Soft-start time
1.4
ms
500
kHz
0
mVPP
20
A
SYSTEMS CHARACTERISTICS
fSW
Switching frequency
η
TA
Peak efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A
91.87%
Full load efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 20 A
91.38%
Operating temperature
25
°C
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External Component Selection
Refer to Section 8.2.2.2.2 for guidelines for this design with all ceramic output capacitors.
The external components selection is a simple process when using organic semiconductors or special polymer
output capacitors.
1. SELECT OPERATION MODE AND SOFT-START TIME
Select operation mode and soft-start time using Table 7-3.
2. SELECT SWITCHING FREQUENCY
Select the switching frequency from 250 kHz to 1 MHz using Table 7-1.
3. CHOOSE THE INDUCTOR
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of
maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise
ratio and helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to
maximum output current ratio, the inductance can be determined by Equation 8.
L=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
VIN(max )
OUT
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max)
(8)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 9.
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IIND(peak ) =
VTRIP
1
+
´
32 ´ RDS(on ) L ´ fSW
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(9)
4. CHOOSE THE OUTPUT CAPACITORS
When organic semiconductor capacitors or specialty polymer capacitors are used, for loop stability,
capacitance and ESR should satisfy Equation 6. For jitter performance, Equation 10 is a good starting
point to determine ESR.
ESR =
VOUT ´ 10mV ´ (1 - D) 10mV ´ L ´ fSW L ´ fSW
=
=
(W )
0.6 V ´ IIND(ripple )
0.6 V
60
(10)
where
•
•
D is the duty factor.
The required output ripple slope is approximately 10 mV per tSW (switching period) in terms of VFB
terminal voltage.
5. DETERMINE THE VALUE OF R1 AND R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 7-4. R1
is connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 11.
VOUT R1 =
IIND(ripple ) ´ ESR
2
0.6
- 0.6
´ R2
(11)
6. CHOOSE THE OVERCURRENT SETTING RESISTOR
The overcurrent setting resistor, RTRIP, can be determined by Equation 12 .
æ
æ
ö (VIN - VOUT )´ VOUT
1
çç IOCP - ç
÷´
VIN
è 2 ´ L ´ fSW ø
è
RTRIP (kW) =
ITRIP (mA)
ö
÷÷ ´ 32 ´ RDS(on) (mW )
ø
(12)
where
•
•
ITRIP is the TRIP pin sourcing current (10 µA).
RDS(on) is the thermally compensated on-time resistance value of the low-side MOSFET.
Use an RDS(on) value of 1.6 mΩ for an overcurrent level of approximately 20 A. Use an RDS(on) value of
1.7 mΩ for overcurrent level of approximately 10 A.
22
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8.2.1.3 Application Curves
Figure 8-2. Enable Turnon
Figure 8-3. Enable Turnoff
8.2.2 Typical Application Circuit Diagram With Ceramic Output Capacitors
C4
4.7 mF
R4
NI
C3
1 mF
R6
200 kW
R8
110 kW
VVDD
4.5 V to 25 V
22
21
20
19
RF
TRIP
MODE
VDD
18
17
VREG VIN
16
15
14
13
12
VIN
VIN
VIN
VIN
VIN
TPS53353
C IN
22 mF
C IN
22 mF
C IN
22 mF
VIN 8 V
to
14 V
C IN
22 mF
VOUT
L1
0.44 mH
PA 0513.441
GND
VREG
R10
100 kW
VFB
EN
PGOOD
VBST
N/C
LL
LL
LL
LL
LL
LL
1
2
3
4
5
6
7
8
9
10
11
R9
2W
PGOOD
EN
R2
10 kW
R7
3.01 kW
C1
0.1 mF
C OUT
4 x 100 mF
Ceramic
R11
NI
C5
0.1 mF
C6
NI
C2
1 nF
R1 14.7kW
UDG-11050
Figure 8-4. Typical Application Circuit Diagram With Ceramic Output Capacitors
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8.2.2.1 Design Requirements
Table 8-2. Design Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
12
14
V
INPUT CHARACTERISTICS
VIN
Voltage range
IMAX
Maximum Input current
VIN = 8 V, IOUT = 20 A
No load input current
VIN = 14 V, IOUT = 0 A with auto-skip mode
4.1
A
1
mA
1.5
V
OUTPUT CHARACTERISTICS
Output voltage
VOUT
Line regulation, 8 V ≤ VIN ≤ 15 V
0.1%
Output voltage regulation
Load regulation, VIN = 12 V, 0 A ≤ IOUT ≤ 20 A
with FCCM
0.2%
VIN = 12 V, IOUT = 20 A with FCCM
VRIPPLE
Output voltage ripple
ILOAD
Output load current
20
IOCP
Output overcurrent
threshold
26
A
tSS
Soft-start time
1.4
ms
500
kHz
0
mVPP
20
A
SYSTEMS CHARACTERISTICS
fSW
Switching frequency
η
TA
Peak efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A
91.87%
Full load efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 20 A
91.38%
Operating temperature
25
°C
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 External Component Selection
Refer to Section 8.2.2.2.2 for guidelines for this design with all ceramic output capacitors.
The external components selection is a simple process when using organic semiconductors or special polymer
output capacitors.
1. Select Operation Mode and Soft-Start Time
Select operation mode and soft-start time using Table 7-3.
2. Select Switching Frequency
Select the switching frequency from 250 kHz to 1 MHz using Table 7-1.
3. Choose The Inductor
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of
maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise
ratio and helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to
maximum output current ratio, the inductance can be determined by Equation 8.
L=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
VIN(max )
OUT
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max)
(13)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 9.
24
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IIND(peak ) =
SLUSAK2D – AUGUST 2011 – REVISED APRIL 2021
VTRIP
1
+
´
32 ´ RDS(on ) L ´ fSW
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(14)
4. External Component Selection with All Ceramic Output Capacitors
Refer to Section 8.2.2.2.2 to select external components because ceramic output capacitors are used in this
design.
5. Choose the Overcurrent Setting Resistor
The overcurrent setting resistor, RTRIP, can be determined by Equation 15.
æ
æ
ö (VIN - VOUT )´ VOUT
1
çç IOCP - ç
÷´
VIN
è 2 ´ L ´ fSW ø
è
RTRIP (kW) =
ITRIP (mA)
ö
÷÷ ´ 32 ´ RDS(on) (mW )
ø
(15)
where
•
•
ITRIP is the TRIP pin sourcing current (10 µA).
RDS(on) is the thermally compensated on-time resistance value of the low-side MOSFET.
Use an RDS(on) value of 1.6 mΩ for an overcurrent level of approximately 20 A. Use an RDS(on) value of
1.7 mΩ for overcurrent level of approximately 10 A.
6. BST Resistor Selection
The recommended BST resistor value is 2 Ω and anything larger than 5.1 Ω is not recommended. Note
that when the gate drive turns on, the voltage on the boot-strap capacitor splits between the internal pull-up
resistance and the boot-strap resistance, with the internal circuits only seeing the portion across the internal
pull-up resistance. Therefore, when the external resistor gets larger than the pull-up resistance, it crashes
the head-room of the SW to BOOT logic, which can cause logic issues with the high-side gate driver.
8.2.2.2.2 External Component Selection Using All Ceramic Output Capacitors
When a ceramic output capacitor is used, the stability criteria in Equation 6 cannot be satisfied. The ripple
injection approach as shown in Figure 8-4 is implemented to increase the ripple on the VFB pin and make the
system stable. In addition to the selections made using Steps 1 through Step 5 in Section 8.2.2.2.1, the ripple
injection components must be selected. The C2 value can be fixed at 1 nF. The value of C1 can be selected from
10 nF to 200 nF.
L ´ COUT
t
> N ´ ON
R7 ´ C1
2
(16)
where
•
N is the coefficient to account for L and COUT variation.
N is also used to provide enough margin for stability. It is recommended N = 2 for VOUT ≤ 1.8 V and N = 4
for VOUT ≥ 3.3 V or when L ≤ 250 nH. The higher VOUT needs a higher N value because the effective output
capacitance is reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor may
have only 8 µF of effective capacitance when biased at 5 V.
Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase
of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node
and the other coupled from the VOUT pin and they can be calculated using Equation 17 and Equation 18 when
neglecting the output voltage ripple caused by equivalent series inductance (ESL).
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V - VOUT
D
´
VINJ _ SW = IN
R7 ´ C1
fSW
VINJ _ OUT = ESR ´ IIND(ripple ) +
(17)
IIND(ripple )
8 ´ COUT ´ fSW
(18)
It is recommended that VINJ_SW to be less than 50 mV and VINJ_TOTAL to be less than 60mV. If the calculated
VINJ_SW is higher than 50 mV, then other parameters must be adjusted to reduce it. For example, COUT can be
increased to satisfy Equation 16 with a higher R7 value, thereby reducing VINJ_SW. Use Equation 19 to calculate
COUT capacitance needed. For a more holistic calculation, please reference the TPS53353 calculator on ti.com
COUT
VIN MAX
VOUT
2 u L u VINJ MAX
u N u t ON
(19)
The DC voltage at the VFB pin can be calculated by Equation 20:
VVFB = 0.6 +
VINJ _ SW + VINJ _ OUT
2
(20)
And the resistor divider value can be determined by Equation 21:
- VVFB
V
´ R2
R1 = OUT
VVFB
26
(21)
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8.2.2.3 Application Curves
Figure 8-5. Enable Turnon
Figure 8-6. Enable Turnoff
Figure 8-7. Output Transient from DCM to CCM
Figure 8-8. Output Transient from DCM to DCM
Figure 8-9. Output Transient with FCCM Mode
Figure 8-10. Output 0.75-V Prebias Turnon
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Figure 8-11. Output Overcurrent Protection
28
Figure 8-12. Output Short-Circuit Protection
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 1.5 V to 22 V (4.5 V to 25 V biased).
This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is also
critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in Section 10.
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10 Layout
10.1 Layout Guidelines
Certain points must be considered before starting a layout work using the TPS53353.
•
•
•
•
•
•
•
•
•
30
The power components (including input/output capacitors, inductor and TPS53353) should be placed on one
side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, in order to
shield and isolate the small signal traces from noisy power lines.
All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
Because the TPS53353 controls output voltage referring to voltage across VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND of
the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors to
the VFB pin should be short and thin.
Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as
close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
Place the VDD and VREG decoupling capacitors as close to the device as possible. Ensure to provide GND
vias for each decoupling capacitor and make the loop as small as possible.
The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 8-4) from the terminal of
ceramic output capacitor. The AC coupling capacitor (C2 in Figure 8-4) should be placed near the device, and
R7 and C1 can be placed near the power stage.
Use separated vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor.
Do not combine these connections.
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10.2 Layout Example
Figure 10-1. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
Eco-mode™, NexFET™, and PowerPAD™ are trademarks of TI.
SWIFT™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53353DQPR
ACTIVE
LSON-CLIP
DQP
22
2500
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
53353DQP
TPS53353DQPT
ACTIVE
LSON-CLIP
DQP
22
250
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
53353DQP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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