TPS53355
SLUSAE5G – AUGUST 2011 – REVISEDTPS53355
APRIL 2021
SLUSAE5G – AUGUST 2011 – REVISED APRIL 2021
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TPS53355 1.5-V to 15-V Input (4.5-V to 25-V bias), 30-A Synch Step-down SWIFT™
Converter with Eco-mode™
1 Features
2 Applications
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Alternative product available: LMZ31530 14.5-V,
30-A step-down power module in 15 × 16 × 5.8mm QFN package
96% maximum efficiency
Conversion input voltage range: 1.5 V to 15 V
VDD input voltage range: 4.5 V to 25 V
Output voltage range: 0.6 V to 5.5 V
5-V LDO output
Supports single rail input
Integrated power MOSFETs with 30 A of
continuous output current
Auto-skip Eco-mode™ for light-load efficiency
< 10-μA shutdown current
D-CAP™ mode with fast transient response
Selectable switching frequency from 250 kHz to
1 MHz with external resistor
Selectable auto-skip or PWM-only operation
Built-in 1% 0.6-V reference
0.7-ms, 1.4-ms, 2.8-ms, and 5.6-ms selectable
internal voltage servo soft start
Integrated boost switch
Precharged start-up capability
Adjustable overcurrent limit with thermal
compensation
Overvoltage, undervoltage, UVLO and
overtemperature protection
Supports all ceramic output capacitors
Open-drain power-good indication
Incorporates NexFET™ power block technology
22-pin QFN package With PowerPAD™
For SWIFT™ power products documentation, see
http://www.ti.com/swift
Green (RoHS compatible) is optional
Create a custom design using the TPS53355 with
the WEBENCH® Power Designer
Enterprise servers and storage
Wired networking switches and routers
ASIC, SoC, FPGA, DSP core, and I/O voltage
3 Description
The TPS53355 is a D-CAP™ mode, 30-A
synchronous switcher with integrated MOSFETs. It is
designed for ease of use, low external component
count, and space-conscious power systems.
This device features 5-mΩ/2-mΩ integrated
MOSFETs, accurate 1% 0.6-V reference, and
integrated boost switch. A sample of competitive
features include: 1.5-V to 15-V wide conversion input
voltage range, very low external component count, DCAP™ mode control for super fast transient, auto-skip
mode operation, internal soft-start control, selectable
frequency, and no need for compensation.
The conversion input voltage ranges from 1.5 V to 15
V, the supply voltage range is from 4.5 V to 25 V, and
the output voltage range is from 0.6 V to 5.5 V.
The device is available in 6-mm × 5-mm, 22-pin QFN
package.
The LMZ31530 integrates the TPS53355, an inductor,
and other passive components into a small, easy-touse module.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS53355
LSON-CLIP (22)
6.00 mm × 5.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VVDD
21
20
19
18
17
16
15
14
13
RF
MODE
VDD
VREG
VIN
VIN
VIN
VIN
VIN
EN
PGOOD
VBST
N/C
LL
LL
LL
LL
LL
LL
GND
VFB
TPS53355
12
VIN
22
TRIP
VIN
1
2
3
4
5
6
7
8
9
10
11
VREG
VOUT
PGOOD
EN
Copyright © 2016, Texas Instruments Incorporated
Typical Application
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLUSAE5G – AUGUST 2011 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings(1) .................................... 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Infomation..................................................... 5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 8
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................31
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 33
11 Device and Documentation Support..........................34
11.1 Device Support........................................................34
11.2 Receiving Notification of Documentation Updates.. 34
11.3 Support Resources................................................. 34
11.4 Trademarks............................................................. 34
11.5 Electrostatic Discharge Caution.............................. 34
11.6 Glossary.................................................................. 34
12 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (June 2019) to Revision G (April 2021)
Page
• Added LMZ31530 information to Section 1 as a module version of the TPS53355........................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Updated Section 2 ............................................................................................................................................. 1
• Added LMZ31530 information to Section 3 as a module version of the TPS53355........................................... 1
• Added BST Resistor Selection to Section 8.2.1.2.2 ........................................................................................ 24
• Added Equation 14 and supporting information................................................................................................25
• MODE and RF pins updated in Figure 10-1 .................................................................................................... 33
Changes from Revision E (March 2019) to Revision F (June 2019)
Page
• Removed -40°C to +85°C temperature range from Description......................................................................... 1
• Removed -40°C to +85°C temperature range from Absolute Maximum Ratings............................................... 5
Changes from Revision D (November 2016) to Revision E (March 2019)
Page
• Added links for WEBENCH ................................................................................................................................1
• Deleted "Operating free-air temperature, TA" row ............................................................................................. 5
Changes from Revision C (February 2016) to Revision D (November 2016)
Page
• Added Feature: Green (RoHS Compatible), is Optional ....................................................................................1
• Added the VQP package to the Section 6.4 ...................................................................................................... 5
• From: a SC5026-1R0 inductor is used. To: a 744355182 inductor is used........................................................ 8
• Changed Figure 6-32 and Figure 6-33 .............................................................................................................. 8
• Section 7.3.1, Changed the NOTE From: "The 5-V LDO is not controlled" To: "The 5-V LDO is controlled"... 16
• Changed 250 µs To ~550 µs in Figure 7-1 ...................................................................................................... 16
Changes from Revision B (January 2014) to Revision C (February 2016)
Page
• Changed the datasheet Title From: "TPS53355 High-Efficiency 30-A Synchronous Buck Converter With Ecomode™" To: "TPS53355 High-Efficiency 30-A Synchronous Buck SWIFT™ Converter With Eco-mode™"..... 1
• Added Section 1: "For SWIFT™ Power Products Documentation,..."................................................................ 1
2
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Changes from Revision A (September 2012) to Revision B (January 2014)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision * (August 2011) to Revision A (September 2012)
Page
• Changed conversion input voltage from "3 V" to "1.5 V" ................................................................................... 1
• Changed VIN input voltage range minimum from "3 V" to "1.5 V"...................................................................... 4
• Changed typographical error in THERMAL INFORMATION table......................................................................5
• Changed VIN (main supply) input voltage range minimum from "3 V' to "1.5 V" in Section 6.3 ........................ 5
• Changed VIN pin power conversion input minimum voltage from "3 V" to "1.5 V" in ELECTRICAL
CHARACTERISTICS table................................................................................................................................. 6
• Changed conversion input voltage range from "3 V" to "1.5" in Section 7.1 ....................................................14
• Added note to the Section 7.2 ......................................................................................................................... 14
• Changed "ripple injection capacitor" to "ripple injection resistor" in Section 10.1 section.................................32
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5 Pin Configuration and Functions
A.
VFB
1
22
RF
EN
2
21
TRIP
PGOOD
3
20
MODE
VBST
4
19
VDD
N/C
5
18
VREG
LL
6
17
VIN
LL
7
16
VIN
LL
8
15
VIN
LL
9
14
VIN
LL
10
13
VIN
LL
11
12
VIN
GND
PowerPad
TM
N/C = no connection
Figure 5-1. Package With PowerPad 22-Pins (LSON-CLIP) Top View
Table 5-1. Pin Functions
PIN
NAME
NO
I/O/P(1)
DESCRIPTION
EN
2
I
Enable pin. Typical turn-on threshold voltage is 1.2 V. Typical turn-off threshold is 0.95 V.
GND
—
—
Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
B
Output of converted power. Connect this pin to the output Inductor.
I
Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 7-3. The softstart time is detected and stored into internal register during start-up.
6
7
8
LL
9
10
11
MODE
20
N/C
5
PGOOD
3
O
Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB
goes out of the specified limits PGOOD goes low after a 2-µs delay.
RF
22
I
Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using
Table 7-1. The switching frequency is detected and stored during the startup.
TRIP
21
I
No connect.
OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 4700 ppm/°C current is sourced
and set the OCL trip voltage as follows:
space VOCL = VTRIP/32
(VTRIP ≤ 2.4 V, VOCL ≤ 75 mV)
VBST
4
P
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node.
Internally connected to VREG via bootstrap MOSFET switch.
VDD
19
P
Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.
1
I
Output feedback input. Connect this pin to Vout through a resistor divider.
P
Conversion power input. VIN input voltage range is from 1.5 V to 15 V.
P
5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry.
VFB
12
13
14
VIN
15
16
17
VREG
(1)
4
18
I=Input, O=Output, B=Bidirectional, P=Supply
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6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
MAX
–0.3
25
VDD
–0.3
28
VBST
–0.3
32
VBST (with respect to LL)
–0.3
7
EN, TRIP, VFB, RF, MODE
–0.3
7
DC
–2
25
Pulse < 20 ns, E = 5 μJ
–7
27
PGOOD, VREG
–0.3
7
GND
–0.3
0.3
VIN (main supply)
Input voltage
LL
Output voltage
Source/sink current
VBST
50
Junction temperature, TJ
V
150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
V
mA
–40
Storage temperature, Tstg
UNIT
–55
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage range
Output voltage range
MIN
MAX
VIN (main supply)
1.5
15
VDD
4.5
25
VBST
4.5
28
VBST (with respect to LL)
4.5
6.5
EN, TRIP, VFB, RF, MODE
–0.1
6.5
–1
22
–0.1
6.5
–40
125
LL
PGOOD, VREG
Junction temperature range, TJ
UNIT
V
V
°C
6.4 Thermal Infomation
TPS53355
THERMAL METRIC(1)
DQP
VQP
UNIT
22 PINS
22 PINS
θJA
Junction-to-ambient thermal resistance
27.2
27.2
°C/W
θJCtop
Junction-to-case (top) thermal resistance
17.1
17.1
°C/W
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TPS53355
THERMAL METRIC(1)
DQP
VQP
UNIT
22 PINS
22 PINS
θJB
Junction-to-board thermal resistance
5.9
5.9
°C/W
ψJT
Junction-to-top characterization parameter
0.8
0.8
°C/W
ψJB
Junction-to-board characterization parameter
5.8
5.8
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
1.2
1.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VVIN
VIN pin power conversion input
voltage
1.5
15
V
VVDD
Supply input voltage
4.5
25
V
IVIN(leak)
VIN pin leakage current
VEN = 0 V
1
µA
IVDD
VDD supply current
TA = 25°C, No load, VEN = 5 V,
VVFB = 0.630 V
590
µA
IVDDSDN
VDD shutdown current
TA = 25°C, No load, VEN = 0 V
10
µA
420
INTERNAL REFERENCE VOLTAGE
CCM condition(1)
VVFB
VFB regulation voltage
VVFB
VFB regulation voltage
0°C ≤ TA ≤ 85°C
IVFB
VFB input current
VVFB = 0.630 V, TA = 25°C
TA = 25°C
–40°C ≤ TA ≤ 85°C
0.6
V
0.597
0.6
0.603
0.5952
0.6
0.6048
0.594
V
0.6
0.606
0.01
0.20
µA
5
5.36
V
LDO OUTPUT
VVREG
LDO output voltage
current(1)
IVREG
LDO output
VDO
Low drop out voltage
0 mA ≤ IVREG ≤ 30 mA
4.77
Maximum current allowed from LDO
30
mA
230
mV
0.1
0.2
V
0.01
1.50
µA
260
400
ns
VVDD = 4.5 V, IVREG = 30 mA
BOOT-STRAP SWITCH
VFBST
Forward voltage
VVREG-VBST, IF = 10 mA, TA = 25°C
IVBSTLK
VBST leakage current
VVBST = 23 V, VSW = 17 V, TA = 25°C
DUTY AND FREQUENCY CONTROL
tOFF(min)
tON(min)
Minimum off time
TA = 25°C
Minimum on time
VIN = 17 V, VOUT = 0.6 V, RRF = 39 kΩ,
TA = 25 °C(1)
150
35
RMODE = 39 kΩ
0.7
RMODE = 100 kΩ
1.4
RMODE = 200 kΩ
2.8
RMODE = 470 kΩ
5.6
ns
SOFT START
Internal soft-start time from
VOUT = 0 V to 95% of VOUT
tSS
ms
INTERNAL MOSFETS
6
RDS(on)H
High-side MOSFET on-resistance
TA = 25°C
5
mΩ
RDS(on)L
Low-side MOSFET on-resistance
TA = 25°C
2
mΩ
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Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
VTHPG
PG threshold
RPG
PG transistor on-resistance
tPGDEL
PG delay
PG in from lower
92.5%
95.0%
98.5%
PG in from higher
107.5%
110.0%
112.5%
2.5%
5.0%
7.5%
15
30
55
Ω
Delay for PG in
0.8
1
1.2
ms
Enable
1.8
PG hysteresis
LOGIC THRESHOLD AND SETTING CONDITIONS
VEN
EN Voltage
IEN
EN Input current
Disable
0.6
VEN = 5 V
1.0
RRF = 0 Ω to GND, TA =
25°C(2)
200
250
300
RRF = 187 kΩ to GND, TA = 25°C(2)
250
300
350
25°C(2)
350
400
450
450
500
550
25°C(2)
580
650
720
RRF = 309 kΩ to VREG, TA = 25°C(2)
670
750
820
25°C(2)
RRF = 619 kΩ, to GND, TA =
fSW
Switching frequency
V
RRF = Open, TA= 25°C(2)
RRF = 866 kΩ to VREG, TA =
RRF = 124 kΩ to VREG, TA =
770
850
930
RRF = 0 Ω to VREG, TA = 25°C(2)
880
970
1070
VTRIP = 1 V, TA = 25°C
9.4
10.0
10.6
µA
kHz
PROTECTION: CURRENT SENSE
ITRIP
TRIP source current
TCITRIP
TRIP current temperature coefficient
On the basis of
VTRIP
Current limit threshold setting range
VTRIP-GND
VOCL
Current limit threshold
VOCLN
Negative current limit threshold
VAZCADJ
Auto zero cross adjustable range
25°C(1)
4700
ppm/°C
0.4
2.4
VTRIP = 2.4 V
68.5
75.0
81.5
VTRIP = 0.4 V
7.5
12.5
17.5
VTRIP = 2.4 V
-315
-300
-285
VTRIP = 0.4 V
-58
-50
-42
Positive
3
Negative
µA
15
–15
–3
115%
120%
125%
65%
70%
V
mV
mV
mV
PROTECTION: UVP and OVP
VOVP
OVP trip threshold
OVP detect
tOVPDEL
OVP propagation delay
VFB delay with 50-mV overdrive
VUVP
Output UVP trip threshold
UVP detect
tUVPDEL
Output UVP propagation delay
tUVPEN
Output UVP enable delay
From enable to UVP workable
1
µs
75%
0.8
1.0
1.2
ms
1.8
2.6
3.2
ms
4.00
4.20
4.33
UVLO
VUVVREG
VREG UVLO threshold
Wake up
Hysteresis
0.25
Shutdown temperature(1)
145
V
THERMAL SHUTDOWN
TSDN
(1)
(2)
Thermal shutdown threshold
Hysteresis(1)
°C
10
Ensured by design. Not production tested.
Not production tested. Test condition is VIN= 12 V, VOUT= 1.1 V, IOUT = 10 A using application circuit shown in Figure 8-11.
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6.6 Typical Characteristics
700
7
600
6
500
400
300
200
VEN = 5V
VVDD = 12 V
VVFB = 0.63 V
No Load
100
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
5
4
3
2
0
−40 −25 −10
14
120
OVP/UVP Trip Threshold (%)
140
10
8
6
4
5
20 35 50 65 80
Junction Temperature (°C)
95
100
80
60
40
20
2
OVP
UVP
VVDD = 12 V
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
0
−40 −25 −10
110 125
Figure 6-3. TRIP Pin Current vs Junction
Temperature
95
110 125
1000
100
FCCM
Skip Mode
10
VIN = 12 V
VOUT = 1.1 V
fSW = 300 kHz
0.1
1
Output Current (A)
10
100
Switching Frequency (kHz)
Switching Frequency (kHz)
5
20 35 50 65 80
Junction Temperature (°C)
Figure 6-4. OVP/UVP Trip Threshold vs Junction
Temperature
1000
1
0.01
110 125
Figure 6-2. VDD Shutdown Current vs Junction
Temperature
16
12
VEN = 0 V
VVDD = 12 V
No Load
1
110 125
Figure 6-1. VDD Supply Current vs Junction
Temperature
TRIP Pin Current (µA)
VDD Shutdown Current (µA)
VDD Supply Current (µA)
For VOUT = 5 V, a 744355182 inductor is used. For 1 ≤ VOUT ≤ 3.3 V, a PA0513.441 inductor is used.
100
FCCM
Skip Mode
10
VIN = 12 V
VOUT = 1.1 V
fSW = 500 kHz
1
0.01
0.1
1
Output Current (A)
10
100
Figure 6-5. Switching Frequency vs Output Current Figure 6-6. Switching Frequency vs Output Current
8
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1000
Switching Frequency (kHz)
Switching Frequency (kHz)
1000
100
10
VIN = 12 V
VOUT = 1.1 V
fSW = 750 kHz
FCCM
Skip Mode
1
0.01
0.1
1
Output Current (A)
10
100
10
VIN = 12 V
VOUT = 1.1 V
fSW = 1 MHz
FCCM
Skip Mode
1
0.01
100
0.1
G001
1
Output Current (A)
10
100
Figure 6-7. Switching Frequency vs Output Current Figure 6-8. Switching Frequency vs Output Current
1500
1.120
fSET = 300 kHz
fSET = 500 kHz
fSET = 750 kHz
fSET = 1 MHz
1200
fSW = 500 kHz
VIN = 12 V
VOUT = 1.1 V
1.115
1.110
Output Voltage (V)
Switching Frequency (kHz)
VIN = 12 V
IOUT = 10 A
900
600
1.105
1.100
1.095
1.090
300
1.085
0
0
1
2
3
4
Output Voltage (V)
5
1.080
6
Figure 6-9. Switching Frequency vs Output Voltage
Skip Mode
FCCM
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30
Output Current (A)
Figure 6-10. Output Voltage vs Output Current
1.120
100
fSW = 500 kHz
VIN = 12 V
1.115
90
80
70
Efficiency (%)
Output Voltage (V)
1.110
1.105
1.100
1.095
60
VIN = 12 V
VVDD = 5 V
VOUT = 1.1 V
50
40
30
Skip Mode, fSW = 500 kHz
FCCM, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCCM, fSW = 300 kHz
1.090
FCCM, IOUT = 0 A
Skip Mode, IOUT = 0 A
FCCM and Skip Mode, IOUT = 20 A
1.085
1.080
4
6
8
10
12
Input Voltage (V)
14
16
Figure 6-11. Output Voltage vs Input Voltage
20
10
0
0.01
0.1
1
Output Current (A)
10
100
Figure 6-12. Efficiency vs Output Current
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100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
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85
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
80
75
70
0
5
10
15
20
Output Current (A)
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
25
95
90
90
Efficiency (%)
Efficiency (%)
95
85
80
70
0
5
10
15
20
Output Current (A)
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
25
95
90
90
85
0
2
4
6
8
10
12
14
Output Current (A)
FCCM
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
16
18
Figure 6-17. Efficiency vs Output Current
25
30
0
5
10
15
20
Output Current (A)
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
25
30
Figure 6-16. Efficiency vs Output Current
Efficiency (%)
Efficiency (%)
70
95
70
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
80
100
75
10
15
20
Output Current (A)
85
100
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
5
75
30
Figure 6-15. Efficiency vs Output Current
80
0
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
Figure 6-14. Efficiency vs Output Current
100
75
10
70
100
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
80
75
30
Figure 6-13. Efficiency vs Output Current
85
20
85
80
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
75
70
0
2
4
6
8
10
12
14
Output Current (A)
Skip Mode
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
16
18
20
Figure 6-18. Efficiency vs Output Current
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VIN = 12 V
VIN = 12 V
IOUT = 20 A
EN (5 V/div)
EN (5 V/div)
IOUT = 0 A
VOUT (0.5 V/div)
VOUT (0.5 V/div)
0.5 V pre-biased
VREG(5 V/div)
VREG(5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (1 ms/div)
Time (1 ms/div)
Figure 6-19. Start-Up Waveforms
Figure 6-20. Pre-Bias Start-Up Waveforms
VIN = 12 V
VEN = 5 V
IOUT = 20 A
EN (5 V/div)
VIN (5 V/div)
VDD = VIN
IOUT = 20 A
VOUT (0.5 V/div)
VOUT (0.5 V/div)
VREG(5 V/div)
VREG(5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (20 ms/div)
Time (2 ms/div)
Figure 6-21. Shutdown Waveforms
Figure 6-22. UVLO Start-Up Waveforms
Skip Mode
VIN = 12 V
IOUT = 0 A
FCCM
VIN = 12 V
IOUT = 0 A
VOUT (20 mV/div)
VOUT (20 mV/div)
LL (5 V/div)
LL (5 V/div)
IL (5 A/div)
IL (5 A/div)
Time (2 ms/div)
Time (1 ms/div)
Figure 6-23. 1.1-V Output FCCM Mode Steady-State
Operation
Figure 6-24. 1.1-V Output Skip Mode Steady-State
Operation
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Skip Mode
VIN = 12 V
VOUT = 1.1 V
Skip Mode
VIN = 12 V
VOUT = 1.1 V
VOUT (20 mV/div)
VOUT (20 mV/div)
LL (5 V/div)
LL (5 V/div)
IL (5 A/div)
IL (5 A/div)
Time (200 ms/div)
Time (200 ms/div)
Figure 6-25. CCM to DCM Transition Waveforms
Figure 6-26. DCM to CCM Transition Waveforms
FCCM
VIN = 12 V, VOUT = 1.1 V
Skip Mode
VIN = 12 V, VOUT = 1.1 V
IOUT from 0 A to 10 A, 2.5 A/ms
IOUT from 0 A to 10 A, 2.5 A/ms
VOUT (20 mV/div)
VOUT (20 mV/div)
IOUT (5 A/div)
IOUT (5 A/div)
Time (100 ms/div)
Time (100 ms/div)
Figure 6-27. FCCM Load Transient
IOUT from 20 A to 25 A
VOUT (1 V/div)
Figure 6-28. Skip Mode Load Transeint
VOUT (1 V/div)
IOUT 2 A then Short Output
VIN = 12 V
VIN = 12 V
LL (10 V/div)
LL (10 V/div)
IL (10 A/div)
IL (10 A/div)
IOUT (25 A/div)
PGOOD (5 V/div)
12
Time (10 ms/div)
Time (10 ms/div)
Figure 6-29. Overcurrent Protection Waveforms
Figure 6-30. Output Short Circuit Protection
Waveforms
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110
EN (5 V/div)
Ambient Temperature (qC)
100
VOUT (1 V/div)
VIN = 12 V
IOUT = 20 A
PGOOD (5 V/div)
90
80
70
60
50
Nat Conv
100 LFM
200 LFM
400 LFM
40
30
0
5
Time (1 s/div)
Figure 6-31. Over-temperature Protection
Waveforms
VIN = 12 V
10
15
20
Output Current (A)
VOUT = 1.2 V
25
30
D001
fSW = 500 kHz
Figure 6-32. Safe Operating Area
110
Ambient Temperature (qC)
100
90
80
70
60
50
Nat Conv
100 LFM
200 LFM
400 LFM
40
30
0
5
VIN = 12 V
10
15
20
Output Current (A)
VOUT = 5 V
25
30
D002
fSW = 500 kHz
Figure 6-33. Safe Operating Area
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7 Detailed Description
7.1 Overview
The TPS53355 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage
point-of-load applications in computing and similar digital consumer applications. The device features proprietary
D-CAP™ mode control combined with an adaptive on-time architecture. This combination is ideal for building
modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to
5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from 4.5 V to
25 V. The D-CAP™ mode uses the equivalent series resistance (ESR) of the output capacitor(s) to sense the
device current. One advantage of this control scheme is that it does not require an external phase compensation
network. This allows a simple design with a low external component count. Eight preset switching frequency
values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive on-time control
tracks the preset switching frequency over a wide input and output voltage range while allowing the switching
frequency to increase at the step-up of the load.
The TPS53355 has a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms as shown in Table 7-3.
7.2 Functional Block Diagram
0.6 V +10/15%
0.6 V –30%
+
UV
PGOOD
+
Delay
Delay
+
0.6 V –5/10%
Ramp
Compensation
Control Logic
+
+20%
+
VFB
VREG
0.6 V
SS
OV
UVP/OVP
Logic
RF
VBST
+
+ PWM
VIN
10 mA
GND
TRIP
tON
OneShot
+
+ OCP
LL
LL
XCON
+
GND
ZC
Control
Logic
SS
FCCM/
Skip
Decode
MODE
EN
·
·
·
·
·
+
1.2 V/0.95 V
GND
On/Off time
Minimum On/Off
Light load
OVP/UVP
FCCM/Skip
VDDOK
LL
Fault
Shutdown
TPS53355
LDO
+
VDD
4.2 V/
3.95 V
Enable
THOK
VREG
EN
+
145°C/
135°C
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Note
The thresholds in this block diagram are typical values. Refer to the Section 6.5 table for threshold
limits.
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7.3 Feature Description
7.3.1 5-V LDO and VREG Start-Up
TPS53355 provides an internal 5-V LDO function using input from VDD and output to VREG. When the VDD
voltage rises above 2 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage
provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.
Note
The 5-V LDO is controlled by the EN pin. The LDO starts-up any time VDD rises to approximately 2 V.
Figure 7-1
7.3.2 Adaptive On-Time D-CAP Control and Frequency Selection
The TPS53355 does not have a dedicated oscillator to determine switching frequency. However, the device
operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time
one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage
and proportional to the output voltage (tON ∝ VOUT/VIN).
This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 7-1. (Maintaining open resistance sets the
switching frequency to 500 kHz.)
Table 7-1. Resistor and Switching Frequency
RESISTOR (RRF)
CONNECTIONS
VALUE (kΩ)
CONNECT TO
SWITCHING
FREQUENCY
(fSW)
(kHz)
0
GND
250
187
GND
300
619
GND
400
OPEN
n/a
500
866
VREG
650
309
VREG
750
124
VREG
850
0
VREG
970
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts a set signal to terminate the off time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time
is extended until the current level falls below the threshold.
Figure 7-2 and Figure 7-3 show two on-time control schemes.
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Above 2 V
VFB
VDD
VREF
VREG
0.6 V
EN
VREF
PWM
tON
tOFF
VOUT
Soft-start
~550 µs
Figure 7-1. Power Up Sequence
UDG-10208
Figure 7-2. On-Time Control Without Ramp
Compensation
VFB
VREF
Compensation
Ramp
PWM
tON
tOFF
UDG-10209
Figure 7-3. On-Time Control With Ramp Compensation
7.3.3 Ramp Signal
The TPS53355 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in
the previous section, the feedback voltage is compared with the reference information to keep the output voltage
in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in
steady state.
During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than
the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the
ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset.
7.3.4 Adaptive Zero Crossing
The TPS53355 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too
early detection. As a result, better light load efficiency is delivered.
7.3.5 Power-Good
The TPS53355 has power-good output that indicates high when switcher output is within the target. The powergood function is activated after soft-start has finished. If the output voltage becomes within +10% and –5% of
the target value, internal comparators detect power-good state and the power-good signal becomes high after
a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good
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signal becomes low after two microsecond (2-μs) internal delay. The power-good output is an open drain output
and must be pulled up externally.
The power-good MOSFET is powered through the VDD pin. VVDD must be >1 V in order to have a valid
power-good logic. It is recommended to pull PGOOD up to VREG (or a voltage divided from VREG) so that the
power-good logic is still valid even without VDD supply.
7.3.6 Current Sense, Overcurrent and Short Circuit Protection
TPS53355 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period in that the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53355 supports
temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the
trip voltage setting resistor, RTRIP. The TRIP terminal sources current (ITRIP) which is 10 μA typically at room
temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 1.
VTRIP (mV ) = RTRIP (kW )´ ITRIP (mA )
(1)
The inductor current is monitored by the LL pin. The GND pin is used as the positive current sensing node and
the LL pin is used as the negative current sense node. The trip current, ITRIP has 4700ppm/°C temperature slope
to compensate the temperature dependency of the RDS(on).
As the comparison is made during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the
load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 2.
IOCP =
VTRIP
(32 ´ RDS(on) )
+
IIND(ripple)
2
=
VTRIP
(32 ´ RDS(on) )
+
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
(2)
In an overcurrent or short circuit condition, the current to the load exceeds the current to the output capacitor
thus the output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts
down. After a hiccup delay (16 ms with 0.7 ms sort-start), the controller restarts. If the overcurrent condition
remains, the procedure is repeated and the device enters hiccup mode.
Hiccup time calculation:
tHIC(wait) = (2n + 257) × 4 µs
(3)
where
•
n = 8, 9, 10, or 11 depending on soft start time selection
tHIC(dly) = 7 × (2n + 257) × 4 µs
(4)
Table 7-2. Hiccup Delay
SELECTED SOFT-START TIME (tSS) (ms)
n
HICCUP WAIT TIME (tHIC(wait))
(ms)
HICCUP DELAY TIME (tHIC(dly)) (ms)
0.7
8
2.052
14.364
1.4
9
3.076
21.532
2.8
10
5.124
35.868
5.6
11
9.220
64.540
7.3.7 Overvoltage and Undervoltage Protection
TPS53355 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal
UVP delay counter begins counting. After 1ms, TPS53355 latches OFF both high-side and low-side MOSFETs
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drivers. The controller restarts after a hiccup delay (16 ms with 0.7 ms soft-start). This function is enabled 1.5-ms
after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver.
The output voltage decreases. If the output voltage reaches UV threshold, then both high-side MOSFET and
low-side MOSFET driver will be OFF and the device restarts after a hiccup delay. If the OV condition remains,
both high-side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed.
7.3.8 UVLO Protection
The TPS53355 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than 3.95
V, the device shuts off. When the VREG voltage is higher than 4.2 V, the device restarts. This is a non-latch
protection.
7.3.9 Thermal Shutdown
TPS53355 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 145°C),
TPS53355 is shut off. When the temperature falls about 10°C below the threshold value, the device will turn
back on. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Enable, Soft Start, and Mode Selection
When the EN pin voltage rises above the enable threshold voltage (typically 1.2 V), the controller enters its
start-up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The
controller then uses the first 250 μs to calibrate the switching frequency setting resistance attached to the RF
pin and stores the switching frequency code in internal registers. During this period, the MODE pin also senses
the resistance attached to this pin and determines the soft-start time. Switching is inhibited during this phase.
In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on
the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
Table 7-3. Soft-Start and MODE Settings
MODE SELECTION
ACTION
Auto Skip
Forced CCM(1)
(1)
Pull down to GND
Connect to PGOOD
SOFT-START TIME (ms)
RMODE (kΩ)
0.7
39
1.4
100
2.8
200
5.6
475
0.7
39
1.4
100
2.8
200
5.6
475
Device enters FCCM after the PGOOD pin goes high when MODE is connected to PGOOD through
the resistor RMODE.
After soft start begins, the MODE pin becomes the input of an internal comparator which determines auto skip or
FCCM mode operation. If MODE voltage is higher than 1.3 V, the converter enters into FCCM mode. Otherwise
it will be in auto skip mode at light load condition. Typically, when FCCM mode is selected, the MODE pin is
connected to PGOOD through the RMODE resistor, so that before PGOOD goes high the converter remains in
auto skip mode.
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7.4.2 Auto-Skip Eco-mode™ Light Load Operation
While the MODE pin is pulled low via RMODE, TPS53355 automatically reduces the switching frequency at light
load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is
kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge
the output capacitor with smaller load current to the level of the reference voltage. The transition point to the
light-load operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be
calculated as shown in Equation 5.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
(5)
where
•
ƒSW is the PWM switching frequency
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 5. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
7.4.3 Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load
range which is suitable for applications that need tight control of the switching frequency at a cost of lower
efficiency.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS53355 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage
point-of-load applications in computing and similar digital consumer applications. The device features proprietary
D-CAP mode control combined with an adaptive on-time architecture. This combination is ideal for building
modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to
5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from 4.5 V to
25 V. The D-CAP mode uses the equivalent series resistance (ESR) of the output capacitor(s) to sense
the device current . One advantage of this control scheme is that it does not require an external phase
compensation network. This allows a simple design with a low external component count. Eight preset switching
frequency values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive
on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing
the switching frequency to increase at the step-up of the load.
8.1.1 Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure
8-1.
TPS53355
Switching Modulator
VIN
VIN
R1
VFB
PWM
1
R2
+
+
Control
Logic
and
Divider
LL
L
VOUT
IIND
IC
IOUT
0.6 V
ESR
RLOAD
Voltage
Divider
VC
COUT
Output
Capacitor
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
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H (s ) =
1
s ´ ESR ´ COUT
(6)
For loop stability, the 0-dB frequency, ƒ0, defined below need to be lower than 1/4 of the switching frequency.
f0 =
f
1
£ SW
2p ´ ESR ´ COUT
4
(7)
According to the equation above, the loop stability of D-CAPTM mode modulator is mainly determined by the
capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance in the
order of several 100 µF and ESR in range of 10 mΩ. These makes ƒ0 on the order of 100 kHz or less, creating
a stable loop. However, ceramic capacitors have an ƒ0 at more than 700 kHz, and need special care when used
with this modulator. An application circuit for ceramic capacitor is described in Section 8.2.1.2.3.
8.2 Typical Applications
8.2.1 Typical Application Circuit Diagram with Ceramic Output Capacitors
C4
4.7 mF
R4
NI
R8
147 kW
C3
1 mF
VVDD
4.5 V to 25 V
R6
200 kW
22
21
20
19
18
RF
TRIP
MODE
VDD
17
VREG VIN
16
15
14
13
12
VIN
VIN
VIN
VIN
VIN
TPS53355
CIN
22 mF
VFB
EN
1
2
PGOOD
EN
PGOOD VBST
3
4
N/C
LL
LL
LL
LL
LL
LL
5
6
7
8
9
10
11
R2
10 kW
R7
3.01 kW
R11
NI
R9
2W
C5
0.1 mF
CIN
22 mF
CIN
22 mF
VOUT
L1
0.44 mH
PA0513.441
GND
VREG
R10
100 kW
CIN
22 mF
VIN 8 V
to
14 V
C1
0.1 mF
C2
1 nF
COUT
4 x 100 mF
Ceramic
C6
NI
R1 14.7 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 8-2. Typical Application Circuit Diagram with Ceramic Output Capacitors Schematic
22
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8.2.1.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
TEST CONDITION
MIN
TYP
MAX
12
14
UNIT
INPUT CHARACTERISTICS
VIN
IMAX
Voltage range
8
Maximum input current
VIN = 8 V, IOUT = 30 A
No load input current
VIN = 14 V, IOUT = 0 A with auto-skip mode
V
6.3
A
1
mA
OUTPUT CHARACTERISTICS
Output voltage
VOUT
1.5
Line regulation, 8 V ≤ VIN ≤ 15 V
0.1%
Output voltage regulation
Load regulation, VIN = 12 V, 0 A ≤ IOUT ≤ 30
A with FCCM
0.2%
VIN = 12 V, IOUT = 30 A with FCCM
VRIPPLE
Output voltage ripple
ILOAD
Output load current
20
IOCP
Output overcurrent threshold
34
A
tSS
Soft-start time
1.4
ms
500
kHz
0
mVPP
30
A
SYSTEMS CHARACTERISTICS
fSW
η
TA
Switching frequency
Peak efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A
91.87%
Full load efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 30 A
89.46%
Operating temperature
25
°C
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS53355 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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8.2.1.2.2 External Component Selection
The external components selection is a simple process when using organic semiconductors or special polymer
output capacitors.
1. Select Operation Mode and Soft-Start Time
Select operation mode and soft-start time using Table 7-3.
2. Select Switching Frequency
Select the switching frequency from 250 kHz to 1 MHz using Table 7-1.
3. Choose the Inductor
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of
maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise
ratio and helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to
maximum output current ratio, the inductance can be determined by Equation 8.
L=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max)
(8)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 9.
IIND(peak ) =
VTRIP
1
+
´
32 ´ RDS(on ) L ´ fSW
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(9)
4. External Component Selection with All Ceramic Output Capacitors
Refer to Section 8.2.1.2.3 to select external components because ceramic output capacitors are used in this
design.
5. Choose the Overcurrent Setting Resistor
The overcurrent setting resistor, RTRIP, can be determined by Equation 10.
æ
æ
1
çç IOCP - ç
2
L
´
´ fSW
è
RTRIP (kW) = è
ö (VIN - VOUT )´ VOUT
÷´
VIN
ø
ITRIP (mA)
ö
÷÷ ´ 32 ´ RDS(on) (mW )
ø
(10)
where
•
•
ITRIP is the TRIP pin sourcing current (10 µA)
RDS(on) is the thermally compensated on-time resistance value of the low-side MOSFET
Use an RDS(on) value of 1.5 mΩ for an overcurrent level of approximately 30 A. Use an RDS(on) value of
1.7 mΩ for overcurrent level of approximately 10 A.
6. BST Resistor Selection
The recommended BST resistor value is 2 Ω and anything larger than 5.1 Ω is not recommended. Note
that when the gate drive turns on, the voltage on the boot-strap capacitor splits between the internal pull-up
resistance and the boot-strap resistance, with the internal circuits only seeing the portion across the internal
pull-up resistance. Therefore, when the external resistor gets larger than the pull-up resistance, it crashes
the head-room of the SW to BOOT logic, which can cause logic issues with the high-side gate driver.
24
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8.2.1.2.3 External Component Selection Using All Ceramic Output Capacitors
When a ceramic output capacitor is used, the stability criteria in Equation 7 cannot be satisfied. The ripple
injection approach as shown in Figure 8-2 is implemented to increase the ripple on the VFB pin and make the
system stable. In addition to the selections made using steps 1 through step 6 in Section 8.2.1.2.2, the ripple
injection components must be selected. The C2 value can be fixed at 1 nF. The value of C1 can be selected
between 10 nF to 200 nF.
L ´ COUT
t
> N ´ ON
R7 ´ C1
2
(11)
where
•
N is the coefficient to account for L and COUT variation
N is also used to provide enough margin for stability. It is recommended N=2 for VOUT ≤ 1.8 V and N=4 for VOUT
≥ 3.3 V or when L ≤ 250 nH. The higher VOUT needs a higher N value because the effective output capacitance
is reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor may have only 8 µF
of effective capacitance when biased at 5 V.
Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase
of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node
and the other coupled from the VOUT pin and they can be calculated using Equation 12 and Equation 13 when
neglecting the output voltage ripple caused by equivalent series inductance (ESL).
V - VOUT
D
´
VINJ _ SW = IN
R7 ´ C1
fSW
VINJ _ OUT = ESR ´ IIND(ripple ) +
(12)
IIND(ripple )
8 ´ COUT ´ fSW
(13)
It is recommended that VINJ_SW to be less than 50 mV and VINJ_TOTAL to be less than 60 mV. If the calculated
VINJ_SW is higher than 50 mV, then other parameters need to be adjusted to reduce it. For example, COUT can be
increased to satisfy Equation 11 with a higher R7 value, thereby reducing VINJ_SW. Use Equation 14 to calculate
COUT capacitance needed. For a more holistic calculation, please reference the TPS53355 calculator on ti.com
COUT
VIN MAX
VOUT
2 u L u VINJ MAX
u N u t ON
(14)
The DC voltage at the VFB pin can be calculated by Equation 15:
VVFB = 0.6 +
VINJ _ SW + VINJ _ OUT
2
(15)
And the resistor divider value can be determined by Equation 16:
- VVFB
V
´ R2
R1 = OUT
VVFB
(16)
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8.2.1.3 Application Curves
TPS5335EVM
Enable Start Up
TPS5335EVM
Enable Shut Down
Test condition: 12 Vin, 1.5 V/30 A
Auto Skip Mode
Test condition: 12 Vin, 1.5 V/30 A
Auto Skip Mode
CH1: EN
CH1: EN
CH2: 1.5 Vout
CH2: 1.5 Vout
CH3: PGOOD
CH3: PGOOD
Figure 8-4. Enable Turn-off
Figure 8-3. Enable Turn-on
TPS5335EVM
Output Transient from DCM to CCM
TPS5335EVM
Output Transient from CCM to DCM
Test condition: 12 Vin, 0 A -15 A
Auto Skip Mode
Test condition: 12 Vin, 1.5 V/15 A-0 A
Auto Skip Mode
CH1: 1.5 Vout
CH1: 1.5 Vout
CH4: Output Current
CH4: Output Current
Figure 8-5. Output Transient From DCM to CCM
TPS5335EVM
Output Transient from 0 A to 15 A
Test condition: 12 Vin, 1.5 V/0 A-15 A
FCCM Mode
Figure 8-6. Output Transient From CCM to DCM
TPS5335EVM
0.75 V Pre-bias Enable Start up
Test condition: 12 Vin, 1.5 V/0 A
FCCM Mode
CH1: EN
CH1: 1.5 Vout
CH2: 1.5 Vout
CH4: output Current
CH3: PGOOD
Figure 8-7. Output Transient With FCCM Mode
26
Figure 8-8. Output 0.75-V Prebias Turn-on
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TPS53355EVM
Over Current Protection
Test Condition: 12 Vin OCP
Test Condition: 12 Vin,
1.5 V Short Circuit
TPS53355EVM
Short Circuit Protection
Ch1: 1.5 Vout
Ch1: 1.5 Vout
Ch2: LL
Ch2: LL
Ch3: PGOOD
Ch3: PGOOD
Figure 8-10. Output Short Circuit Protection
Figure 8-9. Output Overcurrent Protection
8.2.2 Typical Application Circuit
C4
4.7 mF
C3
1 mF
R6
200 kW
R4
NI
VVDD
4.5 V to 25 V
R8
147 kW
22
21
20
19
RF
TRIP
MODE
VDD
18
17
VREG VIN
16
15
14
13
12
VIN
VIN
VIN
VIN
VIN
TPS53355
C IN
22 mF
C IN
22 mF
C IN
22 mF
C IN
22 mF
GND
VREG
L1
0.44 mH
PA 0513.441
R10
100 kW
VFB
EN
PGOOD
VBST
N/C
LL
LL
LL
LL
LL
LL
1
2
3
4
5
6
7
8
9
10
11
R2
10 kW
VOUT
R11
NI
R9
2W
PGOOD
EN
VIN 8 V
to
14 V
C6
NI
C5
0.1 mF
C OUT
330 mF
C OUT
330 mF
R1
15 kW
UDG-11002
Figure 8-11. Typical Application Circuit Diagram
8.2.2.1 Design Requirements
Table 8-2. Design Parameters
PARAMETER
TEST CONDITION
MIN
TYP
MAX
12
14
UNIT
INPUT CHARACTERISTICS
VIN
IMAX
Voltage range
8
Maximum input current
VIN = 8 V, IOUT = 30 A
No load input current
VIN = 14 V, IOUT = 0 A with auto-skip mode
6.3
V
A
1
mA
OUTPUT CHARACTERISTICS
Output voltage
VOUT
VRIPPLE
1.5
Line regulation, 8 V ≤ VIN ≤ 15 V
0.1%
Output voltage regulation
Load regulation, VIN = 12 V, 0 A ≤ IOUT ≤ 30 A with
FCCM
0.2%
Output voltage ripple
VIN = 12 V, IOUT = 30 A with FCCM
20
0
mVPP
ILOAD
Output load current
IOCP
Output overcurrent threshold
34
30
A
A
tSS
Soft-start time
1.4
ms
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Table 8-2. Design Parameters (continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SYSTEMS CHARACTERISTICS
fSW
η
TA
28
Switching frequency
500
Peak efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A
91.87%
Full load efficiency
VIN = 12 V, VOUT = 1.1 V, IOUT = 30 A
89.46%
Operating temperature
25
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kHz
°C
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8.2.2.2 Detailed Design Procedure
8.2.2.2.1 External Component Selection
Refer to Section 8.2.1.2.3 for guidelines for this design with all ceramic output capacitors.
The external components selection is a simple process when using organic semiconductors or special polymer
output capacitors.
1. Select operation mode and soft-start time
Select operation mode and soft-start time using Table 7-3.
2. Select switching frequency
Select the switching frequency from 250 kHz to 1 MHz using Table 7-1.
3. Choose the inductor
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of
maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise
ratio and helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to
maximum output current ratio, the inductance can be determined by Equation 17.
L=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
=
3
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max)
(17)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 9.
IIND(peak ) =
VTRIP
1
+
´
32 ´ RDS(on ) L ´ fSW
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(18)
4. Choose the output capacitors
When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability,
capacitance and ESR should satisfy Equation 7. For jitter performance, Equation 19 is a good starting point
to determine ESR.
ESR =
VOUT ´ 10mV ´ (1 - D) 10mV ´ L ´ fSW L ´ fSW
=
=
(W )
0.6 V ´ IIND(ripple )
0.6 V
60
(19)
where
•
•
D is the duty factor.
The required output ripple slope is approximately 10 mV per tSW (switching period) in terms of VFB
terminal voltage.
5. Determine the value of R1 and R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 8-1. R1
is connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 20.
VOUT R1 =
IIND(ripple ) ´ ESR
2
0.6
- 0.6
´ R2
(20)
6. Choose the overcurrent setting resistor
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The overcurrent setting resistor, RTRIP, can be determined by Equation 10.
æ
æ
1
çç IOCP - ç
2
L
´
´ fSW
è
RTRIP (kW) = è
ö (VIN - VOUT )´ VOUT
÷´
VIN
ø
ITRIP (mA)
ö
÷÷ ´ 32 ´ RDS(on) (mW )
ø
(21)
where
•
•
ITRIP is the TRIP pin sourcing current (10 µA)
RDS(on) is the thermally compensated on-time resistance value of the low-side MOSFET
Use an RDS(on) value of 1.5 mΩ for an overcurrent level of approximately 30 A. Use an RDS(on) value of
1.7 mΩ for overcurrent level of approximately 10 A.
8.2.2.3 Application Curves
TPS5335EVM
Enable Start Up
Test condition: 12 Vin, 1.5 V/30 A
Auto Skip Mode
CH1: EN
TPS5335EVM
Enable Shut Down
Test condition: 12 Vin, 1.5 V/30 A
Auto Skip Mode
CH1: EN
CH2: 1.5 Vout
CH3: PGOOD
CH2: 1.5 Vout
CH3: PGOOD
Figure 8-12. Enable Turn-on
Figure 8-13. Enable Turn-off
30
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 1.5 V and 22 V (4.5-V to 25-V
biased). This input supply must be well regulated. Proper bypassing of input supplies and internal regulators
is also critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in
Section 10.
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10 Layout
10.1 Layout Guidelines
Certain points must be considered before starting a layout work using the TPS53355.
•
•
•
•
•
•
•
•
•
32
The power components (including input/output capacitors, inductor and TPS53355) must be placed on one
side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, in order to
shield and isolate the small signal traces from noisy power lines.
All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
Because the TPS53355 controls output voltage referring to voltage across VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. Connect the
GND of the bottom side resistor to the GND pad of the device. The trace from these resistors to the VFB pin
should be short and thin.
Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as
close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
Place the VDD and VREG decoupling capacitors as close as possible to the device. Make sure GND vias are
provided for each decoupling capacitor and make the loop as small as possible.
The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 8-2) from the terminal of
ceramic output capacitor. The AC coupling capacitor (C2 in Figure 8-2) should be placed near the device, and
R7 and C1 can be placed near the power stage.
Use separate vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor.
Do not combine these connections.
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10.2 Layout Example
Figure 10-1. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using TPS53355 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
Eco-mode™ is a trademark of TI.
NexFET™, PowerPAD™, SWIFT™, D-CAP™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
34
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS53355DQPR
ACTIVE
LSON-CLIP
DQP
22
2500
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
53355DQP
Samples
TPS53355DQPT
ACTIVE
LSON-CLIP
DQP
22
250
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
53355DQP
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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