TPS562201, TPS562208
TPS562208
SLVSD91B – DECEMBER 2015 TPS562201,
– REVISED SEPTEMBER
2020
SLVSD91B – DECEMBER 2015 – REVISED SEPTEMBER 2020
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TPS56220x 4.5-V to 17-V Input, 2-A Synchronous Step-Down Voltage Regulator
in 6-Pin SOT-23
1 Features
3 Description
•
The TPS562201 and TPS562208 are simple, easy-touse, 2-A synchronous step-down converters in
SOT-23 package.
•
•
•
•
•
•
•
•
•
•
•
•
TPS562201 and TPS562208 2-A converter
integrated 140-mΩ and 84-mΩ FETs
D-CAP2™ mode control with fast transient
response
Input voltage range: 4.5 V to 17 V
Output voltage range: 0.76 V to 7 V
Pulse-skip mode (TPS562201) or continuous
current mode (TPS562208)
580-kHz Switching frequency
Low shutdown current less than 10 µA
2% Feedback voltage accuracy (25°C)
Start-up from pre-biased output voltage
Cycle-by-cycle overcurrent limit
Hiccup-mode overcurrent protection
Non-latch UVP and TSD protections
Fixed soft start: 1.0 ms
The devices are optimized to operate with minimum
external component counts and also optimized to
achieve low standby current.
These switch mode power supply (SMPS) devices
employ D-CAP2 mode control providing a fast
transient response and supporting both low equivalent
series resistance (ESR) output capacitors such as
specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
The TPS562201 operates in pulse skip mode, which
maintains high efficiency during light load operation.
The TPS562201 and TPS562208 are available in a 6pin 1.6 × 2.9 (mm) SOT (DDC) package and specified
from –40°C to 125°C of junction temperature.
2 Applications
•
•
•
•
•
Digital TV power supply
High definition Blu-ray™ disc players
Networking home terminal
Digital set-top box (STB)
Surveillance
Device Information
PART NUMBER
TPS562201
TPS562208
(1)
PACKAGE(1)
SOT (6)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100%
90%
TPS562201
1
COUT
3
VIN
VBST
SW
EN
VIN
VFB
70%
5
EN
4
VOUT
Efficiency
2
VOUT
80%
6
GND
60%
50%
40%
30%
CIN
VOUT = 1.05 V
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
20%
10%
Simplified Schematic
0
0.001
0.01 0.02 0.05 0.1 0.2
Iload (A)
0.5
1
2 3 45
D021
TPS562201 Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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SLVSD91B – DECEMBER 2015 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................10
8 Application and Implementation.................................. 12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Power Supply Recommendations................................18
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................19
11.1 Receiving Notification of Documentation Updates.. 19
11.2 Support Resources................................................. 19
11.3 Trademarks............................................................. 19
11.4 Electrostatic Discharge Caution.............................. 19
11.5 Glossary.................................................................. 19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2017) to Revision B (September 2020)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
• Changed to 'TPS562201' from 'TPS563201' in "TPS562201 Efficiency"............................................................1
• Changed 'TPS563201' to 'TPS562201' in "TPS562201 Supply Current vs Junction Temperature"................... 6
• Changed to 'TPS562208' from 'TPS563208' and 'TPS562201' from 'TPS563208' in "Line Regulation".......... 15
• Changed to 'TPS562201' from 'TPS563201' in "TPS562201 Efficiency, VOUT = 1.05 V"................................. 15
Changes from Revision * (December 2015) to Revision A (December 2017)
Page
• Deleted the OVP comparator from the block diagram. ...................................................................................... 9
2
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5 Pin Configuration and Functions
1
GND
2
SW
3
VIN
TPS562201
VBST
6
EN
5
VFB
4
Figure 5-1. 6-Pin SOT DDC Package (Top View)
Pin Functions
PIN
NAME
DESCRIPTION
NO.
GND
1
Ground pin source terminal of low-side power NFET as well as the ground terminal for controller circuit.
Connect sensitive VFB to this GND at a single point.
SW
2
Switch node connection between high-side NFET and low-side NFET
VIN
3
Input voltage supply pin. The drain terminal of high-side power NFET
VFB
4
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
5
Enable input control. Active high and must be pulled up to enable the device
VBST
6
Supply input for the high-side NFET gate drive circuit. Connect a 0.1-µF capacitor between VBST and SW pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input voltage
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
VBST
–0.3
25
V
VBST (10-ns transient)
–0.3
27
V
VBST (vs SW)
–0.3
6.5
V
VFB
–0.3
6.5
V
SW
–2
19
V
–3.5
21
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
SW (10 ns transient)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
MIN
MAX
4.5
17
VBST
–0.1
23
VBST (10-ns transient)
–0.1
26
VBST(vs SW)
–0.1
6.0
EN
–0.1
17
VFB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
125
Supply input voltage
VI
Input voltage
TJ
Operating junction temperature
UNIT
V
V
°C
6.4 Thermal Information
THERMAL METRIC(1)
TPS562201 and
TPS562208
DDC (SOT)
UNIT
6 PINS
4
RθJA
Junction-to-ambient thermal resistance
90.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
°C/W
RθJB
Junction-to-board thermal resistance
16.3
°C/W
ψJT
Junction-to-top characterization parameter
2.6
°C/W
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TPS562201 and
TPS562208
THERMAL METRIC(1)
UNIT
DDC (SOT)
6 PINS
ψJB
(1)
Junction-to-board characterization parameter
16.3
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to 125°C, V = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TPS562201
380
520
TPS562208
590
750
1
10
UNIT
SUPPLY CURRENT
IVIN
Operating – non-switching supply VIN current, EN = 5 V, VFB =
current
0.8 V
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
µA
µA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
REN
EN pin resistance to GND
VEN = 12 V
1.6
225
V
400
0.8
V
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB threshold voltage
VO = 1.05 V, IO = 10 mA, Eco-mode™ operation
VFBTH
VFB threshold voltage
VO = 1.05 V, continuous mode operation
IVFB
VFB input current
VFB = 0.8 V
RDS(on)h
High-side switch resistance
TA = 25°C, VBST – SW = 5.5 V
RDS(on)l
Low-side switch resistance
TA = 25°C
774
749
mV
768
787
mV
0
±0.1
µA
MOSFET
140
mΩ
84
mΩ
CURRENT LIMIT
Iocl
Current limit
DC current, VOUT = 1.05 V, L1 = 2.2 µH
2.4
3.2
4.0
A
THERMAL SHUTDOWN
Thermal shutdown threshold(1)
TSDN
Shutdown temperature
160
Hysteresis
°C
25
ON-TIME TIMER CONTROL
tOFF(MIN)
Minimum off time
VFB = 0.5 V
220
310
ns
Soft-start time
Internal soft-start time
1.0
ms
Switching frequency
VIN = 12 V, VO = 1.05 V, FCCM mode
580
kHz
SOFT START
tss
Frequency
Fsw
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP threshold
THICCUP_WAI
Hiccup wait time
1.8
ms
Hiccup time before restart
15
ms
T
THICCUP_RE
Hiccup detect (H > L)
65%
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shut down VIN voltage
Hysteresis VIN voltage
(1)
4.0
3.3
3.6
4.3
V
0.4
Not production tested
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6.6 Typical Characteristics
0.55
0.770
0.50
0.769
0.45
0.768
FB Voltage (V)
Buck Quiescent Current (mA)
VIN = 12 V (unless otherwise noted)
0.40
0.35
0.30
0.767
0.766
0.765
0.25
0.764
±50
±20
10
40
70
100
Junction Temperature (ƒC)
130
±50
±20
Figure 6-1. TPS562201 Supply Current vs Junction
Temperature
10
40
70
100
Junction Temperature (ƒC)
C001
130
C002
Figure 6-2. VFB Voltage vs Junction Temperature
1.23
1.50
EN Pin UVLO - High (V)
EN Pin UVLO - Low (V)
1.20
1.17
1.14
1.11
1.08
1.47
1.44
1.41
1.38
1.05
1.02
1.35
±50
±20
10
40
70
100
Junction Temperature (ƒC)
130
±20
130
230
120
190
170
150
130
110
40
70
100
130
C003
Figure 6-4. EN Pin UVLO High Voltage vs Junction
Temperature
250
210
10
Junction Temperature (ƒC)
Low Side Rds_on (mŸ)
High Side Rds_on (mŸ)
Figure 6-3. EN Pin UVLO Low Voltage vs Junction
Temperature
110
100
90
80
70
60
90
50
70
±50
±20
10
40
70
100
Junction Temperature (ƒC)
Figure 6-5. High-Side Rds-on vs Junction
Temperature
6
±50
C004
130
±50
±30
±10
10
30
50
70
90
110
Junction Temperature (ƒC)
C005
130
C006
Figure 6-6. Low-Side Rds-on vs Junction
Temperature
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620
600.0
600
500.0
580
400.0
Fsw (Khz)
Fsw (Khz)
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560
540
Vout = 1.05 V
Vout = 1.8 V
Vout = 5 V
300.0
200.0
Vout = 1.05 V
520
100.0
Vout = 3.3 V
Vout = 5 V
500
4
6
8
10
12
14
16
VIN (V)
0.0
0.001
18
0.010
Iout = 10 mA
C013
Figure 6-8. TPS562201 Switching Frequency vs
Output Current
1.0
1.0
0.9
0.9
0.8
0.8
0.7
0.7
Efficiency
Efficiency
1.000
VIN = 12 V
Figure 6-7. TPS562208 Switching Frequency vs
Input Voltage
0.6
0.5
0.6
0.5
0.4
0.4
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.3
0.2
0.1
0.001
0.100
IOUT (A)
C012
0.010
0.100
0.2
0.1
0.001
1.000
I-load (A)
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.3
0.010
0.100
1.000
I-load (A)
C015
C017
1.0
1.0
0.9
0.9
0.8
0.8
0.7
0.7
Efficiency
Efficiency
Figure 6-9. TPS562201 VOUT = 1.05 V Efficiency, L = Figure 6-10. TPS562201 VOUT = 1.5 V Efficiency, L =
2.2 µH
2.2 µH
0.6
0.5
0.4
0.5
0.4
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.3
0.2
0.1
0.001
0.6
0.010
0.100
I-load (A)
1.000
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.3
0.2
0.1
0.001
C018
0.010
0.100
1.000
I-load (A)
C019
Figure 6-11. TPS562201 VOUT = 1.8 V Efficiency, L = Figure 6-12. TPS562201 VOUT = 3.3 V Efficiency, L =
2.2 µH
3.3 µH
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1.0
1.0
0.9
0.9
0.8
0.8
0.7
Efficiency
Efficiency
0.7
0.6
0.5
0.4
0.4
0.010
0.100
0.1
0.0
0.001
1.000
I-load (A)
0.010
0.9
0.8
0.8
0.7
0.7
0.6
0.6
Efficiency
1.0
0.9
0.4
1.000
C022
Figure 6-14. TPS562208 VOUT = 1.05 V Efficiency, L
= 2.2 µH
1.0
0.5
0.100
Iload (A)
C020
Figure 6-13. TPS562201 VOUT = 5 V Efficiency, L =
3.3 µH
0.3
0.5
0.4
0.3
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.2
0.1
0.0
0.001
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.2
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.2
Efficiency
0.5
0.3
0.3
0.1
0.001
0.6
0.010
0.100
Iload (A)
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.2
0.1
0.0
0.001
1.000
0.010
0.100
Iload (A)
C022
1.000
C022
1.0
1.0
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
Efficiency
Efficiency
Figure 6-15. TPS562208 VOUT = 1.5 V Efficiency, L = Figure 6-16. TPS562208 VOUT = 1.8 V Efficiency, L =
2.2 µH
2.2 µH
0.5
0.4
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.2
0.1
0.010
0.100
Iload (A)
1.000
0.2
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.1
0.0
0.001
0.010
0.100
Iload (A)
C022
Figure 6-17. TPS562208 VOUT = 3.3 V Efficiency, L =
2.2 µH
8
0.4
0.3
0.3
0.0
0.001
0.5
1.000
C022
Figure 6-18. TPS562208 VOUT = 5 V Efficiency, L =
3.3 µH
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7 Detailed Description
7.1 Overview
The TPS562201 and TPS562208 are 2-A synchronous step-down converters. The proprietary D-CAP2 mode
control supports low-ESR output capacitors, such as specialty polymer capacitors and multi-layer ceramic
capacitors, without complex external compensation circuits. The fast transient response of D-CAP2 mode control
can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN 5
VUVP
+
UVP
Hiccup
3
VIN
6
VBST
2
SW
1
GND
VREG5
Regulator
UVLO
VFB
4
Voltage
Reference
Ref
Soft Start
SS
PWM
+
+
HS
Control Logic
Ton
One-Shot
XCON
VREG5
TSD
LS
OCL
threshold
OCL
+
+
ZC
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7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562201 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 mode control.
7.3.2 Pulse Skip Control (TPS562201)
The TPS562201 and TPS562208 are designed with Advanced Eco-mode to maintain high light load efficiency.
As the output current decreases from heavy load condition, the inductor current is also reduced and eventually
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comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction
and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The ontime is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The
transition point to the light load operation IOUT(LL) current can be calculated in Equation 1.
IOUT(LL) =
(V - VOUT ) ´ VOUT
1
´ IN
2 ´ L ´ fSW
VIN
(1)
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS562201 and TPS562208 have an internal 1.0-ms soft start. When the EN pin becomes high, the internal
soft-start function begins ramping up the reference voltage to the PWM comparator. If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the internal reference voltage
becomes greater than the feedback voltage, VFB. This scheme ensures that the converters ramp up smoothly
into regulation point.
7.3.4 Current Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current, Iout. If the monitored current is
above the OCL level, the converter keeps the low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
from the converter. This can cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it, then the device will shut down after the UVP delay time
(typically 24 µs) and restart after the hiccup time (typically 15 ms).
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.5 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.6 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS562200 can operate in their normal switching modes. Normal continuous conduction mode (CCM) occurs
when the minimum switch current is above 0 A. In CCM, the TPS562208 operates at a quasi-fixed frequency of
580 kHz.
10
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7.4.2 Eco-mode Operation
When the TPS562201 and TPS562208 are in the normal CCM operating mode and the switch current falls to 0
A, the TPS562200 begins operating in pulse skipping Eco-mode. Each switching cycle is followed by a period of
energy saving sleep time. The sleep time ends when the VFB voltage falls below the Eco-mode threshold
voltage. As the output current decreases, the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS562201 and TPS562208 are operating in either normal CCM or Eco-mode, they can be placed in
standby by asserting the EN pin low.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The devices are typical step-down DC-DC converters. It typically uses to convert a higher dc voltage to a lower
dc voltage with a maximum available output current of 2 A. The following design procedure can be used to select
component values for the TPS562201 and TPS562208. Alternately, the WEBENCH® software may be used to
generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a
comprehensive database of components when generating a design. This section presents a simplified
discussion of the design process.
8.2 Typical Application
The application schematic in Figure 8-1 was developed to meet the previous requirements. This circuit is
available as the evaluation module (EVM). The sections provide the design procedure.
Figure 8-1 shows the TPS562201 and TPS562208 4.5-V to 17-V Input, 1.05-V output converter schematics.
C7 0.1 uF
6
1
GND
VOUT = 1.05 V/2A L1
2
VOUT
VBST
R3 10.0 k
5
SW
EN
VIN
VFB
EN
2.2 uH
C9
3
C8
4
VOUT
R1 3.09 k
22 uF 22 uF
R2
10 k
1
C1
C2
C3
C4
Not Installed 1
10 uF 10 uF 0.1 uF
VIN
VIN = 4.5 to 17 V
1
Figure 8-1. TPS562201 and TPS562208 1.05-V/2-A Reference Design
8.2.1 Design Requirements
Table 8-1 shows the design parameters.
Table 8-1. Design Parameters
PARAMETER
Input voltage range
Output voltage
Transient response, 1.5-A load step
12
EXAMPLE VALUE
4.5 to 17 V
1.05 V
ΔVout = ±5%
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating frequency
580 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads, consider using larger value resistors. Too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1 ö
æ
VOUT = 0.768 ´ ç 1 +
÷
R2
è
ø
(2)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
FP =
1
2p LOUT ´ COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces
the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero
frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 3
is located below the high frequency zero but close enough that the phase boost provided be the high frequency
zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended
in Table 8-2.
Table 8-2. Recommended Component Values
L1 (µH)
OUTPUT VOLTAGE
(V)
R1
(kΩ)
R2
(kΩ)
MIN
TYP
MAX
C8 + C9
(µF)
1
3.09
10.0
2.2
2.2
4.7
20 to 68
1.05
3.74
10.0
2.2
2.2
4.7
20 to 68
1.2
5.76
10.0
2.2
2.2
4.7
20 to 68
1.5
9.53
10.0
2.2
2.2
4.7
20 to 68
1.8
13.7
10.0
2.2
2.2
4.7
20 to 68
2.5
22.6
10.0
3.3
3.3
4.7
20 to 68
3.3
33.2
10.0
3.3
3.3
4.7
20 to 68
5
54.9
10.0
3.3
4.7
4.7
20 to 68
6.5
75
10.0
3.3
4.7
4.7
20 to 68
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 580 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
IlP -P =
VIN(MAX) - VOUT
VOUT
´
VIN(MAX)
LO ´ fSW
IlPEAK = IO +
(4)
IlP -P
2
(5)
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ILO(RMS) = IO2 +
1
IlP -P2
12
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(6)
For this design example, the calculated peak current is 3.5 A and the calculated RMS current is 3.01 A. The
inductor used is a WE 744311330 with a peak current rating of 11 A and an RMS current rating of 6.5 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562201 and TPS562208
are intended for use with ceramic or other low-ESR capacitors. Recommended values range from 20 µF to 68
µF. Use Equation 7 to determine the required RMS current rating for the output capacitor.
ICO(RMS) =
VOUT ´ (VIN - VOUT )
12 ´ VIN ´ LO ´ fSW
(7)
For this design, two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS562201 and TPS562208 require an input decoupling capacitor and a bulk capacitor is needed
depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An
additional 0.1-µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering.
The capacitor voltage rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
14
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3.00%
3.00%
2.00%
2.00%
1.00%
1.00%
VOUT (V)
VOUT (V)
8.2.3 Application Curves
0.00%
0.00%
-1.00%
-1.00%
-2.00%
TPS562201
TPS562208
-3.00%
0.0
0.5
1.0
1.5
2.0
TPS562201
-2.00%
TPS562208
-3.00%
0.0
2.5
0.5
1.0
1.5
2.0
2.5
Loading (A)
Loading (A)
C010
Figure 8-3. Load Regulation VIN = 12 V
Figure 8-2. Load Regulation, VIN = 5 V
1.070
1.0
0.9
1.068
0.8
0.7
Efficiency
VOUT (V)
1.066
1.064
1.062
0.6
0.5
0.4
1.060
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 15 V
0.3
TPS562201
1.058
0.2
TPS562208
1.056
4
6
8
10
12
14
Input Voltage (V)
16
18
0.1
0.001
0.010
0.100
I-load (A)
C011
1.000
C015
TPS562201: Iout = 1 A
TPS562208: Iout = 10 mA
Figure 8-4. Line Regulation
Figure 8-5. TPS562201 Efficiency, VOUT = 1.05 V
VIN = 100 mV/div
VO = 50 mV/div
VLX = 5 V/div
VLX = 5 V/div
IO = 2 A/div
IL = 500 mA/div
20 ns/div
800 ns/div
Figure 8-6. TPS562201 Input Voltage Ripple
Figure 8-7. TPS562201 Output Voltage Ripple, IOUT
= 10 mA
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VO = 20 mV/div
VO = 20 mV/div
VLX = 5 V/div
VLX = 5 V/div
IL = 500 mA/div
IL = 500 mA/div
1 µs/div
1 µs/div
Figure 8-8. TPS562201 Output Voltage Ripple, IOUT
= 0.25 A
Figure 8-9. TPS562201 Output Voltage Ripple, IOUT
=2A
V O = 50 mv/div
VOUT = 20 mV/div
SW = 5V/div
800 ns/div
100 µs/div
Figure 8-10. TPS562208 Output Voltage Ripple, IOUT Figure 8-11. TPS562201 Transient Response, 0.1 to
=0A
1.5 A
VOUT = 20 mv/div
VO = 20 mv/div
IOUT = 1 A/div
IO = 1 A/div
100 µs/div
100 µs/div
Figure 8-12. TPS562201 Transient Response, 0.75
to 2.25 A
16
Figure 8-13. TPS562208 Transient Response 0.1 to
2A
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VIN = 5 V/div
VIN = 5 V/div
VEN = 5 V/div
VEN = 5 V/div
VO = 500 mV/div
VO = 500 mV/div
2 ms/div
1 ms/div
Figure 8-14. TPS562201 Start-Up Relative to VI
Figure 8-15. TPS562201 Start-Up Relative to EN
VIN = 5 V/div
VIN = 5 V/div
VEN = 5 V/div
VEN = 5 V/div
VO = 500 mV/div
VO = 500 mV/div
10 ms/div
10 µs/div
Figure 8-16. TPS562201 Shutdown Relative to VI
Figure 8-17. TPS562201 Shutdown Relative to EN
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9 Power Supply Recommendations
The TPS562201 and TPS562208 are designed to operate from input supply voltage in the range of 4.5 V to 17
V. Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 75%. Using that criteria, the minimum recommended input
voltage is VO / 0.75.
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10.The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VOUT
GND
OUTPUT
CAPACITOR
Additional
Vias to the
GND plane
Vias to the
internal SW
node copper
BOOST
CAPACITOR
OUTPUT
INDUCTOR
Vias to the
internal SW
node copper
VIN
GND
VBST
SW
EN
VIN
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
VFB
INPUT BYPAS
CAPACITOR
SW node copper
pour area on internal
or bottom layer
Figure 10-1. TPS562201 and TPS562208 Layout
18
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
D-CAP2™, Eco-mode™, and TI E2E™ are trademarks of Texas Instruments.
Blu-ray™ is a trademark of Blu-ray Disc Association.
WEBENCH® is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS562201DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2201
TPS562201DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2201
TPS562208DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2208
TPS562208DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2208
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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