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TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
TPS6500xx 2.25-MHz Step-Down Converter With Dual Low Dropouts and Supply Voltage
Supervisor
1 Features
3 Description
•
The TPS6500xx devices are single-chip power
management (PWM) ICs for portable applications.
Both devices combine a single step-down converter
with two low-dropout (LDO) regulators. The stepdown converter enters a low-power mode at light load
for maximum efficiency across the widest possible
range of load currents. For low-noise applications, the
devices can be forced into fixed-frequency PWM
through a pin. The step-down converter is small
because of its small inductor and capacitors. The
step-down converter has power good status output
for sequencing. The LDOs can supply 300 mA and
operate with an input voltage range from 1.6 V to 6 V.
A step-down converter or main battery can power the
LDOs directly. The step-down converter and the
LDOs have separate voltage inputs that enable
maximum design and sequencing flexibility.
1
•
•
•
•
Step-Down Converters:
– VIN Range From 2.3 V to 6 V
– Spread Spectrum Clock (SSC) Generation for
Reduced EMI
– 2.25-MHz Fixed Frequency Operation
– 600-mA or 1-A (TPS650061) Output Current
Low Dropouts (LDOs):
– VIN Range From 1.6 V to 6 V
– Adjustable Output Voltage
– Up to 300-mA Output Current
– Separate Power Inputs and Enables
Supply Voltage Supervisor (TPS65001)
– Manual Reset Input for Push Button
– Adjustable Reset Time
– Adjustable Reset Voltage
3-mm × 3-mm 16-Pin WQFN (TPS65000)
3-mm × 3-mm 20-Pin WQFN (TPS65001)
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
•
Points-of-Load
Embedded Processor Power
Cell Phones
Smart Phones
PDAs
Pocket PCs
Portable Media Players
PACKAGE
BODY SIZE (NOM)
TPS65000,
TPS650001,
TPS650003,
TPS650006
WQFN (16)
3.00 mm × 3.00 mm
TPS65001,
TPS650061
WQFN (20)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Circuit
TPS65000/1
Oscillator
SSCG
EN_DCDC
VINDCDC
VIN
10mF
A
P
475kW
VIN
A
0.1mF
470kW
A
VIN
MR
Supply
Voltage
Supervisor
TRST
A
VLDO1
470kW
LDO1
300mA
180kW
A
VLDO2
EN_LDO2
VINLDO2
A
VIN
470kW
PGND
AGND
10mF
180kW
P
VLDO1
1.8V
P
820kW
FB_LDO2
LDO2
300mA
100kW
PG
RST
EN_LDO1
VDCDC
22pF
RST
FB_LDO1
VINLDO1
VDCDC
3.3V
10mF
P
150kW
A
PG
100nF
A
680W
FB_DCDC
MODE
RSTSNS
232kW
2.2mH
SW
Step-Down
600mA
10mF
VLDO2
2.8V
P
A
Bandgap Reference
TPS65000/01 Joint Function/Pin
TPS65001 Only Function/Pin
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
5
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
5
5
5
6
6
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 26
12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
12.2 Layout Example .................................................... 27
13 Device and Documentation Support ................. 28
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
29
14 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2010) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision A (October 2009) to Revision B
•
Page
In the Ordering Information Table, changed the SVS column From: Included To: N/A for devices TPS650001,
TPS650003, TPS650006 ....................................................................................................................................................... 3
Changes from Original (June 2009) to Revision A
Page
•
Added device numbers TPA650001, TPS650003, TPS650006 and TPA650061 to the data sheet. .................................... 1
•
Changed the PG pin connection From: VDCDC To: VIN in the application circuit. ................................................................ 1
•
Changed resistor values for VLDO1 and VLDO2 in the application circuit. ........................................................................... 1
•
Changed the configuration of the PG and RST pins in the application circuit ....................................................................... 1
•
Added Note 2: to the Electrical Characteristics table. ............................................................................................................ 6
•
Changed Figure 1 title From: EFFICIENCY (DCDC PFM Mode) To: EFFICIENCY (DCDC 600mA PFM Mode)................. 9
•
Changed Figure 2 title From: EFFICIENCY (DCDC PFM Mode) To: EFFICIENCY (DCDC 600mA PFM Mode)................. 9
•
Added Figure 3, EFFICIENCY (DCDC PWM Mode).............................................................................................................. 9
•
Added Figure 4, EFFICIENCY (DCDC PWM Mode).............................................................................................................. 9
•
Changed the configuration of the PG pin in Figure 24 ........................................................................................................ 20
•
Changed the PG pin connection From: VDCDC To: VIN in Figure 31.................................................................................. 24
•
Changed the configuration of the PG and RST pins in Figure 31 ....................................................................................... 24
•
Added Figure 32, Typical TPS650001 Application Schematic ............................................................................................. 25
•
Added Figure 33, Typical TPS650061 Application Schematic ............................................................................................. 26
2
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Product Folder Links: TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061
TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
www.ti.com
SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
5 Description (continued)
The TPS65001 extends functionality by adding a supply voltage supervisor (SVS). To maximize the flexibility of
the SVS, the reset voltage is set with two external resistors and the reset time is set by a small external
capacitor. For external control, the SVS can use its active-low manual reset input to connect to a push button.
The TPS65000 is available in a 16-pin leadless package (3 mm × 3 mm QFN). The TPS65001 is available in a
20-pin leadless package (3 mm × 3 mm QFN).
6 Device Options
PART NUMBER (1) (2)
TPS65000
TPS65001
(1)
(2)
OPTIONS
SVS
SSC
LDO voltages externally adjustable DC-DC
converters 600 mA, VOUT externally adjustable
N/A
Included
Included
Included
TPS650001
LDO1 = 1.8 V fixed,
LDO2 = 2.8 V fixed,
DC-DC Converter 600 MA, DCDC VOUT = 1.2 V
fixed
N/A
Included
TPS650003
LDO1 = 3.3 V fixed,
LDO2 = 1.8 V fixed,
DC-DC Converter 600 MA, DCDC VOUT = 1.5 V
fixed
N/A
Included
TPS650006
LDO1 = 1.8 V fixed,
LDO2 = 3.3 V fixed,
DC-DC Converter 600 MA, DCDC VOUT = 1.2 V
fixed
N/A
Included
TPS650061
LDO1 = 3.3 V fixed,
LDO2 = 1.8 V fixed,
DC-DC Converter 1 A, VOUT externally adjustable
Included
Included
TPS650001, TPS650003, and TPS650006 are spin versions of TPS65000. TPS650061 is a spin version of TPS65001. Different DC-DC
current limits and fixed voltage outputs of the DC-DC and LDOs are available. Please contact your TI sales representative for further
information.
For the most current package and ordering information, see the Mechanical, Packaging, and Orderable Information at the end of this
document, or see the TI website at www.ti.com.
Copyright © 2009–2015, Texas Instruments Incorporated
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TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
www.ti.com
7 Pin Configuration and Functions
VINLDO1
14
VLDO1
13
FB_LDO1
RSTSNS
VINLDO2
VLDO2
FB_LDO2
19
18
17
16
VINLDO1
13
RST
FB_LDO2
14
20
3
EN_LDO2
4
12
AGND
PG
5
11
FB_DCDC
10
FB_DCDC
15
EN_LDO1
EN_DCDC
9
Exposed
Thermal Pad
9
AGND
2
MODE
10
TRST
8
FB_LDO1
1
VINDCDC
11
MR
7
VLDO1
SW
12
6
VLDO2
15
RUK Package
20-Pin WQFN With Exposed Thermal Pad
Top View
PGND
VINLDO2
8
4
EN_DCDC
PGND
7
3
MODE
PG
Exposed
Thermal Pad
6
2
VINDCDC
EN_LDO2
5
1
SW
EN_LDO1
16
RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions
PIN
NAME
I/O
DESCRIPTION
16-PIN RTE
20-PIN RUK
AGND
10
12
—
EN_DCDC
8
10
I
Enable DC-DC converter
EN_LDO1
1
3
I
Enable LDO1
EN_LDO2
2
4
I
Enable LDO2
FB_DCDC
9
11
I
Voltage to DC-DC error amplifier
FB_LDO1
11
13
I
Voltage to LDO1 error amplifier
FB_LDO2
14
16
I
Voltage to LDO2 error amplifier
MODE
7
9
I
Selects force PWM or PWM/PFM automatic-transition mode
MR
—
1
I
Active-low input to force a reset.
PG
3
5
O
Open-drain active low power good output.
Analog ground - Start back to PGND as close to the IC as possible.
(1)
PGND
4
6
—
Power ground – Connected to the thermal pad
RST
—
20
O
Open-drain active low reset output
RSTSNS
—
19
I
Voltage for RST generation
SW
5
7
O
Switch pin – connect inductor here
TRST
—
2
I/O
Capacitor connection for setting reset time
VINDCDC
6
8
I
Input voltage to DC-DC converter and all other control blocks
VINLDO1
13
15
I
Input voltage to LDO1
VINLDO2
16
18
I
Input voltage to LDO2
VLDO1
12
14
O
LDO1 output voltage
VLDO2
15
17
O
LDO2 output voltage
(1)
4
External pull up on MR is required.
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Product Folder Links: TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061
TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
www.ti.com
SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage range
Output voltage range
Current
MIN
MAX
On all pins except AGND, PGND, EN_DCDC, VLDO1, VLDO2, FB_LDO1,
FB_LDO2, FB_DCDC pins with respect to AGND
–0.3
7
On EN_DCDC with respect to AGND
–0.3
VIN + 0.3,
≤7
On VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC
–0.3
V
3.6
V
VINDCDC, SW, PGND,
1800
mA
VINLDO1/2, VLDO1/2, AGND
800
mA
1
mA
At all other pins
Continuous total power dissipation
See Dissipation Ratings
Operating free-air temperature, TA
–40
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
UNIT
–65
85
°C
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±2000
Machine model (MM)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
L1
CI
CO
SW pin inductor
MIN
NOM
MAX
1.5
2.2
3.3
Input capacitor at VINDCDC
10
Input capacitor at VINLDO1/2
2.2
Output capacitor for DCDC
10
Output capacitor for LDO1/2
2.2
μF
22
DC-DC converter output current (TPS650061 ONLY)
LDO1 output current
Operating ambient temperature
Copyright © 2009–2015, Texas Instruments Incorporated
μF
μF
LDO2 output current
TA
μH
μF
DC-DC converter output current
IO
UNIT
–40
600
mA
1000
mA
300
mA
300
mA
85
°C
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5
TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
www.ti.com
8.4 Thermal Information
TPS6500x
THERMAL METRIC (1)
RTE (WQFN)
RUK (WQFN)
16 PINS
20 PINS
UNIT
46.2
°C/W
RθJA
Junction-to-ambient thermal resistance
44.7
RθJC(top)
Junction-to-case (top) thermal resistance
41.7
51
°C/W
RθJB
Junction-to-board thermal resistance
16
17.8
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.7
°C/W
ψJB
Junction-to-board characterization parameter
16
17.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.4
4.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF, (see the
Typical Application section).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
Input voltage for VINDCDC of DCDC converter
VIN
6
See
(1)
1.6
6
Input voltage for LDO2 (VINLDO2)
See
(1)
1.6
6
Internal undervoltage lockout
threshold
VCC falling
Input voltage for LDO1 (VINLDO1)
UVLO
2.3
1.72
Internal undervoltage lockout
hysteresis
1.77
V
1.82
160
V
mV
SUPPLY CURRENT TPS65000
IQ
Operating quiescent current
MODE low, EN_DCDC high,
EN_LDO1/2 low,
IOUT = 0 mA and no switching
23
MODE low, EN_DCDC low,
EN_LDO1/2 high, IOUT = 0 mA
IOUT = 0 mA and no switching (2)
50
μA
EN_DCDC high, MODE high,
EN_LDO1/2 low, IOUT = 0 mA
ISD
Shutdown Current
32
57
4
mA
0.16
2.2
μA
MODE low, EN_DCDC high,
EN_LDO1/2 low,
IOUT = 0 mA and no switching
24
37
μA
MODE low, EN_DCDC low,
EN_LDO1/2 high, IOUT = 0 mA
IOUT = 0 mA and no switching (2)
55
62
μA
EN_DCDC low EN_LDO1 and EN_LDO2 low
SUPPLY CURRENT TPS65001
IQ
Operating quiescent current
EN_DCDC high, MODE high,
EN_LDO1/2 low, IOUT = 0 mA
ISD
(1)
(2)
6
Shutdown Current
4
EN_DCDC low EN_LDO1 and EN_LDO2 low
11
mA
17
μA
The design principle lets only VINDCDC be the highest supply in the system if different voltage input supplies separately to DC-DC
converter and LDOs, meaning VINDCDC ≥ VINLDO1, VINDCDC ≥ VINLDO2.
The max quiescent current of enabling LDOs is 8 μA higher for TPS650001, TPS650003, TPS650006, and TPS650061.
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TPS650003, TPS650006, TPS650061
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SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
Electrical Characteristics (continued)
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF, (see the
Typical Application section).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG, MR, RST)
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Low-level output voltage
PG and RST pins only, IO = -100 μA
Input leakage current
MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to
GND or VINDCDC
Ilkg
1.2
V
0.4
V
0.4
V
0.01
0.1
μA
2.25
2.847
240
480
185
380
OSCILLATOR
fSW
Oscillator frequency
1.722
MHz
STEP DOWN CONVERTER POWER SWITCH
RDS(on)
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
VINDCDC = VGS = 3.6 V
2.3 V ≤ VINDCDC ≤ 2.5 V
300
2.5 V ≤ VINDCDC ≤ 6 V
600
mΩ
IO
DC-output current
IO
DC-output current (TPS650061
ONLY)
2.7 V ≤ VINDCDC ≤ 6 V
ILIMF
Forward current limit PMOS and
NMOS
2.3 V ≤ VINDCDC ≤ 6 V
800
1000
1400
mA
ILIMF
Forward current limit PMOS and
NMOS (TPS650061 ONLY)
2.7 V ≤ VINDCDC ≤ 6 V
1200
1500
1680
mA
Thermal shutdown
Increasing junction temperature
150
Thermal shutdown hysteresis
Decreasing junction temperature
30
TSD
1000
mA
mA
°C
STEP DOWN CONVERTER OUTPUT VOLTAGE
VDCDC
Adjustable output voltage range,
DCDC
0.6
VINDCDC
V
0.1
μA
0.594
0.6
0.606
V
–1.5%
0%
1.5%
FB_DCDC pin current
Vref
Internal reference voltage
VDCDC
RDIS
Output Voltage Accuracy (PWM
Mode) (3)
MODE = high,
2.3 ≤ VINDCDC ≤ 6 V
Output Voltage Accuracy (PFM
mode) (4)
MODE low
1% voltage positioning active
Load regulation (PWM mode)
MODE high
Internal discharge resistance at
SW
EN_DCDC low
1%
0.5%
A
450
Ω
LOW DROP OUT REGULATORS
VI
Input voltage for LDOx (VINLDOx)
VO
Adjustable output voltage, LDOx
(VLDOx) (5)
IO
Continuous Pass FET Current
ISC
Short circuit current limit
1.6
6
V
0.73
VINLDOx – VDO
V
300
2.3 V ≤ VINLDOx
340
700
VINLDOx < 2.3V
210
700
VDO
(3)
(4)
(5)
(6)
Dropout Voltage
(6)
mA
0.1
μA
VINLDOx ≥ 2.3 V, IOUT = 250 mA
370
mV
VINLDOx < 2.3V IOUT = 175 mA
370
mV
FB_LDOx pin current
FB_LDOx voltage
mA
Adjustable VOUT mode only
0.5
V
For VINDCDC = VDCDC + 1 V
In PFM Mode, the internal reference voltage is typ 1.01 × VREF.
Maximum output voltage VLDOx = 3.6 V.
VDO = VINLDOx – VLDOx where VINLDOx = VLDOx (nominal) – 100 mV
Copyright © 2009–2015, Texas Instruments Incorporated
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SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
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Electrical Characteristics (continued)
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF, (see the
Typical Application section).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW DROP OUT REGULATORS (continued)
IO = 1 mA to 300 mA, VINLDOx = 2.3 V – 6 V,
VLDOx = 1.2 V
–3.5%
3.5%
IO = 1mA to 175 mA VINLDOx = 1.6 V – 6 V,
VLDOx = 1.2 V
–3.5%
3.5%
Load regulation
IO = 1mA to 300 mA VINLDOx = 3.6 V
VLDOx = 1.2 V
–1.5%
1.5%
Line regulation
VINLDOx = 1.6 V – 6 V VLDOx = 1.2 V at
IO = 1 mA
–0.5%
0.5%
PSRR
Power Supply Rejection Ratio
fNOISE ≤ 10 kHz, COUT ≥ 2.2 μF, VIN = 2.3 V,
VOUT = 1.3 V IOUT = 10 mA
RDIS
Internal discharge resistance at
VLDOx
TSD
Output Voltage Accuracy
(7)
40
dB
EN_LDOx low
450
Ω
Thermal shutdown
Increasing temperature
150
°C
Thermal shutdown hysteresis
Decreasing temperature
30
°C
SUPPLY VOLTAGE SUPERVISOR
VIN
Input voltage for RSTSNS pin
0
6
t MRDEGLITCH MR Deglitch time
1
VIH
Input high voltage
MR pin only
1.2
VIL
Input low voltage
MR pin only
0
Ilkg
High-input leakage current
RST pin
VOL
Output low voltage
RST pin only, IO = –100 μA
ITRST
Reset timer capacitor current
(7)
6
0.01
Voltage rising (Reset time begins)
Reset voltage trip hysteresis
Voltage falling (RST pulled low)
0.58
V
0.4
V
0.1
μA
0.4
V
2
2.2
μA
0.6
0.63
V
1.6
Reset voltage trip voltage
V
ms
–5%
Output voltage specification does not include tolerance of external programming resistors.
8.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STEP DOWN CONVERTER OUTPUT VOLTAGE
tStart
Start-up time
EN_DCDC to start of switching
(10%)
250
tRamp
VDCDC ramp-up time
VDCDC ramp from 10% to 90%
250
μs
VLDOx ramp from 10% to 90%
200
μs
μs
LOW DROP OUT REGULATORS
tRAMP
VLDOx Ramp Time
8.7 Dissipation Ratings
DEVICE
TPS65000/01 (1)
TPS65000/01 (2)
(1)
(2)
8
PACKAGE
RTE/RUK
TA ≤ 25°C
TA = 70°C
TA = 85°C
POWER RATING POWER RATING POWER RATING
RθJA
RθJB
270°C/W
14°C/W
370 mW
204 mW
148 mW
48.7°C/W
14°C/W
2.05 W
1.13 W
821 mW
The JEDEC low-K (1s) board used to derive this data was a 3 in × 3 in, two-layer board with 2-oz copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3 in × 3 in, multilayer board with 1-oz internal power and ground.
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8.8 Typical Characteristics
100
90
100
VOUT = 1.2V
o
TA = 25 C
90
VOUT = 1.2V
o
TA = 25 C
4.2V
80
80
3.6V
3.3V
70
6V
2.8V
Efficiency - %
Efficiency - %
70
5.5V
60
5V
2.3V
50
4.5V
4.2V
40
3.3V
60
6V
2.8V
50
5.5V
2.3V
40
3.6V
30
30
20
20
10
10
0
0.00001
0.0001
0.001
0.01
0.1
5V
4.5V
0
0.00001
1
IO - Output Current - A
0.001
0.01
0.1
1
IO - Output Current - A
Figure 1. Efficiency (DC-DC 600-mA PFM Mode) vs Output
Current
Figure 2. Efficiency (DC-DC 600-mA PWM Mode) vs Output
Current
100
100
90
0.0001
VOUT = 1.2V
o
TA = 25 C
90
80
VOUT = 1.2V
o
TA = 25 C
80
4.5V
2.8V
5V
2.7V
5.5V
70
6V
4.5V
60
Efficiency - %
Efficiency - %
70
4.2V
50
3.6V
40
4.2V
6V
60
3.6V
50
5.5V
3.3V
5V
40
2.8V
3.3V
30
30
2.7V
20
20
10
10
0
0.00001
0.0001
0.001
0.01
0.1
1
0
0.00001
0.01
0.1
1
Figure 4. Efficiency (DC-DC 1 A TPS650061 Only, PWM
Mode) vs Output Current
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Load Current = 60mA
EN_DCDC = high
EN_LDO1 = low
EN_LDO2 = low
Ch4: Load Current
DCDC
20mAdiv
Ch2: SW
2V/div
Ch1: VDCDC
10mV/div
Ch2: SW
2V/div
Ch3: Load Current
DCDC
20mAdiv
0.001
Ch1: VDCDC
10mV/div
Figure 3. Efficiency (DC-DC 1A TPS650061 Only, PFM Mode)
vs Output Current
0.0001
IO - Output Current - A
IO - Output Current - A
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Load DCDC = 400mA
EN_DCDC = high
EN_LDO1 = low
EN_LDO2 = low
t - Time - 2ms/div
t - Time - 200ns/div
Figure 5. Output Voltage Ripple (DC-DC PFM Mode)
Figure 6. Output Voltage Ripple (DC-DC PWM Mode)
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Ch1: EN_LDOx
500mV/div
VINDCDC = 3.6 V
VINLDOx = 2.3V
TA = 25oC
VLDOx = 1.2 V
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Ch3: VLDOx
500mV/div
Ch3: SW
20V/div
Ch2: VDCDC Ch1: EN_DCDC
500mV/div
2V/div
Ch1: VINLDOx
1V/div
Typical Characteristics (continued)
Load DCDC = 100mA
EN_DCDC = 0V to 3.6V
EN_LDO1 = low
EN_LDO2 = low
Load LDOx = 100mA
EN_LDOx = 0V to 2.3V
EN_DCDC = low
t - Time - 100ns/div
t - Time - 100ns/div
Figure 7. Startup Timing (DC-DC)
Figure 8. Start-Up Timing (LDOx)
50
20
18
TA = 85oC
40
TA = 25oC
16
Quiescent Current - mA
Quiescent Current - mA
o
30
20
o
TA = -40 C
VOUT = 1.8V
EN_DCDC = VIN
Mode = GND
IO =0 mA
Measure time = 2 s
EN_LDOx = GND
10
TA = 85 C
12
10
2.5
3
3.5
4
4.5
5
5.5
8
VOUT = 1.2V
EN_DCDC = GND
EN_LDOx = VIN
IO = 0mA
Measure time = 2 s
6
4
2
0
2
TA = -40oC
TA = 25oC
14
0
1.6
6
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
VI - Input Voltage - V
VI - Input Voltage - V
Figure 9. TPS650001 Quiescent Current (DC-DC PFM Mode)
vs Input Voltage
Figure 10. TPS650001 Quiescent Current (LDOx) vs Input
Voltage
TA = 25oC
o
VINDCDC = 3.6V
o
TA = 25 C
DCDC Load Current = 30mA
VDCDC = 1.8V
Ch2: VDCDC
20mV/div
TA = 85 C
10
TA = -40oC
VOUT = 1.8V
EN_DCDC = GND
Mode = GND
IO = 0mA
Measure time = 2 s
EN_LDOx = GND
Ch3: SW
2V/div
Quiescent Current - mA
Ch1: Mode
2V/div
20
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VI - Input Voltage - V
Figure 11. TPS650001 Shutdown Current vs Input Voltage
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t - Time - 4ms/div
Figure 12. PFM to PWM Transition (DC-DC)
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100
VINDCDC = 3.6V
o
TA = 25 C
DCDC Load Current = 30mA
VDCDC = 1.8V
VIN = 2.3V
VLDOx = 1.3V
CI = 2.2mF
CO = 10mF
90
Rejection Ratio - dB
80
Ch3: SW
2V/div
Ch2: VDCDC
20mV/div
Ch1: Mode
2V/div
Typical Characteristics (continued)
70
60
50
40
IO = 10mA
30
20
10
0
10
t - Time - 4ms/div
Figure 13. PWM to PFM Transition (DC-DC)
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100
1k
10k
100k
1M
10M
f - Frequency - MHz
Figure 14. Power Supply Rejection Ratio (LDOx) vs
Frequency
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9 Detailed Description
9.1 Overview
The TPS6500x provides one step-down converter, two low dropout regulators, spread spectrum clock
generation, and a supply voltage supervisor for the TPS65001 only. The device has an input voltage range of
2.3 V to 6 V and is characterized across a –40°C to 85°C range. This device is intended, but not limited, to
powering smart phones, embedded processors, and point-of-load devices.
The output voltage of the step-down converter can be selected through resistor networks on the output. To
maximize efficiency, there are two modes of operation based on load conditions: PWM or PFM. By pulling the
MODE pin high, forced PWM can be achieved. Pulling this pin low results in an automatic adjustment between
PFM and PWM modes.
The two general purpose low drop-out regulators each have their own separate enables and voltage inputs. The
inputs can be tied to the output of the step-down converter or to a separate voltage source. Resistor networks
are required on the output of the regulator to set the output voltage. Their wide voltage range lets them handle
direct connections to a battery.
The switching frequency of the step-down converter is handled by the oscillator, with a typical frequency of
2.25 MHz. The spread spectrum clock (SSC) modulates this frequency when the device is in PWM mode. This
additional circuit in the oscillator block reduces power that may cause EMI.
The TPS6500x devices also provide a power good signal to monitor the condition of the DC-DC and both LDOs.
The DC-DC and LDOs are only monitored if their enable signal is high. If all enabled resources are in regulation,
the pin is pulled low. If one or more of the enabled resources are out of regulation, the pin is pulled in Hi-Z.
The supply voltage supervisor is only available for the TPS65001 and TPS650061 devices. This circuit monitors
the supply voltage to the device that the TPS65001 and TPS650061 is powering for under voltage conditions.
The circuit can connect to a button for manual resets. Reset-recovery time can also be set. Four different
scenarios can trigger the circuit to cause a rest.
12
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9.2 Functional Block Diagram
2
3 x 3 mm QFN
TPS65000/TPS65001
Oscillator
SSCG
VINDCDC
EN_DCDC
MODE
SW
FB_DCDC
PG
Buck Converter
600mA
Supply
Voltage
Supervisor
MR
RSTSNS
VINLDO1
EN_LDO1
TRST
RST
VLDO1
FB_LDO1
LDO1
300mA
PGND
VINLDO2
EN_LDO2
VLDO2
FB_LDO2
LDO2
300mA
AGND
Bandgap Reference
Joint Function/Pin
TPS65001 Only Function/Pin
9.3 Feature Description
9.3.1 Step-Down Converter
TI intends the step-down converter to maximize the flexibility in the equipment. The output voltage is selectable
with a resistor network on the output. Figure 15 shows the required connections.
L
VINDCDC
SW
EN_DCDC
MODE
P
Switch Control
DISCHG
CF
RDC1
FB_DCDC
θJA Diode
+
Oscillator
CO
RDC2
-
ZLOAD
P
A
P
VREF(DCDC)
AGND
PGND
A
P
Figure 15. DCDC Block Diagram and Output Voltage Setting
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Feature Description (continued)
The output voltage of the DC-DC converter is set by Equation 1:
+ RDC2 )
(R
VDCDC = VFB_DCDC x DC1
RDC2
VDCDC = 0.6V x
(RDC1 + RDC2 )
RDC2
(1)
The combined resistance of RDC1 and RDC2 should be less than 1 MΩ.
Fixed output voltages and additional current limit options are also possible. Contact TI for further information.
The step-down converter has two modes of operation to maximize efficiency at different load conditions. At
moderate to heavy load currents, the device operates in a fixed-frequency pulse width modulation (PWM) mode
that results in small output ripple and high efficiency. Pulling the MODE pin to a DC-high level results in PWM
mode over the load range.
At light-load currents, the device operates in a pulsed-frequency modulation (PFM) mode to improve efficiency.
The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating
discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from its nominally set
value. TI intends this voltage positioning to minimize the voltage undershoot of a load step from light to heavy
loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load throw-off.
Figure 16 shows the voltage positioning behavior for a light to heavy load step.
Output voltage
VOUT(nom) + 1%
Light load
PFM Mode
VOUT(nom)
moderate to heavy load
PWM Mode
Time
Figure 16. PFM Voltage Positioning
Pulling the MODE pin to DC ground results in an automatic transition between PFM and PWM modes to
maximize efficiency.
The DC-DC converter output automatically discharges to ground through an internal 450-Ω load when EN_DCDC
goes low or when the UVLO condition is met.
9.3.2 Soft Start
The step-down converter has an internal soft start circuit that limits the inrush current during start-up. During a
soft start, the output voltage ramp up is controlled as Figure 17 shows.
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Feature Description (continued)
EN
90%
10%
VOUT
tRAMP
tStart
Figure 17. Soft Start
9.3.3 Linear Regulators
TI designed the two linear drop-out regulators (LDOs) in the TPS65000 and TPS65001 to provide flexibility in
system design. Each LDO has a separate voltage input and enable signal. The input can be tied to the output of
the step-down converter or the output of another voltage source. Each LDO output discharge to ground
automatically when EN_LDOx goes low.
A resistor network is required to set the output voltage of the LDOs. Fixed-voltage output versions are also
available. Contact TI sales representative for more information.
The LDOs are general-purpose devices that can handle inputs from 6 V to 1.6 V, making them suitable for
directly connecting to the battery. Figure 18 illustrates the connections for LDO1. The same architecture applies
to LDO2.
VLDO1
VINLDO1
RLDO1_1
θJA Diode
DISCHG
+
EN_LDO1
CO(LD01)
FB_LDO1
ZLOAD
VREF(LD01)
RLOD1_2
AGND
PGND
A
P
P
A
Figure 18. LDO Block Diagram and Output Voltage Setting
The output voltages of the LDOs are set by Equation 2:
VLDO1 = VFB_LDO1 x
VLDO1 = 0.5V x
(RLDO1_1 + RLDO1_2 )
RLDO1_2
(RLDO1_1 + RLDO1_2 )
RLDO1_2
(2)
The combined resistance of RLDO1_1 and RLDO1_2 should be less than 1 MΩ.
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Feature Description (continued)
9.3.4 Oscillator and Spread Spectrum Clock Generation
The TPS6500x contains an internal oscillator running at a typical frequency of 2.25 MHz. This frequency is the
fundamental switching frequency of the step-down converter when running in PWM mode. An additional circuit in
the oscillator block implements spread spectrum clocking, which modulates the main-switching frequency when
the device is in PWM mode. This spread spectrum oscillation reduces the power that may cause EMI. When
viewed in the frequency domain, the SSC spreads out the frequency that may introduce interference while
simultaneously reducing the power. Because the frequency is continually shifting, the amount of time the
switcher spends at any single frequency is reduced. This reduction in time indicates that the receiver that may
sense the interference has less time to integrate the interference.
Different spin versions of SSC settings are also feasible. Contact a TI sales representative for more information.
70
70
RBW = 10 kHz
RBW = 10 kHz
60
60
50
50
40
40
30
30
dBmV
dBmV
SSC
ON
20
20
10
10
0
0
-10
-10
-20
-20
-30
Start 1.5 MHz
Stop 150 MHz
Figure 19. SSC On/Off Comparison from 1.5 MHz to 150
MHz
SSC
OFF
-30
Start 1.5 MHz
Stop 3.5 MHz
Figure 20. Zoom In of SSC On/Off Comparison from 1.5
MHz to 3.5 MHz
Figure 19 to Figure 20 shows the advantage of SSC with the frequency spectrum centering on the nominal
frequency 2.25 MHz. The blue spectrum is the result of the spread change. The figures show the harmonic
spectrum is attenuated 10 dB comparing to the same device without SSC.
9.3.5 Power Good
The open drain PG output indicates the condition of the step-down converter and each LDO. This output is
combined, with the outputs being compared when the appropriate enable signal is high. The pin is pulled low
when all enabled outputs are greater than 90% of the target voltage and Hi-Z when an enabled output is less
than 90% of its intended value or when all the enable signals are pulled low.
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Feature Description (continued)
EN_DCDC
EN_LDO1
EN_LDO2
VDCDC
VDCDC
PG
+
VDCDC
Target
A
VLDO1
+
VLDO1
Target
-
VLDO2
+
VLDO2
Target
-
Figure 21. Power Good Functionality
9.3.6 Supply Voltage Supervisor (SVS) [TPS65001 and TPS650061 Only]
The SVS has fourinputs and one output. The RST pin is an active-low high-impedance output. The MR pin is an
active-low input that suitable for connecting to a push-button circuit for manual reset generation. The RSTSNS
pin is an analog-input pin for voltage comparison. The TRST pin is connected to an external capacitor, allowing
the reset timing to be set in the application. The VINDCDC pin is the main-supply input for the control circuits
and the switch-mode converter.
VIN
RS1
CS4
RSTSNS
A
VRESET
RS2
CS2
A
0.6V
Reference
A
RS4
RST
VINDCDC
Reset
Logic and
Timing
MR
VIN
TRST
RS3
A
AGND
A
A
Figure 22. SVS Block Diagram
Each input can individually trigger RST to go active. Table 1 outlines the paths to activate the reset.
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Feature Description (continued)
Table 1. RST Generation Table
INPUTS
OUTPUTS
VINDCDC
MR
VRSTSNS
RST
0.4 < V < UVLO
X
X
Low
> UVLO
≥ VIH(MR)
≤ 0.6 V
Low
> UVLO
≥ VIH(MR)
> 0.6 V
High-Z
> UVLO
< VIL(MR)
X
Low
The RSTSNS pin must be tied to VINDCDC if the reset functionality is not required from this pin. This action
causes the reset to activate only when VINDCDC is rising from 0 V or when VINDCDC drops below UVLO. The
RSTSNS pin must connect to an external RC network to set the deglitch timing for triggering a reset when
VINDCDC is below the UVLO threshold. The reset threshold voltage is given by Equation 3:
(RS2 + RS1)
VRST = 0.6V x
RS2
(3)
The RST recovery timing is set by the capacitor on the TRST pin. A 2-μA current is enabled when the reset
condition is met, charging the capacitor. The TRST voltage is monitored internally and the reset ends when the
voltage reaches 0.6 V. The capacitor value to reset time can be computed with Equation 4:
C
tRST = 0.6V x
2 x 10-6 A
(4)
The value tRST is the time from the end of condition that activated RST until RST returns to its Hi-Z state. The
TRST pin would be internally discharged to ground when the reset condition is true or after tRST.
1
Reset Trigger
0
2 mA
ITRST
0
0.6V
VTRST
GND
Hi-Z
RST
GND
tRST
tRST
Figure 23. RST Recovery Timing
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9.4 Device Functional Modes
The step-down converter has two modes of operation to maximize efficiency:
PFM
• For light loads
• For automatic transition to between this mode and PWM mode automatically when MODE pin is pulled low
over all load ranges
• To increase in output voltage setting by 1%
• For better accuracy
PWM
• For moderate to heavy loads
• For a small output ripple
• For pulling MODE pin high to result in PWM mode over all load range
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI-component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS65000 device is designed to pair with various applications, such as embedded processor power and
portable media players. For detailed information on using the TPS65000 with TMS32C2834x, see Related
Documentation.
TI designed the TPS65001 device to pair with various applications, such as PDAs and pocket PCs. For detailed
information on using the TPS65001 with TMS320C5504/05, see Related Documentation.
TI designed the TPS650001 and TPS650061 devices to pair with various applications, such as cell and smart
phones, as well as point-of-load. For detailed information on using the TPS650001 and TPS650061 with OMAPL13x, see Related Documentation.
10.2 Typical Application
10.2.1 Typical TPS65000 Application
TPS65000
VIN
10mF
P
A
EN_DCDC
VINDCDC
MODE
2.2mH
SW
VDCDC
3.3V
680kW
10mF
P
FB_DCDC
150kW
A
22pF
470kW
VIN
PG
VLDO1
FB_LDO1
470kW
10mF
180kW
EN_LDO1
VDCDC
P
A
EN_LDO2
VINLDO1
VLDO2
FB_LDO2
PGND
AGND
VLDO2
2.8V
820kW
10mF
P
VINLDO2
A
VLDO1
1.8V
P
180kW
A
Figure 24. Typical TPS65000 Application Schematic
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
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RESOURCES
VOLTAGE
SW
3.3 V
VLDO1
1.8 V
VLDO2
2.8 V
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)
10.2.1.2.1.1 Inductor Selection
The typical value for the converter inductor is 2.2-μH output inductor. Larger or smaller inductor values in the
range of 1.5 μH to 3.3 μH can optimize the performance of the device for specific operation conditions. The
selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the
inductance influences the efficiency of the converter directly. An inductor with lowest DC resistance must be
selected for highest efficiency. See SLVA157 for more information on inductor selection.
Equation 5 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 6. TI
recommends this because during heavy load transient the inductor current rises above the calculated value.
V
1 - OUT
VIN
DIL = VOUT x
Lxf
where
•
•
•
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak to Peak Inductor Ripple Current
ILmax = IOUTmax
(5)
DI
+ L
2
where
•
ILmax = Maximum Inductor Current
(6)
The highest inductor current occurs at maximum VIN.
Open-core inductors have a soft saturation characteristic and can usually handle higher inductor currents versus
a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consider that the core material from inductor to inductor differs and impacts the
efficiency especially at high-switching frequencies.
The step down converter has internal loop compensation. TI designed the internal loop compensation to work
with a certain output filter corner frequency calculated as follows:
1
fC =
with L = 2.2mH, COUT = 10mF
2p L x COUT
(7)
The selection of external L-C filter must be coped with Equation 7. The product of L × COUT must be constant
while selecting smaller inductor or increasing output capacitor value.
See Table 3 and the typical applications for possible inductors.
Table 3. Inductors
INDUCTOR TYPE
INDUCTANCE (μH)
SUPPLIER
MAX DIMENSIONS (mm)
MIPS2520D2R2
2.0
FDK
2.5 × 2.0 × 1.0
MIPSA2520D2R2
2.0
FDK
2.5 × 2.0 × 1.2
KSLI-252010AG2R2
2.2
Htachi Metals
2.5 × 2.0 × 1.0
LQM2HPN2R2MJ0L
2.2
Murata
2.5 × 2.0 × 1.2
LPS15222
2.2
Coilcraft
3.0 × 3.0 × 1.5
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10.2.1.2.1.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the converter allows the use of small ceramic
capacitors with a typical value of 22 μF, without having large output voltage under and overshoots during heavy
load transients. TI recommends ceramic capacitors with low ESR values because they result in lowest output
voltage ripple. See the TI-recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. The RMS ripple current is calculated as the following:
V
1 - OUT
VIN
1
IRMSCout = VOUT x
x
Lxf
2x 3
(8)
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor:
V
1 - OUT
æ
ö
VIN
1
DVOUT = VOUT x
x ççç
+ ESR÷÷÷
Lx f
èç 8 x COUT x f
ø÷
(9)
Where the highest output voltage ripple occurs at the highest input voltage VIN.
At light load currents, the converter operates in power save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
The adjustable output voltage of the DC-DC converter is calculated by Equation 1 in the Step-Down Converter.
To keep the external resistor divider network robust against noise, an external feed forward capacitor is required
for optimum load transient response. The value of feed forward capacitor must be in the range between 22 pF
and 33 pF provided the equivalent resistance of RDC1 || RDC2 in Equation 1 is approximately 300 kΩ. Scale
change on RDC1||RDC2 would apply a scale change to the feed forward capacitor to keep the RC product a
constant.
10.2.1.2.1.3 Input Capacitor Selection
Due to the DC-DC converter having a pulsating input current, a low-ESR input capacitor is required for best input
voltage filtering, and minimizing the interference with other circuits caused by high-input voltage spikes. Put the
input capacitor as close to the VINDCDC pin as close as possible with the clean GND connection. Do the same
for the output capacitor and the inductor. The converters require a ceramic input capacitor of 10 μF. The input
capacitor can increase without any limit for better input voltage filtering.
Table 4. Capacitors
22
CAPACITANCE
SUPPLIER
TYPE
22 μF
TDK C2012X5R0J226MT
Ceramic
22 μF
Taiyo Yuden JMK212BJ226MG
Ceramic
10 μF
Taiyo Yuden JMK212BJ106M
Ceramic
10 μF
TDK C2012X5R0J106M
Ceramic
10 μF
Murata GRM188R60J106M69D
Ceramic
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SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = GND
VINDCDC = 3.6 V to 4.2V to 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = VINDCDC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
VINDCDC = 3.6 V to 4.2V to 3.6V
TA = 25oC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
10.2.1.3 Application Curves
Figure 25. Line Transient Response (DC-DC PFM Mode)
Figure 26. Line Transient Response (DC-DC PWM Mode)
Ch2: DCDC Load Current
200mA/div
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = GND
t - Time - 100ms/div
Figure 28. Load Transient Response (DC-DC PFM Mode)
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
Ch1: LDOx Load Current
50mA/div
t - Time - 100ms/div
Figure 27. Line Transient Response (LDOx)
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
Ch2: VLDOx
20mV/div
Ch2: VLDOx
20mV/div
Ch1: VDCDC
50mV/div
Ch2: DCDC Load Current
200mA/div
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
o
TA = 25 C
Ch1: VDCDC
50mV/div
t - Time - 100ms/div
Ch1: VINLDOx
500mV/div
t - Time - 100ms/div
VINDCDC = 3.6V
VINLDOx = 3.6V
o
TA = 25 C
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
t - Time - 100ms/div
t - Time - 200ms/div
Figure 29. Load Transient Response (DC-DC PWM Mode)
Figure 30. Load Transient Response (LDOx)
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10.2.2 Typical TPS65001 Application
TPS65001
VIN
10mF
A
P
EN_DCDC
VINDCDC
MODE
2.2mH
SW
10mF
P
FB_DCDC
150kW
A
22pF
475kW
RSTSNS
0.1nF
470kW
232kW
A
A
VIN
A
VDCDC
3.3V
680kW
470kW
PG
PG
RST
MR
TRST
VLDO1
FB_LDO1
100nF
470kW
10mF
A
180kW
EN_LDO1
VDCDC
A
VLDO2
FB_LDO2
PGND
AGND
VLDO2
2.8V
820kW
10mF
P
VINLDO2
A
RST
VLDO1
1.8V
P
EN_LDO2
VINLDO1
VIN
100kW
P
180kW
A
Figure 31. Typical TPS65001 Application Schematic
10.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 5.
Table 5. Design Parameters
24
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RESOURCES
VOLTAGE
SW
1.2 V
VLDO1
1.8 V
VLDO2
2.8 V
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SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
10.2.3 Typical TPS650001 Application
TPS650001
VIN
10mF
P
A
EN_DCDC
VINDCDC
MODE
2.2mH
VDCDC
1.2V
SW
10mF
P
FB_DCDC
470kW
VIN
PG
VLDO1
FB_LDO1
10mF
VLDO1
1.8V
P
VIN
EN_LDO1
EN_LDO2
VINLDO1
VLDO2
2.8V
VLDO2
FB_LDO2
10mF
P
VINLDO2
A
PGND
AGND
P
Figure 32. Typical TPS650001 Application Schematic
Table 6. Design Parameters
RESOURCES
VOLTAGE
SW
1.2 V
VLDO1
3.3 V
VLDO2
1.8 V
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10.2.4 Typical TPS650061 Application
TPS650061
VIN
10mF
A
P
EN_DCDC
VINDCDC
MODE
2.2mH
SW
VDCDC
1.2V
475kW
10mF
P
FB_DCDC
475kW
A
22pF
470kW
VIN
100kW
475kW
RSTSNS
VIN
0.1mF
470kW
232kW
A
A
VIN
A
PG
RST
MR
TRST
VLDO1
FB_LDO1
100nF
10mF
VLDO1
3.3V
P
A
EN_LDO1
VIN
EN_LDO2
VINLDO1
VLDO2
1.8V
VLDO2
FB_LDO2
10mF
P
VINLDO2
A
PGND
AGND
P
Figure 33. Typical TPS650061 Application Schematic
10.2.4.1 Design Requirements
For this design example, use the parameters listed in Table 7.
Table 7. Design Parameters
RESOURCES
VOLTAGE
SW
1.2 V
VLDO1
3.3 V
VLDO2
1.8 V
11 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 1.6 V to 6 V. This input supply can be
from a DC supply, or other externally regulated supply. If the input supply is located more than a few inches from
the TPS65000, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 10 µF is a typical choice.
26
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SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
The VINDCDC and VINLDOx pins must be bypassed to ground with a low-ESR ceramic bypass capacitor. TI
recommends the typical bypass capacitance is 10 μF and 2.2 μF with a X5R dielectric.
The optimum placement is closest to the VINDCDCx and VINLDOx pins of the device. Minimize the loop area
formed by the bypass capacitor connection, the VINDCDC and VINLDO pins, and the thermal pad of the
device.
The thermal pad must be tied to the PCB ground plane with multiple vias.
The VLDOx and VDCDCx pins (feedback pins) traces must be routed away from any potential noise source
to avoid coupling.
VODC output capacitance must be placed immediately at the VODC pin. Excessive distance between the
capacitance and DCDCx pin may cause poor converter performance.
AGND star back to PGND as close to IC as possible.
DGND connect to thermal pad.
12.2 Layout Example
PowerPad
Vias to GND
plane
Figure 34. Layout Recommendation
Bypass capacitors to GND for VIN pins
Vias to
GND
Figure 35. Bypass Capacitor and Via Placement Recommendation
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Choosing Inductors and Capacitors for DC/DC Converters, SLVA157
• High Efficiency Power Solution for TMS32C2834x MCU, SLDA039
• Power for TMS320C5504/05, SLVA401
• Power for OMAP-L13x, SLYT405
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65000
Click here
Click here
Click here
Click here
Click here
TPS65001
Click here
Click here
Click here
Click here
Click here
TPS650001
Click here
Click here
Click here
Click here
Click here
TPS650003
Click here
Click here
Click here
Click here
Click here
TPS650006
Click here
Click here
Click here
Click here
Click here
TPS650061
Click here
Click here
Click here
Click here
Click here
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
28
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SLVS810C – JUNE 2009 – REVISED SEPTEMBER 2015
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS650001RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAG
TPS650001RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAG
TPS650003RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAH
TPS650006RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
DAI
TPS650006RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAI
TPS65000RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CFO
TPS65000RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CFO
TPS65001RUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CFQ
TPS65001RUKT
ACTIVE
WQFN
RUK
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CFQ
TPS650061RUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAJ
TPS650061RUKT
ACTIVE
WQFN
RUK
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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