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TPS65286
SLVSCG1 – MARCH 2014
TPS65286 Dual Power Distribution Switches With 4.5-V to 28-V Input Voltage,
6-A Output Current Synchronous Buck Regulator
1 Features
3 Description
•
The TPS65286 is a full featured 4.5-V to 28-V VIN,
6-A output current synchronous step down DCDC
converter, which is optimized for small designs
through high efficiency and integrating the high-side
and low-side MOSFETs. The device also
incorporates dual N-channel MOSFET power
switches for power distribution systems. This device
provides a total power distribution solution, where
precision current limiting and fast protection response
are required.
1
•
Integrated Dual Power Distribution Switches:
– 2.5 V to 6 V Operating Input Voltage Range
– Integrated Back-to-Back Power MOSFETs
With Typical 100-mΩ On-Resistance
– Adjustable Current Limiting from 75 mA to
2.7 A
– ±6% Current-Limit Accuracy at 1.2 A (Typical)
– Latch-off Over Current Protection Versions
– Reverse Input-Output Voltage Protection
– Built-In Soft-Start
Integrated Buck DCDC Converter:
– 4.5 V to 28 V Wide Input Voltage Range
– Maximum Continuous 6-A Output Load
Current
– Feedback Reference Voltage 0.6 V ±1%
– Fixed 500-kHz Switching Frequency
– Built-In Internal Soft-Start Time: 1 ms
– Cycle-by-Cycle Current Limit
– Adjustable Current Limit Threshold
– Output Over-Voltage Protection
– External Clock Synchronization
– Over Temperature Protection
Constant frequency peak current mode control in the
DCDC converter simplifies the compensation and
optimizes transient response. Cycle-by-cycle overcurrent protection and operating in hiccup mode limit
MOSFET power dissipation. When die temperature
exceeds thermal over loading threshold, the over
temperature protection shuts down the device.
Device Information
ORDER NUMBER
TPS65286RHD
2 Applications
•
•
•
•
•
•
A dual 100-mΩ independent power distribution switch
limits the output current to a programmable current
limit threshold between typical 50 mA~2.7 A by using
an external resistor. The current limit accuracy can be
achieved as tightly as ±6% at typical 1.2 A. The
nFAULT output asserts low under over-current and
reverse-voltage conditions.
PACKAGE
BODY SIZE
VQFN (28)
5 mm x 5 mm
USB Ports and USB Hubs
Digital TV
Computing Power
Laptop Dock
Car Infotainment
Monitoring
4 Simplified Schematic
+5V
L1
R7
C7
Efficiency
C5
R5
C10
24
FB
SW_EN1
COMP
SW_EN2
25
TPS65286
RLIM
SW_OUT1
R3
26
RSET1
SW_OUT2
R4
27
80
nFAULT2
13
70
SW_EN1
USB Data
R2
C2
14
nFAULT2
12
SW_EN2
C8
11
10
C9
RSET2
EN
9
MODE/
SYNC
8
R5
ENable
USB Data
V7V
GND
GND
C4
VIN
C3
60
50
40
30
20
Efficiency at VOUT = 5 V,
fSW = 500 kHz
0
0.01
0.1
10
7
6
5
GND
4
VIN
3
2
1
VIN
AGND
VIN
28
Efficiency (%)
23
90
R6
USB1
FB
SS
100
FB
R8
USB2
22
SW_IN1
C11
nFAULT1
SW_IN2
LX
BST
LX
LX
nFAULT1
Loading (A)
12V
24V
1
10
C020
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65286
SLVSCG1 – MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 23
1
1
1
1
2
3
5
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 24
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 36
Absolute Maximum Ratings ...................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Typical Characteristics ............................................ 10
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 38
12.1 Trademarks ........................................................... 38
12.2 Electrostatic Discharge Caution ............................ 38
12.3 Glossary ................................................................ 38
Detailed Description ............................................ 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
8.1 Overview ................................................................. 13
5 Revision History
2
DATE
VERSION
NOTES
March 2014
*
Initial release
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6 Terminal Configuration and Functions
LX
LX
LX
BST
SW_IN2
SW_IN1
nFAULT1
28-Terminal VQFN
RHD Package
(Top View)
21
20
19
18
17
16
15
SS
22
14
nFAULT2
FB
23
13
SW_EN1
COMP
24
12
SW_EN2
RLIM
25
11
SW_OUT1
RSET1
26
10
SW_OUT2
RSET2
27
9
EN
AGND
28
8
MODE/SYNC
1
2
3
4
5
6
7
VIN
VIN
VIN
PGND
PGND
PGND
V7V
TPS65286
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
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Terminal Functions
NAME
NO.
DESCRIPTION
VIN
1, 2, 3
Input power supply for buck. Connect this terminal as close as practical to the (+) terminal of an
input ceramic capacitor (suggest 22 µF).
PGND
4, 5, 6
Power ground connection. Connect this terminal as close as practical to the (-) terminal of input
capacitor.
V7V
7
Internal low-drop linear regulator (LDO) output. The internal driver and control circuits are powered
from this voltage. Decouple this terminal to power ground with a minimum 1-M µF ceramic
capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction onresistances of internal power MOSFETs. In PCB design, the power ground and analog ground
should have one-point common connection at the (-) terminal of V7V bypass capacitor.
MODE/SYNC
8
External synchronization input to internal clock oscillator in forced continuous mode. When an
external clock is applied to this terminal, the internal oscillator will force the rising edge of clock
signal to be synchronized with the falling edge of the external clock. Connecting this terminal to
ground forces a continuous current mode (CCM) operation in buck converter. Connecting this
terminal to V7V the buck converter will automatically operate in pulse skipping mode (PSM) at light
load condition to save the power.
EN
9
Enable for buck converter. Adjust the input under-voltage lockup with two resistors.
SW_OUT2
10
Power switch 2 output
SW_OUT1
11
Power switch 1 output
SW_EN2
12
Enable power switch 2. There is an internal 1.25-MΩ pull-up resistor connecting this terminal to
SW_IN2.
SW_EN1
13
Enable power switch 1. There is an internal 1.25-MΩ pull-up resistor connecting this terminal to
SW_IN1.
nFAULT2
14
Active low open drain output, asserted during over-current or reverse-voltage condition of power
switch 2.
nFAULT1
15
Active low open drain output, asserted during over-current or reverse-voltage condition of power
switch 1.
SW_IN1
16
Power switch input voltage for USB1. Connect to buck output, or other power supply input.
SW_IN2
17
Power switch input voltage for USB2. Connect to buck output, or other power supply input.
BST
18
Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor
(recommend 47 nF) from this terminal to LX.
LX
19, 20, 21
SS
22
Soft-start and tracking input for buck converter. An internal 5.5-µA pull-up current source is
connected to this terminal. An external soft-start can be programmed by connecting a capacitor
between this terminal and ground. Leave the terminal floating to have a default 1ms of soft-start
time. This terminal allows the start-up of buck output to track an external voltage using an external
resistor divider at this terminal.
FB
23
Feedback sensing terminal for buck output voltage. Connect this terminal to the resistor divider of
buck output. The feedback reference voltage is 0.6 V ±1%.
COMP
24
Error amplifier output and Loop compensation terminal for buck. Connect a series resistor and
capacitor to compensate the control loop of buck converter with peak current PWM mode.
RLIM
25
BUCK current limit control terminal. An external resistor used to set current limit threshold of buck
converter. Recommended 120 kΩ ≤ RLIM ≤ 450kΩ. Connect this terminal to GND, set the current
limit to 8 A.
RSET1
26
Power switch current limit control terminal. An external resistor used to set current limit threshold
of power switch 1. Recommended 9.1 kΩ ≤ RLIM ≤ 300 kΩ.
RSET2
27
Power switch current limit control terminal. An external resistor used to set current limit threshold
of power switch 2. Recommended 9.1 kΩ ≤ RLIM ≤ 300 kΩ.
AGND
28
Analog ground common to buck controller and power switch controller. AGND must be routed
separately from high current power grounds to the (-) terminal of bypass capacitor of internal V7V
LDO output.
Power PAD
4
Switching node connection to the inductor and bootstrap capacitor for buck converter. This
terminal voltage swings from a diode voltage below the ground up to VIN voltage.
Exposed pad beneath the IC. Connect to the power ground. Always solder power pad to the
board, and have as many vias as possible on the PCB to enhance power dissipation. There is no
electric signal down bonded to pad inside the IC package.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 30
V
Voltage range at LX (maximum withstand voltage transient < 20 ns)
–1 to 30
V
Voltage at BST referenced to LX terminal
–0.3 to 7
V
Voltage at SW_IN1, SW_OUT1, SW_ IN2, SW_ OUT2
–0.3 to 7
V
Voltage at EN, SW_EN1, SW_EN2, nFAULT1, nFAULT2, V7V,
MODE/SYNC
–0.3 to 7
V
Voltage at SS, COMP , RLIM, RSET1, RSET2, FB
–0.3 to 3.6
V
Voltage at AGND, PGND
–0.3 to 0.3
V
Operating virtual junction temperature range
–40 to 125
°C
Voltage range at VIN, LX
TJ
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
PARAMETER
Tstg
VESD (1)
(1)
(2)
(3)
DEFINITION
MIN
Storage temperature range
-55
Human body model (HBM) ESD stress voltage (2)
MAX
UNIT
150
°C
2000
Charge device model (CDM) ESD stress voltage (3)
V
500
Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into
the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process. Terminals listed as 1 kV may actually have higher performance.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
28
V
TA
Ambient temperature
–40
125
°C
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7.4 Thermal Information
TPS65286
THERMAL METRIC (1)
RHD
UNIT
28 TERMINAL
Junction-to-ambient thermal resistance (2)
RθJA
35.6
(3)
RθJCtop
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance (4)
7.9
RψJT
Junction-to-top characterization parameter (5)
0.3
RψJB
Junction-to-board characterization parameter (6)
7.96
RθJCbot
Junction-to-case (bottom) thermal resistance (7)
1.1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
24.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
7.5 Electrical Characteristics
TJ = 25°C, VIN = 24 V, fSW = 500 kHz, RnFAULTx = 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
VIN1 and VIN2
IDDSDN
Shutdown supply current
EN1 = EN2 = low
IDDQ_NSW
Quiescent current without buck
switching
EN = high, ENx = low, FB = 1 V
Without buck switching
0.8
mA
IDDQ_SW
Input quiescent current with buck
switching
EN = high, ENx = low, FB = 0.6 V
With buck switching
26
mA
UVLO
VIN under voltage lockout
4.5
7.60
Rising VIN
4
Falling VIN
3.75
Hysteresis
V7V
Low side gate driver, controller,
biasing supply
IOCP_V7V
Current limit of V7V LDO
V7V load current = 0 A,
VIN = 24 V
28
V
15
µA
4.25
4.50
4
4.25
V
6.4
V
0.25
6.10
6.25
83
mA
ENABLE
VENR
Enable threshold
Rising
VENF
Enable threshold
Falling
1.17
V
IENL
Enable pull-up current
EN = 1 V
3
µA
IENH
Enable pull-up current
EN = 1.5 V
6
µA
IENHYS
Enable hysteresis current
3
µA
6
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1.21
1.10
1.26
V
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Electrical Characteristics (continued)
TJ = 25°C, VIN = 24 V, fSW = 500 kHz, RnFAULTx = 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSW
Switching frequency
Internal oscillator clock frequency
400
500
600
kHz
TSYNC_w
Clock sync minimum pulse width
VSYNC_HI
Clock sync high threshold
VSYNC_LO
Clock sync low threshold
VSYNC_D
Clock falling edge to LX rising edge
delay
fSYNC
Clock sync frequency range
OSCILLATOR
80
ns
2
0.8
V
V
200
120
ns
1600
kHz
BUCK CONVERTER
VIN
Input supply voltage
4.5
28
VCOMP = 1.2 V, TJ = 25°C
0.594
0.6
0.606
0.588
0.6
0.612
V
VFB
Feedback voltage
VCOMP = 1.2 V,
TJ = 40°C to 125°C
Gm_EA
Error amplifier trans-conductance
-4 µA < ICOMP < 4 µA
Gm_SRC
COMP voltage to inductor current
Gm (1)
ILX = 0.5 A
ISS
Soft-Start terminal charging current
SS = 1 V
TSS_INT
Internal Soft-Start time
SS terminal floats
0.5
1
1.5
ILIMIT
Buck peak inductor current limit
RLIM = 0 Ω
6.6
7.7
8.7
TON_MIN
Minimum on time (current sense
blanking)
Rdson_HS
On resistance of high side FET
V7V = 6.25 V, includes bondwire
resistance
55
mΩ
Rdson_LS
On resistance of low side FET
VIN = 24 V, includes bondwire
resistance
30
mΩ
Thiccupwait
Hiccup wait time
256
cycles
Thiccup_re
Hiccup time before re-start
8192
cycles
1240
µS
9.2
A/V
5.5
RLIM = 200 kΩ
%/V
µA
5.2
85
120
ms
A
ns
POWER DISTRIBUTION SWITCH
VSW_IN
VUVLO_SW
RDSON_SW
Power switch input voltage range
2.5
Input under-voltage lock out
Power switch NDMOS on-resistance
6
VSW_IN rising
2.15
2.25
2.35
VSW_IN falling
2.05
2.15
2.25
Hysteresis
0.1
VSW_INx = 5 V, ISW_OUTx = 0.5 A,
TJ = 25°C, includes bondwire
resistance
100
VSW_INx = 2.5 V, ISW_OUTx = 0.5 A,
TJ = 25°C, includes bondwire
resistance
100
V
V
mΩ
tD_on
Turn-on delay time
1.26
1.9
ms
tD_off
Turn-off delay time
1.17
1.76
ms
tr
Output rise time
0.86
1.3
ms
tf
Output fall time
ms
VSW_INx = 5 V, CL = 10 µF,
RL = 100 Ω (see Figure 1)
IOS
Current limit threshold (Maximum DC
current delivered to load) and short
circuit current, SW_OUT connect to
ground
TIOS
Response time to short circuit
(1)
1.37
2.06
RSET = 14.3 kΩ
1.65
1.76
1.87
RSET = 20 kΩ
1.18
1.26
1.34
RSET = 50 kΩ
RSET shorted to SW_IN or open
VSW_INx = 5 V
0.5
1.18
1.2
A
1.34
2
us
Ensured by design.
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Electrical Characteristics (continued)
TJ = 25°C, VIN = 24 V, fSW = 500 kHz, RnFAULTx = 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
7
10
13
ms
400
mV
TDEGLITCH(OCP)
Switch over current fault deglitch
Fault assertion or de-assertion
due to over-current condition
VL_nFAULT
nFAULTx terminal output low voltage
InFAULTx = 1 mA
VEN_SWH
SW_EN1/2 high level input voltage
SW_EN1, SW_EN2
VEN_SWL
SW_EN1/2 low level input voltage
SW_EN1, SW_EN2
RDIS
Discharge resistance (2)
VSW_INx = 5 V, VSW_ENx = 0 V
104
Ω
Rising temperature
160
°C
2
V
0.4
V
THERMAL SHUTDOWN
TTRIP_BUCK
THYST_BUCK
TTRIP_SW
THYST
(2)
8
Thermal protection trip point
Power switch thermal protection trip
point
Hysteresis
Rising temperature
Hysteresis
20
°C
145
°C
20
°C
The discharge function is active when the device is disabled (when enable is de-asserted). The discharge function offers a resistive
discharge path for the external storage capacitor.
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50%
50%
tD_on tr
tD_off tf
VENx
90%
VOUTx
90%
10%
10%
Figure 1. Power Switches Test Circuit and Voltage Waveforms
IOUT
120% ´ IOS
IOS
0A
tIOS
Figure 2. Response Time to Short Circuit Waveform
VIN
Decreasing
Load
Resistance
VOUT
Slope = –rDS(on)
0V
0A
IOUT
IOS
Figure 3. Output Voltage vs Current Limit Threshold
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7.6 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
60
50
40
60
50
40
30
30
20
20
Forced PWM
Auto PSM-PWM
10
0
0.01
0.1
1
10
10
Loading (A)
0.1
1
10
Loading (A)
C019
Figure 4. Buck Efficiency, VOUT = 5 V
C003
Figure 5. Buck Efficiency, VOUT = 2.5 V
5.100
2.570
5.095
2.565
5.090
2.560
5.085
5.080
VOUT (V)
VOUT (V)
Auto PSM-PWM
Forced PWM
0
0.01
5.075
5.070
5.065
2.555
2.550
2.545
2.540
5.060
Auto PWM-PSM
Forced PWM
5.055
5.050
2.535
Auto PWM-PSM
Forced PWM
2.530
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Loading (A)
Loading (A)
C018
Figure 6. Buck Line Regulation, VOUT = 5 V
C017
Figure 7. Buck Line Regulation, VOUT = 2.5 V
5.20
2.60
5.15
2.58
VOUT (V)
VOUT (V)
5.10
5.05
2.56
2.54
5.00
Forced PWM 6A
4.95
2.52
Forced PWM 0A
4.90
6
8
10
12
14
16
18
20
22
24
2.50
26
VIN (V)
28
6
8
10
12
14
16
18
20
22
24
26
VIN (V)
C013
Figure 8. Buck Load Regulation, VOUT = 5 V
10
Forced PWM 0A
Forced PWM 6A
Auto PSM-PWM 0A
Auto PSM-PWM 0A
28
C014
Figure 9. Buck Load Regulation, VOUT = 2.5 V
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Typical Characteristics (continued)
TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
28
Quiescent switching Current ( mA)
0.90
Quiescent Current ( mA)
0.85
0.80
0.75
0.70
0.65
0.60
26
25
24
23
22
21
20
±50
±20
10
40
70
100
Tj - Junction Temperature (C)
130
±50
10
40
70
100
130
Tj - Junction Temperature (C)
C012
Figure 11. IIN (With Buck Switching) vs Temperature
540
0.63
530
Internal Frequency (kHz)
0.62
0.61
0.60
0.59
0.58
520
510
500
490
480
470
460
0.57
±50
±20
10
40
70
100
Tj - Junction Temperature (C)
130
±50
±20
10
40
70
100
130
Tj - Junction Temperature (C)
C021
Figure 12. Reference Voltage vs Temperature
C010
Figure 13. Oscillator Frequency vs Temperature
1.24
1.17
1.23
EN Terminal UVLO - Low (V)
EN Terminal UVLO - High (V)
±20
C011
Figure 10. IIN (Without Switching) vs Temperature
FB Voltage ( V)
27
1.22
1.21
1.20
1.19
1.18
1.16
1.15
1.14
1.13
-50
-20
10
40
70
100
Tj - Junction Temperature (°C)
130
±50
±20
Figure 14. EN UVLO Start vs Temperature
10
40
70
100
Tj - Junction Temperature (°C)
C002
130
C001
Figure 15. EN UVLO Stop vs Temperature
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Typical Characteristics (continued)
TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
75
40
/RZVLGH5'6B21 P
+LJKVLGH5'6B21 P
70
65
60
55
50
45
35
30
25
20
40
35
15
±50
±20
10
40
70
100
Tj - Junction Temperature (C)
130
±50
7.3
100
7.2
95
Minimun On Time (ns)
Current Limit (A)
40
70
100
130
C007
Figure 17. Low-Side RDS_ON vs Temperature
7.1
7.0
6.9
6.8
90
85
80
75
6.7
70
±50
±30
±10
10
30
50
70
Te - Environment Temperature (C)
90
±50
±20
10
40
70
100
Tj - Junction Temperature (C)
C004
Figure 18. Buck DC Max IOUT vs Temperature
130
C005
Figure 19. Minimum On Time vs Temperature
2.9
8.5
8.3
2.8
Current Limit (A)
Buck Current limit ( A)
10
Tj - Junction Temperature (C)
Figure 16. High-Side RDS_ON vs Temperature
8.1
7.9
2.7
2.6
7.7
7.5
2.5
6
10
14
18
22
26
Vin (V)
30
±50
±30
±10
10
30
50
Te - Environment Temperature (C)
C008
Figure 20. Buck Current Limit vs VIN
(RLIMIT = 120 kΩ)
12
±20
C006
70
90
C009
Figure 21. Power Switch Current Limit vs Temperature
(RSET = 9.1 kΩ)
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8 Detailed Description
8.1 Overview
The TPS65286 PMIC integrates two independent current-limited, power distribution switches using N-channel
MOSFETs for applications where short circuits or heavy capacitive loads will be encountered and provide
precision current limit protection and fast protection response to over current. Additional device features include
over temperature protection and reverse-voltage protection. The device incorporates an internal charge pump
and gate driver circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the
driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge
pump operates from the input voltage of power switches as low as 2.5 V. The driver incorporates circuitry that
controls the rise and fall times of the output voltage to limit large current and voltage surges and provides built-in
soft-start functionality. The TPS65286 device limits output current to a safe level when output load exceeds the
current limit threshold. After deglitching time, the device latches off when the load exceeds the current limit
threshold. The device asserts the nFAULT1/2 signal during over current or reverse voltage faulty condition.
The TPS65286 PMIC also integrates a synchronous step-down converter with regulated 0.6 V ±1% feedback
reference voltage. The synchronous buck converter incorporates 55-mΩ high side power MOSFET and
30-mΩ low side power MOSFETs to achieve high efficiency power conversion. The converter supports an input
voltage range from 4.5 V to 28 V. The converter operates in continuous conduction mode (CCM) with peak
current mode control for simplified loop compensation. The peak inductor current limit threshold is adjustable to
up to 8 A. The switching clock frequency is a fixed 500 kHz. The soft-start time can be adjusted by connecting an
external capacitor at the SS terminal or fixed at 1 ms with the SS terminal open.
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8.2 Functional Block Diagram
V7V
7
1
LDO
2
Voltage Reference
Current Bias
Preregulator
3
HS current
sensing
VIN
VIN
VIN
CS
18
EN
RLIM
COMP
FB
BST
9
25
24
23
enable comparator
enable
threshold
HS driver
Current
Sensing
(0.1V/A)
19
20
Buck
Controller
21
PWM comparator
V7V
slope
comp
Vfb
LX
LX
LX
LS driver
0.6V
SS
22
error amplifer
CS
1ms
Internal
Soft Start
MODE/SYNC
AGND
LS current
sensing
Oscillotor
Mode
4
5
8
6
BUCK
28
PGND
PGND
PGND
POWER SWITCH 2
SW_EN2
enable buffer
12
10ms
Degl.
Time
1.25M
Driver
14
Current
Limit
nFAULT2
1.25M
27
Charge
Pump
current sensing
10
CS
SW_IN2
SW_IN1
17
reverse
voltage
comparator
UVLO
POR
16
RSET2
4ms Degl.
Time
UVLO
POR
SW_OUT2
reverse voltage
comparator
11
CS
current sensing
Charge
Pump
4ms Degl.
Time
26
1.25M
Driver
15
Current
Limit
SW_OUT1
RSET1
nFAULT1
1.25M
SW_EN1
13
enable buffer
10ms
Degl.
Time
POWER SWITCH 1
14
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8.3 Feature Description
8.3.1 Power Switch
8.3.1.1 Over Current Condition
The TPS65286 responds to over-current conditions on power switches by limiting the output currents to the IOS
level, which is set by an external resistor. During normal operation the N-channel MOSFET is fully enhanced,
and VSW_OUT = VSW_IN - (ISW_OUT x RDSON_SW). The voltage drop across the MOSFET is relatively small compared
to VSW_IN, and VSW_OUT ≈ VSW_IN. When an over current condition is detected, the device maintains a constant
output current and reduces the output voltage accordingly. During current-limit operation, the N-channel
MOSFET is no longer fully-enhanced and the resistance of the device increases. This allows the device to
effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the
MOSFET is that the voltage drop across the device is no longer negligible (VSW_IN ≠ VSW_OUT) and VSW_OUT
decreases. The amount that VSW_OUT decreases is proportional to the magnitude of the overload condition. The
expected VSW_OUT can be calculated by IOS × RLOAD, where IOS is the current-limit threshold and RLOAD is the
magnitude of the overload condition.
Three possible overload conditions can occur as summarized in Table 1.
Table 1. Overload Conditions
CONDITIONS
BEHAVIORS
Short circuit or partial short circuit present
when the device is powered up or enabled.
The output voltage is held near zero potential with respect to ground and the TPS65286
ramps output current to IOS. The device limits the current to IOS until the overload condition is
removed or the internal deglitch time (10 ms typical) is reached and the device is turned off.
The device will remain off until power is cycled or the device enable is toggled.
Gradually increasing load (< 100 A/s) from
normal operating current to IOS.
The current rises up to the current limit. Once the threshold has been reached, the device
switches into its current limiting at IOS. The device limits the current to IOS until the overload
condition is removed or the internal deglitch time (10 ms typical) is reached and the device is
turned off. The device will remain off until power is cycled or the device enable is toggled.
Short circuit, partial short circuit or fast
transient overload occurs while the device is
enabled and powered on.
The device responds to the over-current condition within time tIOS. The current sensing
amplifier is overdriven during this time and needs time for loop response. Once tIOS has
passed, the current sensing amplifier recovers and limits the current to IOS. The device limits
the current to IOS until the overload condition is removed or the internal deglitch time (10 ms
typical) is reached and the device is turned off. The device will remain off until power is
cycled or the device enable is toggled.
8.3.1.2 Reverse Current and Voltage Protection
A power switch in the TPS65286 incorporates dual back-to-back N-channel power MOSFETs so as to prevent
the reverse current flowing back the input through body diode of MOSFET when the power switches are off.
The reverse-voltage protection turns off the N-channel MOSFETs whenever the output voltage exceeds the input
voltage by 135 mV (typical) for 4 ms (typical). This prevents damaging devices by blocking significant current
reverse injection into the input capacitance of power switch or buck output capacitance. The TPS65286 keeps
the power switch turned off even if the reverse-voltage condition is removed and does not allow the N-channel
MOSFET to turn on until power is cycled or the device enable is toggled. The reverse-voltage comparator also
asserts the nFAULT1/2 output (active-low) after 4 ms.
8.3.1.3 nFAULT1/2 Response
The nFAULT1/nFAULT2 open-drain output is asserted (active low) during an over current, over temperature or
reverse-voltage condition and remains asserted while the part is latched-off. The nFAULT signal is de-asserted
once the device power is cycled or the enable is toggled and the device resumes normal operation. The
TPS65286 is designed to eliminate false nFAULT reporting by using an internal delay deglitch circuit for over
current (10 ms typical) and reverse-voltage (4 ms typical) conditions without the need for external circuitry. This
ensures that nFAULT is not accidentally asserted due to normal operation such as starting into a heavy
capacitive load. Deglitching circuitry delays entering and leaving fault conditions. Over temperature conditions
are not deglitched and assert the FAULT signal immediately. Figure 22 shows the over current operation of USB
switch.
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USB_VIN
0
USB_EN
USB_OUT
Over current is detected
Over current is cleared
Ios
USB_I
Normal operation
Overcurrent at the output
Alarm is asserted after 10ms
Alarm is cleared
Normal operation is restored
nFAULT
Tdeglith
T deglitch
Figure 22. USB Switch Over Current Operation
8.3.1.4 Under-Voltage Lockout (UVLO)
The under-voltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large
current surges.
8.3.1.5 Enable and Output Discharge
The logic enable EN_SW1/EN_SW2 controls the power switch, bias for the charge pump, driver, and other
circuits. The supply current from power switch driver is reduced to less than 1 µA when a logic low is present on
EN_SW1/2. A logic high input on EN_SW1/EN_SW2 enables the driver, control circuits, and power switch. The
enable input is compatible with both TTL and CMOS logic levels.
When enable is de-asserted, the discharge function is active. The output capacitor of power switch is discharged
through an internal NMOS with a 104-Ω resistance. The time taken for discharging is dependent on the RC time
constant of the resistance and the output capacitor.
8.3.1.6 Power Switch Input and Output Capacitance
Input and output capacitors improve the performance of the device. The actual capacitance should be optimized
for the particular application. The output capacitor in buck converter is recommended to place between SW_IN
and AGND as close to the device as possible for local noise de-coupling. Additional capacitance may be needed
on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device during
heavy transient conditions. This is especially important during bench testing when long, inductive cables are
used to connect the input of power switches in the evaluation board to the bench power-supply. Placing a highvalue electrolytic capacitor on the output terminal is recommended when large transient currents are expected on
the output.
8.3.1.7 Programming the Current-Limit Threshold
The over-current threshold is user programmable via an external resistor. The TPS65286 uses an internal
regulation loop to provide a regulated voltage reference on the RLIM terminal. The current-limit threshold is
proportional to the current sourced out of the RSET terminal. A resistor with 1% accuracy is used between 10 kΩ
≤ RSET ≤ 232 kΩ to ensure stability of the internal regulation loop. Equation 1 and Figure 23 can be used to
calculate current limiting threshold for a given external resistor value.
Current-limit threshold equation (IOS):
IOS = 27.465 x (RSET)-1.04
16
(1)
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3
2.5
ILIMIT(A)
2
1.5
1
0.5
0
0
50
100
150
200
250
300
350
RSET (kΩ)
Figure 23. Current-Limit Threshold IOS vs RLIM
8.3.2 Buck DCDC Converter
8.3.2.1 Output Voltage
The TPS65286 regulate output voltage set by a feedback resistor divider to 0.6-V reference voltage with
feedback resistor divider. It is recommended to use 1% tolerance or better divider resistors. Great care should be
taken to route the FB line away from noise sources, such as the inductor or the LX switching node line. Start with
39 kΩ for the R1 resistor and use Equation 2 to calculate R2.
0.6V
R2 = R1 × (
)
VOUT - 0.6V
(2)
Vout=5V
R1
39k
C1
82pF
23
-
FB
EA
+
0.6V
Reference
R2
5.3k
24
COMP
Figure 24. Buck Feedback Resistor Divider
8.3.2.2 Clock Synchronization
An internal phase locked loop (PLL) has been implemented to allow an external clock with frequency between
200 kHz and 1600 kHz to be synchronized to the internal clock. To implement the synchronization feature,
connect a clock signal to the MODE/SYNC terminal with minimum pulse width larger than 80 ns and low/high
voltage threshold at 0.4 V/2V. When an external clock is applied to MODE/SYNC terminal, the internal oscillator
will force the rising edge of clock signal to be synchronized with the falling edge of the external clock.
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TPS65286
Mode
Selection
MODE/
SYNC
Figure 25. Clock Synchronization Mode
8.3.2.3 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the FB terminal voltage to the
lower of the SS terminal voltage or the internal 0.6-V voltage reference. The transconductance of the error
amplifier is 1300 µA/V during normal operation. The frequency compensation network is connected between the
COMP terminal and ground.
8.3.2.4 Slope Compensation
The device adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations. The slope rate of slope compensation remains constant over the full duty cycle range.
8.3.2.5 Enable and Adjusting Under-Voltage Lockout
The EN terminal provides electrical on/off control of the device. Once the EN terminal voltage exceeds the
threshold voltage, the device starts operation. If the EN terminal voltage is pulled below the threshold voltage, the
regulator stops switching and enters low Iq state. The EN terminal has an internal pull-up current source,
allowing the user to float the EN terminal for enabling the device. If an application requires controlling the EN
terminal, use open drain or open collector output logic to interface with the terminal. The device implements
internal UVLO circuitry on the VIN terminal. The device is disabled when the VIN terminal voltage falls below the
internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150 mV. If an application
requires either a higher UVLO threshold on the VIN terminal or a secondary UVLO on the PVIN in split rail
applications, then the EN terminal can be configured as shown in Figure 26. When using the external UVLO
function, it is recommended to set the hysteresis to be greater than 500 mV.
The EN terminal has an internal pull-up current source, allowing the user to float the EN terminal for enabling the
device. If an application requires controlling the EN terminal, use open drain or open collector output logic to
interface with the terminal. The pull-up current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ih once the EN terminal crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 3 and Equation 4.
TPS65286
VIN
Ip
Ih
R1
9
EN
R2
enable threshold
Figure 26. Adjustable VIN Under Voltage Lock Out
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VENFALLING
) - VSTOP
VENRISING
V
IP (1 - ENFALLING ) + Ih
VENRISING
(3)
R1 ´ VENFALLING
VSTOP - VENFALLING + R1(Ih + Ip )
(4)
VSTART (
R1 =
R2 =
Where Ih = 1 µA, Ip = 2 µA, VENRISING = 1.21 V, and VENFALLING = 1.17 V.
8.3.2.6 Soft-Start Time
During startup, the output voltage follows up the voltage at the SS terminal to prevent inrush current. When the
SS terminal voltage is less than the internal 0.6-V reference, the TPS65286 regulates the feedback voltage to the
SS terminal voltage. The SS terminal can be used to program an external soft-start function or to allow output of
the buck to track another supply during start-up. An internal pull-up current source of 5.5 µA charges an external
soft-start capacitor to provide a ramping voltage at SS terminal. The TPS65286 will regulate the feedback voltage
to the SS terminal voltage and VOUT rises smoothly from 0 V to its final regulated voltage. The soft-start time
can be calculated by Equation 5:
Css(nF) ´ Vref(V)
Tss(ms) =
Iss(uA)
(5)
With a floating SS terminal, there is default 1-ms (typical) soft-start time built in the chip.
8.3.2.7 Internal V7V Regulator
The TPS65286 features an internal low dropout linear regulator (LDO) from VIN to V7V. The LDO regulates V7V
to 6.3-V over drive voltage on power MOSFET for the best efficiency performance. the LDO also provides supply
bias for internal analog controller and power for low-side MOSFET for the best efficiency performance. The
current limit of LDO is 50 mA and connecting a minimum 1-µF ceramic capacitor to the V7V terminal is
recommended. Directly placing the capacitor close to the V7V and PGND terminals is highly recommended for
high transient current required by the MOSFET gate drivers.
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8.3.2.8 Hard Short Circuit Protection
The peak inductor current limit trip of buck converter is set by an external resistor at the RLIM terminal. The peak
inductor current threshold for over current protection can be calculated by Equation 6.
ILIMIT = 926.78 x (RLIM)-0.979
(6)
500
450
400
350
R (kΩ)
300
250
200
150
100
50
0
0
1
2
3
4
5
6
7
8
9
ILIMIT(A)
Figure 27. Current-Limit Threshold vs RLIM
The device is protected from over current conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
High-side MOSFET over current protection:
The device implements current mode control which uses the COMP terminal voltage to control the turn off of the
high-side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch
current and the current reference generated by the COMP terminal voltage are compared, the peak switch
current intersects the current reference and the high-side switch is turned off.
Low-side MOSFET over current protection:
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally sourcing current limit threshold. If the low-side sourcing
current is exceeded, the high-side MOSFET is turned off and the low-side MOSFET is forced on for the next
cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit threshold at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the next cycle. Furthermore, if an output overload condition (as measured by the COMP terminal voltage)
has lasted for more than the hiccup wait time which is programmed for 256 switching cycles, the device will shut
down and recover after the hiccup time of 8192 cycles. The hiccup mode helps to reduce the device power
dissipation under over current conditions.
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Vout
Current limit threshold
IL
256 clock cycles
VLX
8192
Figure 28. DCDC Over-Current Protection
8.3.2.9 Bootstrap Voltage (BST) and Low Dropout Operation
The device has an integrated bootstrap regulator and requires a small ceramic capacitor between the BST and
LX terminals to provide the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is charged
when the BST terminal voltage is less than VIN and BST-LX voltage is below regulation. The value of this
ceramic capacitor is recommended 0.047 μF or less. A ceramic capacitor with an X7R or X5R grade dielectric
with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature
and voltage.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BST to LX terminal
voltage is greater than the BST-LX UVLO threshold which is typically 2.1 V. When the voltage between BST and
LX drops below the BST-LX UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
8.3.2.10 Thermal Performance
The device implements an internal thermal overloading sensor to protect the chip with stopping buck converter
switching if the junction temperature exceeds 160°C. Once the die temperature decreases below 140°C, the
device automatically reinitiates the power up sequence.
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8.3.2.11 Loop Compensation
The integrated buck DCDC converter in TPS65286 incorporates a peak current mode. The error amplifier is a
trans-conductance amplifier with a gain of 1000 µA/V. A typical type II compensation circuit adequately delivers a
phase margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when
needed. To calculate the external compensation components, follow these steps:
1. Select switching frequency, fSW, that is appropriate for application depending on L and C sizes, output ripple,
and EMI. Switching frequency between 500 kHz to 1 MHz gives the best trade off between performance and
cost. To optimize efficiency, lower switching frequency is desired.
2. Set up cross over frequency, fc, which is typically between 1/5 and 1/20 of fSW.
3. RC can be determined by:
2p × fc × Vo × Co
RC =
gM × Vref × gmps
(7)
where gM is the error amplifier gain (1000 µA/V), gmps is the power stage voltage to current conversion gain
(10 A/V).
4. Calculate CC by placing a compensation zero at or before the dominant pole (fp = 1 / CO x RL x 2π).
R × Co
CC = L
RC
(8)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
Re sr × Co
Cb =
RC
(9)
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C1 is calculated from Equation 10.
1
C1 =
2p × R1 × fC
(10)
VOUT
R1
C1
39K
Vref =0.6V
COMP
Current Sense
I/V Converter
EA
Vfb
iL
gM =1000uS
R2
VOUT
RESR
gmps =13.6A/V
RL
5.3K
Cb
Rc
Co
Cc
Figure 29. DCDC Loop Compensation
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8.4 Device Functional Modes
8.4.1 Pulse Skipping Mode Operation
When a synchronous buck converter operates at light load condition, TPS65286 operates with pulse skipping
mode (PSM) to reduce the switching loss by keeping the power transistors in the off-state for several switching
cycles, while maintaining a regulated output voltage. The output voltage, load and inductor current diagrams are
shown in Figure 30. When the VCOMP falls lower than VGS, the COMP terminal voltage is clamped to VGS
internally, typical 350 mV, the device enters pulse skipping mode and high side MOSFET stops switching, then
the output falls and the VCOMP rises. When the VCOMP rises larger than VGS, the high side MOSFET starts
switching, then the output rises and the VCOMP falls. When the VCOMP falls lower than VGS, the high side
MOSFET stops switching again. If the peak inductor current rise above typical 600 mA (VIN = 24 V, VOUT = 5 V)
and the COMP terminal voltage to rise above VGS, the converter exits pulse skipping mode. Since converter
detects the peak inductor current for pulse skip mode, the average load current entering pulse skipping mode
varies with the applications and external output filters.
VOUT
IL
Burst
Skipping
IOUT
Figure 30. Pulse Skipping Mode
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9 Application and Implementation
9.1 Application Information
The TPS65286 is a step down dc/dc converter. It is typically used to convert a higher dc voltage to a lower dc
voltage with a maximum available output current of 6 A. The following design procedure can be used to select
component values for the TPS65286.
Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. This section presents a simplified discussion of the design process.
9.2 Typical Applications
The application schematic of Figure 31 was developed to meet the requirements above. This circuit is available
as the TPS65286EVM evaluation module. The design procedure is given in this section.
+5V
L1
R7
C7
C5
R5
C10
23
24
SW_EN1
25
SW_EN2
TPS65286
RLIM
SW_OUT1
R3
26
RSET1
SW_OUT2
R4
27
nFAULT2
13
SW_EN1
USB Data
COMP
R2
C2
14
nFAULT2
FB
R6
12
SW_EN2
USB1
FB
SS
R8
C8
11
10
C9
RSET2
EN
9
MODE/
SYNC
8
R5
USB2
22
FB
nFAULT1
C11
SW_IN1
SW_IN2
BST
LX
LX
LX
nFAULT1
ENable
USB Data
V7V
7
GND
6
GND
5
GND
4
VIN
3
2
1
VIN
AGND
VIN
28
C4
VIN
C3
Figure 31. Typical Application Schematic
24
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Typical Applications (continued)
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4.5 V - 28 V
Output voltage
5V
Transient response, 1.5-A load step
ΔVOUT = ±5%
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
6A
Operating frequency
500 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Step by Step Design Procedure
To
•
•
•
•
•
•
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Input voltage range
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
9.2.2.2 Related Parts
PART NO.
TPS65280
DESCRIPTION
COMMENTS
One buck converter and two USB switches
0.3 ≤ fSW ≤ 1.4 MHz, 4.5 V ≤ VIN ≤ 18 V, VOUT fixed 5 V, maximum
DC current 4 A, 2.5 V ≤ VSW_IN ≤ 6 V, USB current limit fixed
1.2 A, with manufacture trim option.
TPS65281, TPS65281-1 One buck converter and one USB switch
0.3 ≤ fSW ≤ 1.4 MHz, 4.5 V ≤ VIN ≤ 18 V, VOUT adjustable,
maximum DC current 4 A, 2.5 V ≤ VSW_IN ≤ 6 V, USB current limit
adjustable form 75 mA to 2.7 A.
TPS65282
One buck converter and two USB switches
0.3 ≤ fSW ≤ 1.4 MHz, 4.5 V ≤ VIN ≤ 18 V, VOUT adjustable,
maximum DC current 4 A, 2.5 V ≤ VSW_IN ≤ 6 V, USB current limit
adjustable form 75 mA to 2.7 A.
TPS65287
Three buck converters and one USB switch
0.3 ≤ fSW ≤ 2.2 MHz, 4.5 V ≤ VIN ≤ 18 V, VOUT adjustable,
maximum DC current 3/2/2 A, 2.5 V ≤ VSW_IN ≤ 6 V, USB current
limit adjustable form 75 mA to 2.7 A.
TPS65288
Three buck converters and two USB
switches
0.3 ≤ fSW ≤ 2.2 MHz, 4.5 V ≤ VIN ≤ 18 V, VOUT adjustable,
maximum DC current 3/2/2 A, 2.5 V ≤ VSW_IN ≤ 6 V, USB current
limit fixed 1.2 A, with manufacture trim option.
9.2.2.3 Inductor Selection
The higher operating frequency allows the use of smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off,
the effect of inductor value on ripple current and low current operation must also be considered. The ripple
current depends on the inductor value. The inductor ripple current iL decreases with higher inductance or higher
frequency and increases with higher input voltage VIN. Accepting larger values of iL allows the use of low
inductances, but results in higher output voltage ripple and greater core losses.
To calculate the value of the output inductor, use Equation 11. LIR is a coefficient that represents inductor peakto-peak ripple to DC load current. LIR is suggested to choose to 0.1 ~ 0.3 for most applications.
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Actual core loss of inductor is independent of core size for a fixed inductor value, but it is very dependent on
inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss
and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing
saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak
design current is exceeded. It results in an abrupt increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate. It is important that the RMS current and saturation current
ratings are not exceeding the inductor specification. The RMS and peak inductor current can be calculated from
Equation 13 and Equation 14.
V - Vout
Vout
L = in
×
IO × LIR Vin × fsw
(11)
DiL =
Vin - Vout
Vout
×
L
Vin × fsw
(12)
Vout × (Vinmax - Vout ) 2
)
Vinmax × L × fsw
2
iLrms = IO +
12
Di
ILpeak = IO + L
2
(
(13)
(14)
For this design example, use LIR = 0.3 and the inductor is calculated to be 4.40 µH with VIN = 24 V. Choose
4.7 µH value of the standard inductor, the peak to peak inductor ripple is about 28.1% of 6-A DC load current.
9.2.2.4 Output Capacitor Selection
There are two primary considerations for selecting the value of the output capacitor. The output capacitors are
selected to meet load transient and output ripple’s requirements. Equation 15 gives the minimum output
capacitance to meet the transient specification. For this example, Lo = 4.7 µH, ΔIOUT = 3 A – 0 A = 3 A and
ΔVOUT = 250 mV (5% of regulated 5 V). Using these numbers gives a minimum capacitance of 34 µF. A standard
4 x 22 µF ceramic is chose in the design.
Co >
DIOUT 2 × L
Vout × DVout
(15)
The selection of COUT is driven by the effective series resistance (ESR). Equation 16 calculates the minimum
output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency,
ΔVOUT is the maximum allowable output voltage ripple, and ΔiL is the inductor ripple current. In this case, the
maximum output voltage ripple is 40 mV (1% of regulated 5 V). From Equation 16, the output current ripple is
1.7 A and the minimum output capacitance meeting the output voltage ripple requirement is 12.2 µF with 3-mΩ
ESR resistance.
1
1
Co >
×
D
V
8 × fsw
out
- esr
DiL
(16)
After considering both requirements, for this example, four 22-µF 6.3-V X7R ceramic capacitors with 3-mΩ of
ESR will be used. Equation 17 calculates the maximum ESR an output capacitor can have to meet the output
voltage ripple specification. Equation 17 indicates the ESR should be less than 23.5 mΩ. In this case, the
ceramic capacitors’ ESR is much smaller than 23.5 mΩ.
Voripple
£ Re sr
Iripple
(17)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, a 47-µF 6.3-V X5R ceramic capacitor with 3-mΩ of ESR is be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 18 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 18 yields
486 mA.
26
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Icorms =
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Vout × (Vinmax - Vout)
12 × Vinmax× L1× fSW
(18)
9.2.2.5 Input Capacitor Selection
A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These
capacitors should be connected as close as physically possible to the input terminals of the converters as they
handle the RMS ripple current shown in Equation 19. For this example, Iout = 6 A, Vout = 5 V, minimum Vin_min =
24 V. The input capacitors must support a ripple current of 2.4-A RMS.
Iinrms = Iout ×
Vout (Vinmin - Vout )
×
Vinmin
Vinmin
(19)
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 20. Using the design example values, Iout_max = 6 A, Cin = 22 µF, fsw = 500 kHz, yields
an input voltage ripple of 136 mV.
I
× 0.25
DVin = out max
Cin × fsw
(20)
To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used.
9.2.2.6 Soft-Start Capacitor Selection
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS65286 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor
value can be calculated using . The soft-start circuit requires 1 nF per around 0.109 ms to be connected at the
SS terminal. For the example circuit, the output capacitor value is 47 nF and the soft-start time is 5.1 ms. In
TPS65286, Iss is 5.5 µA and Vref is 0.6 V.
æ 0.6V ö
Tss = Css × ç
÷
è 5.5µA ø
(21)
9.2.2.7 Minimum Output Voltage
Due to the internal design of the TPS65286, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 22.
Vout min = Ontimemin × Fsmax(Vinmax + Iout min(RDS2min- RDS1min)) - Iout min(RL + RDS2min)
where
•
•
•
•
•
•
•
•
•
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (120 ns maximum)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS1min = minimum high side MOSFET on resistance (52 mΩ typical)
RDS2min = minimum low side MOSFET on resistance (27 mΩ typical)
RL = series resistance of output inductor
For the example circuit, Vin = 24V, Fs = 500 kHz, when Iout = 0 A, the minimum output voltage is 1.44 V
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9.2.2.8 Compensation Component Selection
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60° and 90°. The method presented here ignores the effects of the slope compensation that is internal to the
TPS65286. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the
cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 23 and Equation 24.
For Cout, use a derated value of 22.4 μF. Use Equation 25 and Equation 26 to estimate a starting point for the
closed loop crossover frequency fco. Then the required compensation components may be derived. For this
design example, fpmod is 12.9 kHz and fzmod is 2730 kHz. Equation 23 is the geometric mean of the modulator
pole and the ESR zero and Equation 24 is the geometric mean of the modulator pole and one half the switching
frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this
case, Equation 23Equation (22) yields 175 kHz and Equation 24 yields 55.7 kHz. The lower value is 55.7 kHz. A
slightly higher frequency of 60.5 kHz is chosen as the intended crossover frequency.
Iout
fpmod =
2 × p × Vout × Cout
(23)
Iout
fzmod =
2 × p × RESR × Cout
(24)
fco = fpmod× fzmod
(25)
fSW
fco = fpmod×
2
(26)
Now the compensation components can be calculated. First calculate the value for Rc which sets the gain of the
compensated network at the crossover frequency. Use Equation 27 to determine the value of RC.
2p × fc × Vo × Co
RC =
gM × Vref × gmps
(27)
Next calculate the value of CC. Together with RC, CC places a compensation zero at the modulator pole
frequency. Equation 28 to determine the value of C3.
R × Co
CC = L
RC
(28)
An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series
combination of R4 and C4. The pole frequency can be placed at the ESR zero frequency of the output capacitor
as given by Equation 24. Use Equation 29 to calculate the required capacitor value for Cb.
Re sr × Co
Cb =
RC
(29)
9.2.2.9 Auto-Retry Functionality of USB Switches
Some applications require that an over-current condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with external resistors and
capacitor shown in Figure 32. During a fault condition, nFAULT pulls low disabling the part. The part is disabled
when EN is pulled low, and nFAULT goes high impedance allowing CRETRY1/2 to be charged. The part reenables when the voltage on EN_SW reaches the turn-on threshold, and the auto-retry time is determined by the
resistor/capacitor time constant. The part will continue to cycle in this manner until the fault condition is removed.
28
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L1
4.7uH
+5V
10
USB1
SW_IN1
SW_IN2
LX
BST
nFAULT1
11
SW_OUT2
V7V
9
MODE/
SYNC
8
ENable
USB Data
7
2
1
GND
AGND
EN
USB2
C9
10uF
RSET2
VIN
28
SW_OUT1
C8
10uF
RSET1
6
27
USB Data
Cretry2
1uF
TPS65286
GND
26
R4
20K
R5
20K
R6
5.3N
12
SW_EN2
RLIM
R5
39N
Cretry1
1uF
13
COMP
GND
25
5
R2
10k
14
SW_EN1
4
24
C2
2.2nF
R3
0
C7
22uF
C6
22uF
FB
nFAULT2
FB
VIN
23
SS
3
C1
100pF
LX
LX
22
VIN
C1
47nF
R8
10
R7
10
C10
47nF
C5
82pF
R=0
C4
1uF
C3
22uF
Analog Ground
VIN
4.5V~28V
Power Ground
Figure 32. Auto Retry Functionality
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
Figure 33 shows how an external logic signal can drive EN_SW through RFAULT and maintain auto-retry
functionality. The resistor/capacitor time constant determines the auto-retry time-out period.
L1
4.7uH
+5V
Cretry1
1uF
R7
1MQ
external logic signal
13
SW_OUT1
11
SW_OUT2
10
external logic signal
USB Data
R8
1MQ
USB1
nFAULT1
SW_IN2
BST
LX
SW_IN1
SW_EN2
12
R5
39N
R6
5.3N
RSET1
C8
10uF
V7V
EN
9
MODE/
SYNC
8
ENable
C9
10uF
USB Data
7
1
GND
AGND
USB2
RSET2
6
28
14
TPS65286
GND
27
RLIM
5
26
SW_EN1
GND
25
C7
22uF
FB
COMP
VIN
R4
20K
R5
20K
R2
10k
4
24
C2
2.2nF
R3
0
C6
22uF
Cretry2
1uF
nFAULT2
FB
VIN
23
3
C1
100pF
SS
VIN
22
2
C1
47nF
LX
LX
C10
47nF
C5
82pF
R=0
VIN
4.5V~28V
C3
22uF
C4
1uF
Analog Ground
Power Ground
Figure 33. Auto Retry Functionality With External Enable Signal
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9.2.3 Application Performance Plots
TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
VIN
VIN
VOUT
VOUT
EN
EN
SS
SS
Figure 34. Buck Start Up by EN Terminal With an
External 47-nF SS Capacitor
Figure 35. Buck Start Up by EN Terminal With Internal
Soft-Start (SS terminal Open)
VIN
VIN
VOUT
VOUT
EN
EN
SS
SS
Figure 37. Ramp VIN to Power Down Buck With an
External 22-nF SS Capacitor
Figure 36. Ramp VIN to Start Up Buck With an
External 22-nF SS Capacitor
VOUT Ripple
VOUT Ripple
LX
LX
ILX
ILX
Figure 38. Buck Output Voltage Ripple,
IOUT = 0.1-A PSM Mode
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Figure 39. Buck Output Voltage Ripple,
IOUT = 0-A PWM Mode
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TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
VOUT Ripple
VOUT Ripple
LX
IOUT
ILX
Figure 40. Buck Output Voltage Ripple, IOUT = 4 A
Figure 41. Buck Output Load Transient in PSM Mode,
IOUT = 0 - 2 A
VOUT Ripple
VOUT Ripple
IOUT
IOUT
Figure 42. Buck Output Load Transient in PWM Mode,
IOUT = 0 - 2 A
Figure 43. Buck Output Load Transient in PWM Mode,
IOUT = 2 - 4 A
VOUT
VOUT
LX
LX
ILX
ILX
Figure 44. Buck Hiccup Response to Hard Short Circuit
Figure 45. Buck Output Hard Short Response (Zoom In)
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TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
CLOCK
CLOCK
LX
LX
Figure 46. Clock Synchronization Operation
SW_IN1
SW_IN2
SW_OUT1
SW_OUT2
SW_EN1
SW_EN2
nFAULT1
nFAULT2
Figure 48. Power Switch1 Turn on Delay and Rise Time
Figure 49. Power Switch2 Turn on Delay and Rise Time
SW_IN1
SW_IN2
SW_OUT1
SW_OUT2
SW_EN1
SW_EN2
nFAULT1
nFAULT2
Figure 50. Power Switch1 Turn off Delay and Fall Time,
ROUT = 50 Ω, COUT = 10 µF
32
Figure 47. Clock Synchronization at 1 MHz
Figure 51. Power Switch2 Turn off Delay and Fall Time,
ROUT = 50 Ω, COUT = 10 µF
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TA = 25°C, VIN = 24 V, VOUT = 5 V, fSW = 500 kHz, RnFAULT = 100 kΩ (unless otherwise noted)
SW_IN1
SW_IN2
SW_OUT1
SW_OUT2
nFAULT1
nFAULT2
IOUT1
IOUT2
Figure 52. Power Switch1 Enable into Short Circuit
Figure 53. Power Switch2 Enable into Short Circuit
SW_IN1
SW_IN2
SW_OUT1
SW_OUT2
nFAULT1
nFAULT2
IOUT1
IOUT2
Figure 54. Power Switch1 Current Limit Operation
Figure 55. Power Switch2 Current Limit Operation
SW_OUT1
SW_OUT2
SW_IN1
SW_IN2
nFAULT1
nFAULT2
IOUT1
IOUT2
Figure 56. Power Switch1 Reverse Voltage Protection
Response
Figure 57. Power Switch2 Reverse Voltage Protection
Response
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10 Power Supply Recommendations
The total power dissipation inside TPS65286 should not to exceed the maximum allowable junction temperature
of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (θJA)
and ambient temperature. The analysis below gives an approximation in calculating junction temperature based
on the power dissipation in the package. However, it is important to note that thermal analysis is strongly
dependent on additional system level factors. Such factors include air flow, board layout, copper thickness and
surface area, and proximity to other devices dissipating power. Good thermal design practice must include all
system level factors in addition to individual component analysis.
To calculate the temperature inside the device under continuous load, use the following procedure.
1. Define the total continuous current through buck converter (including the load current through power
switches). Make sure the continuous current does not exceed maximum load current requirement.
2. From the graphs below, determine the expected losses (Y axis) in watts for buck converter inside the device.
The loss PD_BUCK depends on the input supply and the selected switching frequency.
3. Determine the load current IOUT1 and IOUT2 through the power switches. Read RDS(on)1/2 of power switch from
the typical characteristics graph.
4. The power loss through power switches can be calculated by PD_PW = RDS1(on) × IOUT1 + RDS2(on) × IOUT2.
5. The Dissipating Rating Table provides the thermal resistance θJA for specific packages and board layouts.
6. To calculate the maximum temperature inside the IC, use the following formula.
TJ = (PD_BUCK + PD_PW ) × θJA + TA
where
•
•
•
•
34
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C/W)
PD_BUCK = Total power dissipation in buck converter (W)
PD_PW = Total power dissipation in power switches (W)
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4.5
4.0
4.0
3.5
3.0
Power Loss (W)
Power Loss (W)
3.5
3.0
2.5
2.0
1.5
2.5
2.0
1.5
1.0
1.0
5V
2.5V
1.2
0.5
0.0
0.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Loading (A)
5V
2.5V
1.2V
0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Loading (A)
C016
C015
Figure 58. Power Dissipation of TPS65286,
VIN = 24 V
Figure 59. Power Dissipation of TPS65286,
VIN = 12 V
Figure 60. Thermal Signature of TPS65286EVM,
TA = Room Temperature, VIN = 24 V,
VOUT to VSW_in = 5 V/0 A, ISW_OUT1/2 = 1.2 A
EVM Board: 4-Layer PCB, 1.6 mm Thickness, 2 oz. Copper
Thickness, 65-mm x 65-mm Size, 25 Vias at Thermal Pad
Figure 61. Thermal Signature of TPS65286EVM,
TA = Room Temperature, VIN = 24 V, VOUT = 5 V/5 A,
ISW_OUT1/2 = 0 A
EVM Board: 4-Layer PCB, 1.6 mm Thickness, 2 oz. Copper
Thickness, 65-mm x 65-mm Size, 25 Vias at Thermal Pad
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11 Layout
11.1 Layout Guidelines
When laying out the printed circuit board, the following guideline should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the layout diagram of Figure 62.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. This capacitor provides the AC current into the internal power
MOSFETs. Connect the (+) terminal of the input capacitor as close as possible to the VIN terminal, and
Connect the (-) terminal of the input capacitor as close as possible to the PGND terminal. Care should be
taken to minimize the loop area formed by the bypass capacitor connections, the VIN terminals, and the
power ground PGND connections.
• Since the LX connection is the switching node, the output inductor should be located close to the LX terminal,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching
node, LX, away from all sensitive small-signal nodes.
• Connect V7V decoupling capacitor connected close to the IC, between the V7V and the power ground PGND
terminal. This capacitor carries the MOSFET drivers’ current peaks.
• Place the output filter capacitor of buck converter close to SW_IN terminals. Try to minimize the ground
conductor length while maintaining adequate width.
• AGND terminal should be separately routed to the (-) terminal of V7V bypass capacitor to avoid switching
grounding path. A ground plane is recommended connecting to this ground path.
• The compensation should be as close as possible to the COMP terminals. The COMP and ROSC terminals
are sensitive to noise so the components associated to these terminals should be located as close as
possible to the IC and routed with minimal lengths of trace. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of power components. You can connect the copper
areas to PGND, AGND, VIN or any other DC rail in your system.
• There is no electric signal internal connected to thermal pad in the device. Nevertheless connect exposed pad
beneath the IC to ground. Always solder thermal pad to the board, and have as many vias as possible on the
PCB to enhance power dissipation.
36
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11.2 Layout Example
VOUT_BUCK
output inductor
boot capacitor
nFAULT1
Top Side
Power
Ground
Area
nFAULT2
nFAULT2
FB
SW_EN1
COMP
SW_EN2
AGND
MODE/SYNC
V7V
SW_OUT2
power switch
output capacitor
PGND
EN
PGND
RSET2
PGND
SW_OUT1
SW_OUT2
VIN
SW_OUT1
REST1
VIN
RLIM
VIN
AGND
SW_IN2
Top Side
Analog
Ground
Area
SW_IN1
BST
LX
LX
LX
SS
output
capacitor
nFAULT1
Top Side
Power
Ground
Area
Input bypass capacitor
VIN
PGND
Thermal VIA
Signal VIA
Figure 62. 4-Layers PCB Layout Recommendation Diagram
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Product Folder Links: TPS65286
37
TPS65286
SLVSCG1 – MARCH 2014
www.ti.com
12 Device and Documentation Support
12.1 Trademarks
WEBENCH is a registered trademark of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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Product Folder Links: TPS65286
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65286RHDR
ACTIVE
VQFN
RHD
28
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65286
TPS65286RHDT
ACTIVE
VQFN
RHD
28
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65286
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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