CYRF69313-40LTXC

CYRF69313 Programmable Radio-on-Chip LPstar Programmable Radio-on-Chip LPstar Features Simple Development ■ Radio System-on-Chip, with built-in 8-bit MCU in a single device. ■ Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz). ■ On Air compatible with second WirelessUSB™ LP and PRoC LP. ■ Pin-to-pin compatible with PRoC LP except the pin 31 and pin 37. generation radio Intelligent ■ Auto transaction sequencer (ATS): MCU can stay sleeping longer to save power ■ Framing, length, CRC16, and Auto ACK ■ Separate 16 byte transmit and receive FIFOs ■ Receive signal strength indication (RSSI) ■ Built-in serial peripheral interface (SPI) control while in sleep mode ■ Advanced development tools based on Cypress’s PSoC® Tools ■ Flexible I/O ■ 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins ■ Each GPIO pin supports high impedance inputs, configurable pull-up, open-drain output, CMOS/TTL inputs, and CMOS output ■ Maskable interrupts on all I/O pins ■ M8C based 8-bit CPU, optimized for human interface devices (HID) applications ■ 256 bytes of SRAM ■ 8 Kbytes of flash memory with EEPROM emulation ■ In-System reprogrammable through D+/D– pins ■ CPU speed up to 12 MHz ■ 16-bit free running timer ■ Low power wakeup timer ■ Low external component count ■ 12-bit programmable interval timer with interrupts ■ Small footprint 40-pin QFN (6 mm × 6 mm) ■ Watchdog timer ■ GPIOs that require no external components ■ Operates off a single crystal ■ Integrated 3.3 V regulator ■ Integrated pull-up on D– BOM Savings Low Power ■ 21 mA operating current (Transmit at –5 dBm) ■ Sleep current less than 1 µA ■ Operating voltage from 4.0 V to 5.25 V DC ■ Fast startup and fast channel changes ■ Conforms to USB specification version 2.0 ■ Supports coin-cell operated applications ■ Conforms to USB HID specification version 1.1 ■ Supports one low speed USB device address ■ Supports one control endpoint and two data end points ■ Integrated USB transceiver USB Specification Compliance Reliable and Robust ■ Receive sensitivity typical –90 dBm ■ AutoRate™ – dynamic data rate reception ❐ Enables data reception for any of the supported bit rates automatically. ❐ DSSS (250 Kbps), GFSK (1 Mbps) Applications ■ Wireless keyboards and mice ■ Operating temperature from 0 °C to 70 °C ■ Presentation tools ■ Closed-loop frequency synthesis for minimal frequency drift ■ Wireless gamepads ■ Remote controls ■ Toys ■ Fitness Cypress Semiconductor Corporation Document Number: 001-66503 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 21, 2014 CYRF69313 Logic Block Diagram 1ohm VIO VCC1 VCC2 VCC3 VBat0 VCC4 VBat1 VBat2 SCK nSS RST P1.2 / VReg VDD_MICRO MOSI Vbus RFbias RFp RFn P0_1,3,4,7 Microcontroller Function 4 P1_6:7 2 Radio Function IRQ/GPIO P1.5/MOSI MISO/GPIO P1.4/SCK P2_0:1 2 XOUT/GPIO P1.3/nSS 12MHz Document Number: 001-66503 Rev. *E VSS ..... GND GND RESV Xtal GND D+/D2 ....... Page 2 of 81 CYRF69313 Contents Functional Description ..................................................... 5 Functional Overview ........................................................ 5 2.4 GHz Radio Function .............................................. 5 USB Microcontroller Function ...................................... 5 Backward Compatibility ............................................... 5 Pinouts .............................................................................. 6 Pin Configuration ............................................................. 6 PRoC LPstar Functional Overview ................................. 7 Functional Block Overview .............................................. 8 2.4 GHz Radio ............................................................. 8 Frequency Synthesizer ................................................ 8 Baseband and Framer ................................................. 8 Packet Buffers ............................................................. 9 Auto Transaction Sequencer (ATS) ............................ 9 Interrupts ..................................................................... 9 Clocks .......................................................................... 9 GPIO Interface ............................................................ 9 Power-on Reset ......................................................... 10 Power Management .................................................. 10 Timers ....................................................................... 10 USB Interface ............................................................ 10 Low Noise Amplifier (LNA) and Received Signal Strength Indication (RSSI) ..................... 10 SPI Interface .................................................................... 10 Three-Wire SPI Interface ........................................... 10 Four-Wire SPI Interface ............................................. 11 SPI Communication and Transactions ...................... 11 SPI I/O Voltage References ...................................... 11 SPI Connects to External Devices ............................ 11 CPU Architecture ............................................................ 12 CPU Registers ................................................................. 13 Flags Register ........................................................... 13 Accumulator Register ................................................ 13 Index Register ........................................................... 13 Stack Pointer Register ............................................... 14 CPU Program Counter High Register ....................... 14 CPU Program Counter Low Register ........................ 14 Addressing Modes ......................................................... 15 Source Immediate ..................................................... 15 Source Direct ............................................................. 15 Source Indexed ......................................................... 15 Destination Direct ...................................................... 15 Destination Indexed ................................................... 16 Destination Direct Source Immediate ........................ 16 Destination Indexed Source Immediate .................... 16 Destination Direct Source Direct ............................... 16 Source Indirect Post Increment ................................. 17 Destination Indirect Post Increment .......................... 17 Instruction Set Summary ............................................... 18 Memory Organization ..................................................... 19 Flash Program Memory Organization ....................... 19 Data Memory Organization ....................................... 20 Flash .......................................................................... 20 SROM ........................................................................ 20 SROM Function Descriptions .................................... 21 Document Number: 001-66503 Rev. *E SROM Table Read Description ...................................... 24 Clocking .......................................................................... 25 Clock Architecture Description .................................. 26 CPU Clock During Sleep Mode ................................. 32 Reset ................................................................................ 32 Power-on Reset .............................................................. 34 Watchdog Timer Reset .............................................. 34 Sleep Mode ...................................................................... 34 Sleep Sequence ........................................................ 34 Wakeup Sequence .................................................... 35 Low Power in Sleep Mode ......................................... 35 Power-on Reset Control ................................................. 37 POR Compare State ................................................. 37 ECO Trim Register .................................................... 37 General-Purpose I/O Ports ............................................. 38 Port Data Registers ................................................... 38 GPIO Port Configuration ........................................... 39 GPIO Configurations for Low Power Mode ............... 43 Serial Peripheral Interface (SPI) .................................... 44 SPI Data Register ...................................................... 45 SPI Configure Register .............................................. 45 Timer Registers .............................................................. 47 Registers ................................................................... 47 Interrupt Controller ......................................................... 50 Architectural Description ........................................... 50 Interrupt Processing .................................................. 51 Interrupt Latency ....................................................... 51 Interrupt Registers ..................................................... 51 USB Transceiver ............................................................. 56 USB Transceiver Configuration ................................. 56 USB Serial Interface Engine (SIE) ................................. 56 USB Device ..................................................................... 57 Endpoint 0 Mode ....................................................... 58 Endpoint Data Buffers ............................................... 60 USB Mode Tables ........................................................... 61 Mode Column ............................................................ 61 Encoding Column ...................................................... 61 SETUP, IN, and OUT Columns ................................. 61 Details of Mode for Differing Traffic Conditions .......... 62 Register Summary .......................................................... 64 Radio Function Register Descriptions ......................... 66 Absolute Maximum Ratings .......................................... 67 DC Characteristics ......................................................... 67 RF Characteristics .......................................................... 69 AC Test Loads and Waveforms for Digital Pins .......... 70 AC Characteristics ......................................................... 71 Switching Waveforms .................................................... 72 Ordering Information ...................................................... 76 Ordering Code Definitions ......................................... 76 Package Handling ........................................................... 77 Package Diagrams .......................................................... 77 Acronyms ........................................................................ 79 Document Conventions ................................................. 79 Units of Measure ....................................................... 79 Document History Page ................................................. 80 Page 3 of 81 CYRF69313 Sales, Solutions, and Legal Information ...................... 81 Worldwide Sales and Design Support ....................... 81 Products .................................................................... 81 PSoC® Solutions ....................................................... 81 Cypress Developer Community ................................. 81 Technical Support ..................................................... 81 Document Number: 001-66503 Rev. *E Page 4 of 81 CYRF69313 Functional Description PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution. Communication between the microcontroller and the radio is via the SPI interface between both functions. Functional Overview The CYRF69313 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69313 is designed to implement low cost wireless systems operating in the worldwide 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz–2.4835 GHz). 2.4 GHz Radio Function The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data Document Number: 001-66503 Rev. *E rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. USB Microcontroller Function The microcontroller function is based on the powerful CYRF69313 microcontroller. It is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The microcontroller has up to 14 GPIO pins to support USB, PS/2 and other applications. Each GPIO port supports high impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. The microcontroller features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz ± 1.5%). The PRoC LPstar has up to 8 Kbytes of Flash for user’s firmware code and up to 256 bytes of RAM for stack space and user variables. Backward Compatibility The CYRF69313 IC is fully interoperable with the main modes of the second generation Cypress radio SoC namely the CYRF6936, CYRF69103 and CYRF69213. CYRF69313 IC device may transmit data to or receive data from a second generation device, or both. Page 5 of 81 CYRF69313 Pinouts Figure 1. 40-pin QFN pinout NC 31 33 P1.6 32 VIO 36 RST 34 37 P1.7 35 GND 39 VDD_1.8 VBAT0 40 P0.7 38 V CC Corner tabs P0.4 1 30 XOUT / GPIO XTAL 2 29 MISO / GPIO VCC 3 P0.3 4 P0.1 5 26 P1. 4 / SCK VBAT1 6 25 P1. 3 / SS VCC 7 24 P1. 2 P2.1 8 23 VDD_ Micro VBAT2 9 CYRF69313 PRoC LPstar 28 P1. 5 / MOSI 27 IRQ / GPIO 22 P1.1/D* E- PAD Bottom Side RFBIAS 10 21 P1.0/D+ 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP Pin Configuration Pin Name 1 P0.4 Function Individually configured GPIO 2 Xtal_in 3, 7, 16, 40 VCC 12 MHz Crystal. External clock in Connected to pin 24 via 0.047 F capacitor 4 P0.3 Individually configured GPIO 5 P0.1 Individually configured GPIO 6, 9, 39 Vbat Connected to pin 24 via 0.047 Fshunt capacitor 8 P2.1 GPIO. Port 2 Bit 1 10 RF Bias 11 RFp 12 GND Ground 13 RFn Differential RF to/from antenna 14, 17, 18, 20, 36 NC 15 P2.0 19 RESV RF pin voltage reference Differential RF input to/from antenna GPIO. Port 2 Bit 0 Reserved. Must connect to GND 21 P1.0 / D+ / GPIO 1.0 / Low speed USB I/O / ISSP-SCLK ISSP-SCLK 22 P1.1 / D– / GPIO 1.1 / Low speed USB I/O/ISSP-SDATA ISSP-SDATA 23 VDD_micro 24 P1.2 4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU Must be configured as 3.3 V output. It must have a 1–2 F output capacitor Document Number: 001-66503 Rev. *E Page 6 of 81 CYRF69313 Pin Configuration (continued) Pin Name Function 25 P1.3 / nSS Slave select SPI Pin 26 P1.4 / SCK Serial Clock Pin from MCU function to radio function 27 28 IRQ Interrupt output, configure high/low or GPIO P1.5 / MOSI Master Out Slave In 29 MISO Master In Slave Out, from radio function. Can be configured as GPIO 30 XOUT Bufferd CLK or GPIO 31 NC 32 P1.6 Must be floating GPIO. Port 1 Bit 6 33 VIO I/O interface voltage. Connected to pin 24 via 0.047 F 34 Reset Radio Reset. Connected to VDD via 0.47 F capacitor or to microcontroller GPIO pin. Must have a RESET = HIGH event the very first time power is applied to the radio otherwise the state of the radio function control registers is unknown 35 P1.7 36 VDD_1.8 37 GND Must be connected to ground 38 P0.7 GPIO. Port 0 Bit 7 E-pad Must be connected to GND 41 42 GPIO. Port 1 Bit 7 Regulated logic bypass. Connected via 0.47 F to GND Corner Tabs Do not connect corner tabs PRoC LPstar Functional Overview The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband performs Start of Frame (SOF), End of Frame (EOF) detection and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate Document Number: 001-66503 Rev. *E systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. The MCU function is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The instruction set has been optimized specifically for USB operations, although it can be used for a variety of other embedded applications. The MCU function has up to eight Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free-Running Timer, and 12-bit Programmable Interrupt Timer. The MCU function supports in-system programming by using the D+ and D– pins as the serial programming mode interface. The programming protocol is not USB. Page 7 of 81 CYRF69313 Functional Block Overview ■ All the blocks that make up the PRoC LPstar are presented here. 2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to 0 dBm transmit power, with an output power control range of 30 dB in six steps. The supply current of the device is reduced as the RF output power is reduced. Table 1. Internal PA Output Power Step Table PA Setting Typical Output Power (dBm) 6 0 5 –5 4 –10 3 –15 2 –20 1 –25 0 –30 In DSSS mode eight bits (8DR, 32 chip) are encoded in each derived code symbol transmitted, resulting in effective 250 Kbps data rate. 32 chip Pseudo Noise (PN) codes are supported. The two data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, DSSS reduce packet error rate in any environment. Link Layer Modes The CYRF69313 IC device supports the following data packet framing features: SOP Packets begin with a two-symbol SoP marker. If framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. Length Length field is the first eight bits after the SOP symbol, and is transmitted at the payload data rate. An EoP condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16. CRC16 Frequency Synthesizer The ‘fast channels’ (