ESD207B102ELE6327XTMA1

TVS Diode Transient Voltage Suppressor Diodes ESD207-B1-02 Series Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes ESD207-B1-02ELS ESD207-B1-02EL Data Sheet Revision 1.3, 2013-12-19 Final Power Management & Multimarket ESD207-B1-02 Series Revision History: Revision 1.2, 2013-11-15 Page or Item Subjects (major changes since previous revision) Revision 1.3, 2013-12-19 5 Table 2-2) updated Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 FinalData Sheet 2 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes 1 Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes 1.1 Features • • • • • • ESD / transient / surge protection of one data / Vbus line exceding standard: – IEC61000-4-2 (ESD): ±30 kV (air / contact discharge) – IEC61000-4-4 (EFT): ±50 A (5/50 ns) – IEC61000-4-5 (surge): ±8 A (8/20 μs) Bi-directional, symmetrical working voltage up to VRWM = ±3.3 V Medium capacitance: CL = 14 pF (typ.) Ultra low clamping voltage VCL = 7 V (typ.) @ IPP = 16 A (TLP) Ultra low dynamic resistance RDYN = 0.13 Ω typ. Pb-free (RoHS compliant) and halogen free package 1.2 • • Application Examples Audio Line, Speaker, Headset, Microphone Protection Human Interface Devices (Keyboard, Touchpad, Buttons) 1.3 Product Description Pin 1 Pin 2 Pin 1 marking (lasered) Pin 1 TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram P G-TS (S)LP -2_Dual_Diode_S erie_P inConf_and_S c hematic Diag. vs d Figure 1-1 Pin Configuration and Schematic Diagram Table 1-1 Ordering Information Type Package Configuration Marking code ESD207-B1-02ELS TSSLP-2-3 1 line, bi-directional Y ESD207-B1-02EL TSLP-2-19 1 line, bi-directional A FinalData Sheet 3 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 2 Characteristics Table 2-1 Maximum Ratings at TA = 25 °C, unless otherwise specified1) Parameter Symbol Values Unit Min. Typ. Max. VESD – – 30 kV IPP – – 8 A Peak pulse power (tp = 8/20 μs) PPK – – 65 W Operating temperature range TOP -40 – 125 °C Storage temperature Tstg -65 – 150 °C ESD contact discharge 2) Peak pulse current (tp = 8/20 μs) 3) 3) 1) Device is electrically symmetrical 2) VESD according to IEC61000-4-2 3) IPP according to IEC61000-4-5 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at TA = 25 °C, unless otherwise specified   

 
   

      







 
Figure 2-1 Definitions of electrical characteristics FinalData Sheet     4

 





             



         
                 !"#   Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics Table 2-2 DC Characteristics at TA = 25 °C, unless otherwise specified1) Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Reverse working voltage VRWM – – 3.3 V Reverse current IR – – 50 nA Trigger voltage Vt1 3.65 – – V Holding voltage Vh 3.65 4.4 – V IR = 10 mA Unit Note / Test Condition pF VR = 0 V, f = 1 MHz VR = 3.3 V 1) Device is electrically symmetrical Table 2-3 AC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Line capacitance Table 2-4 CL Values Min. Typ. Max. – 14 20 ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol 1) Clamping voltage Pin 1 to GND VCL 1) Clamping voltage GND to Pin 1 2) Clamping voltage Dynamic resistance 1) RDYN Values Unit Note / Test Condition V ITLP = 16 A Min. Typ. Max. – 7 – – 9 – ITLP = 30 A – 7.5 – ITLP = 16 A – 9 – ITLP = 30 A – 4.5 5.8 IPP = 1 A – 6.8 8.1 IPP = 8 A – 0.13 – Ω 1) ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 Ω, tp = 100 ns, tr , = 0.6 ns, ITLP and VTLP averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between ITLP1 = 5 A and ITLP2 = 40 A. Please refer to Application Note AN210 [1] 2) IPP according to IEC61000-4-5 (tp = 8/20 µs) FinalData Sheet 5 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 2.2 Typical Characteristics at TA = 25 °C, unless otherwise specified -5 10 -6 10 10-7 IR [A] 10-8 10-9 10-10 10-11 10 -12 -4 -3 -2 -1 0 VR [V] 1 2 3 4 Figure 2-2 Reverse current: IR = f(VR) 1000 IR [nA] 100 10 1 0.1 -50 -25 0 25 50 TA [°C] 75 100 125 Figure 2-3 Reverse current: IR = f(TA) , VR = 3.3 V FinalData Sheet 6 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 20 CL [pF] 15 10 5 -4 -3 -2 -1 0 VR [V] 1 2 3 4 Figure 2-4 Line capacitance: CL = f(VR), f = 1MHz FinalData Sheet 7 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 60 30 ESD207-B1-02series RDYN 50 25 40 20 30 15 20 10 10 5 0 0 -10 -5 -20 -10 Equivalent VIEC [kV] ITLP [A] RDYN = 0.13 Ω RDYN = 0.14 Ω -30 -15 -40 -20 -50 -25 -60 -20 -15 -10 -5 0 5 10 15 -30 20 VTLP [V] Figure 2-5 Clamping voltage (TLP): ITLP = f(VTLP) according ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 Ω, tp = 100 ns, tr = 0.6 ns, ITLP and VTLP averaging window: t1 = ns to t2 = 60 ns, extraction of dynamic resistance using squares fit to TLP characteristics between ITLP1 = 5 A and ITLP2 = 40 A. Please refer to Application Note AN210 [1] FinalData Sheet 8 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 11 10 ESD207-B1-02series RDYN 9 8 7 6 5 RDYN = 0.3 Ω 4 3 IPP [A] 2 1 0 -1 -2 -3 RDYN = 0.4 Ω -4 -5 -6 -7 -8 -9 -10 -11 -15 -10 -5 0 VCL [V] 5 10 15 Figure 2-6 Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL) FinalData Sheet 9 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 40 30 VCL-max-peak = 38.1 [V] VCL [V] 20 VCL-30ns-peak = 7.7 [V] 10 0 -10 -100 0 100 200 300 400 tp [ns] 500 600 700 800 900 700 800 900 Figure 2-7 IEC61000-4-2 : VCL = f(t), 8 kV positive pulse from pin 1 to pin 2 10 VCL [V] 0 -10 VCL-max-peak = -37.5 [V] -20 VCL-30ns-peak = -6.9 [V] -30 -40 -100 0 100 200 300 400 tp [ns] 500 600 Figure 2-8 IEC61000-4-2 : VCL = f(t), 8 kV negative pulse from pin 1 to pin 2 FinalData Sheet 10 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Characteristics 70 60 50 VCL [V] 40 VCL-max-peak = 61.3 [V] 30 VCL-30ns-peak = 8.3 [V] 20 10 0 -10 -20 -30 -100 0 100 200 300 400 tp [ns] 500 600 700 800 900 700 800 900 Figure 2-9 IEC61000-4-2 : VCL = f(t), 15 kV positive pulse from pin 1 to pin 2 30 20 10 VCL [V] 0 -10 -20 VCL-max-peak = -65.0 [V] -30 VCL-30ns-peak = -7.6 [V] -40 -50 -60 -70 -100 0 100 200 300 400 tp [ns] 500 600 Figure 2-10 IEC61000-4-2 : VCL = f(t), 15 kV negative pulse from pin 1 to pin 2 FinalData Sheet 11 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Application Information Application Information Audio_in Audio_out single ended Time ESD-strike PCB line Headset cable -Vcc +Vcc Charge Pump ESD Diode Audio Amp. ESD-strike Headset Ear-phone +Vcc Voltage 3 Headset con. e.g. 3.5mm jack E S D3V 3S1B -02LS_A pplic ation. v s d Figure 3-1 Single line, bi-directional ESD / Transient protection FinalData Sheet 12 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Package Information 4 Package Information 4.1 TSSLP-2-3 Top view Bottom view 0.31 +0.01 -0.02 0.32 ±0.05 0.355 0.62 ±0.05 2 Cathode marking 0.05 MAX. 0.26 ±0.035 0.2 ±0.035 1) 1 1) 1) Dimension applies to plated terminals TSSLP-2-3, -4-PO V01 Figure 4-1 TSSLP-2-3: Package overview (dimension in mm) 0.19 0.24 Solder mask 0.19 0.57 0.14 0.62 Copper 0.19 0.27 0.24 0.32 Stencil apertures TSSLP-2-3, -4-FP V02 Figure 4-2 TSSLP-2-3: Footprint (dimension in mm) g 0.35 Tape type Ex Ey Punched Tape 0.43 0.73 Embossed Tape 0.37 0.67 8 Ey 4 Cathode marking Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. Ex TSSLP-2-3, -4-TP V03 Figure 4-3 TSSLP-2-3: Tape information (dimension in mm) 1 Type code Cathode marking TSSLP-2-3, -4-MK V01 Figure 4-4 TSSLP-2-3: Marking (example) FinalData Sheet 13 Revision 1.3, 2013-12-19 ESD207-B1-02 Series Package Information 4.2 TSLP-2-19 Top view Bottom view 0.31 +0.01 -0.02 0.6 ±0.05 0.05 MAX. 1±0.05 0.65 ±0.05 2 0.25 ±0.035 1) 1 0.5 ±0.035 1) Cathode marking 1) Dimension applies to plated terminals TSLP-2-19, -20-PO V01 Figure 4-5 TSLP-2-19: Package outline(dimension in mm), proposal 0.35 0.28 0.38 0.93 0.3 1 Copper 0.28 0.45 0.35 0.6 Solder mask Stencil apertures TSLP-2-19, -20-FP V01 Figure 4-6 TSLP-2-19: Footprint (dimension in mm), proposal 0.4 1.16 Cathode marking 8 4 0.76 TSLP-2-19, -20-TP V02 Figure 4-7 TSLP-2-19: Tape information (dimension in mm), proposal Type code 12 Cathode marking TSLP-2-19, -20-MK V01 Figure 4-8 TSLP-2-19: Marking (example) FinalData Sheet 14 Revision 1.3, 2013-12-19 ESD207-B1-02 Series References References [1] Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP Characterization Methodology [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages FinalData Sheet 15 Revision 1.3, 2013-12-19 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG