IRS2505LTRPBF

SMPS µPFCTM IRS2505LPBF Boost PFC and SMPS Control IC Features             Description The IRS2505L is a control IC for PFC boost converters operating in critical-conduction mode. The IC incorporates a voltage feedback loop for output voltage regulation combined with smart zero crossing detection to control the gate drive output without the need for a secondary inductor winding. DC output over-voltage protection and cycle-by-cycle over-current protection are also included. Multi-functional inputs enable the IRS2505L to perform all functions with only 5 pins. Critical-conduction mode PFC control (CrCM) High PF and ultra-low THD Wide line and load range Regulated DC output voltage No secondary winding required Cycle-by-cycle over-current protection Output over-voltage protection Ultra-low start-up current 20.8V internal zener clamp on VCC Excellent ESD and latch immunity RoHS compliant 5-pin SOT-23 package Package Options Applications    Off-line power supply Electronic ballast LED power supply 5 Lead SOT23 Application Diagram Rect (+) DC Bus (+) CMP COM 2 VCC VCC (+) 3 VBUS IRS2505L 1 5 PFC 4 VCC (-) Rect (-) DC Bus (-) Ordering Information Base Part Number Package Type IRS2505LPBF 5L-SOT-23 1 Standard Pack Form Quantity Tape and Reel 3000 Orderable Part Number IRS2505LTRPBF 2016-02-17 IRS2505LPBF Qualification Information† Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant †† Industrial (per JEDEC JESD 47E) Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. ††† MSL1 SOT-23 (per IPC/JEDEC J-STD-020C) Class B (per JEDEC standard EIA/JESD22-A115-A) Class 2 (per EIA/JEDEC standard JESD22-A114-B) Class I, Level A (per JESD78A) Yes † †† Qualification standards can be found at the Infineon web site http://www.infineon.com Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for further information. 2 2016-02-17 IRS2505LPBF Functional Block Diagram VCC COM 3 2 VCLAMP UVLO OCP VBUS 5 VBUSREG OVP OTA VCC VBUSOV 4 CMP PFC 1 VCMPOH Watchdog Timer S Q R Q CT S VCOMPON Q R1 R2 Q ZX Detect 3 2016-02-17 IRS2505LPBF Timing Diagram PFC VCC VPFCOFF VPFCZX- t ILPFC t VDRAIN DC BUS t OFF-TIME 4 ON-TIME 2016-02-17 IRS2505LPBF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any pin. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VPFC VBUS ICC ICMP PD Rθja Tj Ts TL Definition PFC pin voltage VBUS pin voltage VCC pin supply current †† † CMP pin current Package power dissipation SOT-23 5L @ Ta  +25 ºC Thermal resistance, junction to SOT-23 5L ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. -0.3 -0.3 Max. VCC + 0.3 VCC + 0.3 Units --- 25 --- 1 --- 0.5 W --- 191 ºC/W -55 -55 --- 150 150 300 ºC V mA † This IC contains a voltage clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 20.8V. This supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. This IC contains a voltage clamp structure between the CMP and COM which has a †† nominal breakdown voltage of 10.2V. This pin should not be driven by a DC, low impedance power source greater than the VZCMP specified in the Electrical Characteristics section. 5 2016-02-17 IRS2505LPBF Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VCC ICC VCMP Tj Definition Supply voltage Supply current CMP pin voltage Junction temperature Min. Max. Units VCCUV+ + 0.5V VCLAMP V 0 0 10 VZCMP mA V -40 125 ºC Recommended Component Values Symbol CCMP CVCC Component Compensation capacitor value VCC filter capacitor CVBUS VBUS pin filter capacitor 6 Value 0.68 0.1 Units µF µF 1.0 nF 2016-02-17 IRS2505LPBF Electrical Characteristics VCC=14V, CVCC=0.1uF, CCMP=0.68uF, CPFC=1nF, CVBUS=10nF, and Ta=25°C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions Supply Characteristics VCLAMP VCC clamp voltage 19.8 20.8 21.8 VCCUV+ Rising VCC under-voltage threshold 10.0 11.1 12.0 VCCUV- Falling VCC under-voltage threshold 7.0 7.9 9.0 VCC UVLO hysteresis 2.9 3.2 3.5 Micro-power start-up VCC supply current --- 46.0 60.0 µA VCC = VCCUV+ - 500mV rising No switching --- 1.2 1.6 mA VCOMP=0V,GBD VCC current @ 50kHz --- 1.6 2.1 mA VCCUVHYS IQCCUV IQCC ICC50kHz ICC = 19 mA V PFC Characteristics tONMIN Minimum PFC On-time --- 0.9 --- tONMAX Maximum PFC On-time 51 68 86 VBUSREG VBUS Pin Regulation Voltage 4.02 4.1 4.18 VBUSOV+ VBUS Pin OVP Threshold VBUS Pin OVP Fault Reset Threshold VBUS Pin Over-Current Threshold 4.30 4.50 4.70 4.13 4.26 4.48 0.45 0.53 0.62 --- 300 --- 0.39 0.40 0.51 tOFFDLY Over-Current Blanking Time PFC Pin Zero-Crossing Arming Threshold PFC Pin Zero-Crossing Detection Threshold PFC Pin Off-Time Delay tZXBLNK PFC Pin Zero-Crossing Blank Time VBUSOVVBUSOC+ tOC VPFCZX+ VPFCZX- s V VBUS = 3V ns VPFC Rising, GBD V 0.39 0.40 0.51 --- 0.5 --- --- 0.5 --- VPFC Falling, GBD s tWD Watch Dog Timer Pulse Interval 100 140 180 ICMP+ CMP Pin OTA IO+ 25 33 40 ICMP- CMP Pin OTA IOOTA Output Voltage Swing (high state) OTA Output Voltage Swing (low state) Minimum COMP Voltage for Switching OTA Output Voltage in Fault Mode -40 -33 -25 9.9 10.2 11.5 VBUS=3.5V --- 0 --- VBUS=4.5V 1.21 1.50 1.83 --- 0 --- 9.9 10.2 11.5 VCMPOH VCMPOL VCMPON VCMPFLT VZCMP CMP Pin Clamp Voltage A VBUS=3.5V,VCMP=0V VBUS=4.5V,VCMP=5V V VBUS=3.5V GBD : Guaranteed by design 7 2016-02-17 IRS2505LPBF Electrical Characteristics VCC=14V, CVCC=0.1uF, CCMP=0.68uF, CPFC=1nF, CVBUS=10nF, and Ta=25°C unless otherwise specified. Gate Driver Output Characteristics (PFC) VPFCON Gate High Voltage --- 13.0 --- VPFCOFFI Gate Low Voltage during initial switch off period --- --- 0.1 VPFCOFF Gate Low Voltage (after initial switch off) 0.50 0.59 0.63 Gate initial switch off pull down time --- 500 --- tr Output rise time --- 135 220 tf Output fall time --- 20 35 IO+ Output source current --- 50 --- IO- Output sink current --- 450 --- tPD 8 V ns Rising, 10% to 70% Falling, 80% to 20% mA 2016-02-17 IRS2505LPBF Pin Assignments and Definitions CMP COM 2 VCC 3 5 IRS2505 1 VBUS PFC 4 Pin Name 1 CMP PFC error amplifier compensation 2 COM IC power and signal ground 3 VCC Logic and gate drive supply voltage 4 PFC PFC gate driver output and zero-crossing detection 5 VBUS 9 Description DC bus sensing input, OVP and OCP 2016-02-17 IRS2505LPBF Functional Description The following topics are described in more detail below: 1) 2) 3) 4) 5) PFC Control Circuit Multi-Function PFC Pin On-Time Modulation Over-Voltage Protection (OVP) Over-Current Protection (OCP) The IRS2505L is primarily intended for but not limited to pre-regulator PFC Boost converter front end stages in general power supplies and lighting applications such as LED power supplies, fluorescent and HID ballasts. The IRS2505L may also be used in other converter topologies such as Buck, Buck-Boost and Flyback, where its small size and functionality can offer simplicity and cost advantage. It can also be used in converters where PFC is not required. 1. PFC Control Circuit The IRS2505 is a high frequency SMPS PWM controller designed for Boost PFC pre-regulators operating in critical-conduction mode (CrCM), also known as transition (TM) or boundary mode (BM). The PFC Boost converter provides a regulated high voltage DC output over a range of AC line input voltage and load, while at the same time shaping the input current so that it follows the sinusoidal profile of the voltage resulting in high power factor and low total harmonic distortion (THD). Figure 1 shows the main elements of the PFC Boost converter; the input capacitor (CIN) is for high frequency bypass and does not provide smoothing at low frequency under steady state operation. When a load is connected at the output the rectified input voltage across CIN is full wave rectified. During the on-time of the PFC MOSFET (MPFC), the IRS2505 gate drive output (PFC) is high so the inductor (LPFC) current ramps up linearly to a peak current value. During the off-time the gate drive output is low and the inductor current linearly discharges back down to zero at which point MPFC is turned on again. The control loop response has to be slow compared to the line frequency so that the on time remains effectively constant over a single line half cycle; except for some gradual increase as the voltage approaches the zero crossings, which improves THD. The off time varies during the AC line half cycle being longest at the peak. LPFC DPFC (+) Rectified AC Line Input (-) CIN MPFC DC BUS (+) ILPFC CBUS (-) t ON-TIME OFF-TIME Figure 1: Boost-type converter and inductor current during critical-conduction mode. The result is a triangular shaped inductor current that varies in frequency depending on the level of the instantaneous rectified AC line voltage shown in figure 2. The maximum switching frequency occurs at the zerocrossings of the rectified AC line voltage and the minimum at the peak of the rectified AC line voltage. The average inductor current is equal to half of the peak, which is equal to the instantaneous line input current after the high frequency elements have been filtered out. 10 2016-02-17 IRS2505LPBF V, I AC Line Voltage Inductor Current AC Line Current time Cross-over distortion Figure 2: PFC inductor current during the rectified AC line voltage cycle. The IRS2505 internal control circuit blocks shown in figure 3 include; the feedback error amplifier controlling on-time via timing capacitor (CT), zero-crossing (ZX) detection and off-time control, gate drive output, over-voltage protection (OVP) and over-current protection (OCP). The PFC pin is a multi-function input/output pin used for driving the external PFC MOSFET gate and also for sensing the PFC inductor current zero-crossing during the off-time. The VBUS pin is also a multi-function pin used for monitoring the DC bus voltage through an external divider network and also measuring the MOSFET (MPFC) source current. An internal OTA compares the voltage feedback with an accurate internal voltage reference (VBUSREG) to control the CMP pin voltage by charging and discharging the external compensation capacitor (CCMP). The voltage level at the CMP pin determines the on-time to control power transfer to the output. The MOSFET current is measured with a current-sensing resistor and then AC-coupled onto the VBUS pin through an external series resistor and capacitor. RECT (+) VBUS (+) VCC (+) 3 9...19.8V OCP UVLO (-) VBUS 2 OVP COM + OFF Time PFC 4 5 4.1V PFC Logic ON Time CMP 1 CT RECT (-) VBUS (-) Figure 3: PFC control circuitry 11 2016-02-17 IRS2505LPBF 2. PFC Multi-Function Pin The multi-function PFC pin performs the following two functions: 1) PFC gate drive output. 2) PFC inductor current zero-crossing detection. During each switching cycle illustrated in figure 4, at the beginning of each cycle the PFC pin gate drive output pulls the PFC pin voltage high to approximately VCC-1V and the external PFC MOSFET turns on; the on-time duration is set by the CMP pin voltage. The internal PFC control loop steers the CMP pin voltage to control the ontime such that if the DC bus voltage increases then the CMP pin voltage and on-time will decrease. This will decrease the peak inductor current each switching cycle transferring less energy and causing the DC bus voltage to decrease. If the DC bus voltage decreases, then the CMP pin voltage and on-time will increase having the opposite effect. This negative feedback control regulates the DC bus to a constant voltage over AC line voltage or output load variations. The speed of the control loop is determined by the internal OTA trans-conductance and compensation capacitor CCMP. At the end of each on time period, the PFC pin gate drive circuit pulls the PFC pin to COM and the external PFC MOSFET turns off. After a short initial switch off delay (tPD), the internal gate drive pull-down turns off and the PFC pin is then weakly pulled up and clamped at approximately one diode forward voltage drop (VPFCOFF), which is well below the gate threshold of the MOSFET (MPFC) ensuring that it will not begin to switch on. During the off-time the PFC inductor current discharges through the boost diode into the DC output capacitor and load. When the inductor current falls to zero, the drain voltage falls from the level of the output voltage plus the output diode forward voltage and transitions negatively. During this transition current flows through the MOSFET parasitic gate to drain capacitance CGD overcoming the internal weak pull up and causing the gate voltage to drop below the threshold VPFCZX-. After remaining below this threshold for a period of tZXBLANK, the PFC gate drive will be turned on again to start the next switching cycle and so the sequence repeats. To ensure ZX detection, a minimum voltage headroom is needed between the peak line voltage at high line and the output voltage. This value depends on the MOSFET C GD, a value of 60-70V is typical. To operate with a smaller headroom 500V minimum rated capacitor around 100pF may be added between drain and source. PFC VCC VPFCOFF VPFCZX- t ILPFC t VDRAIN DC BUS t OFF-TIME ON-TIME Figure 4: PFC timing diagram. 12 2016-02-17 IRS2505LPBF 3. PFC On-Time Modulation Fixed on-time over the entire half cycle of the line input voltage produces a peak inductor current that naturally follows the sinusoidal shape of the line input voltage. The filtered, averaged line input current is in phase with the line input voltage to provide high power factor. However some harmonic distortion of the current is still present mostly due to cross-over distortion occurring near the zero-crossings of the line input voltage as shown in figure 2. To achieve very low harmonics within the limits of international standards and to meet general market requirements, an additional on-time modulation function is included in the IRS2505L, which dynamically increases the on-time as the line input voltage nears the zero-crossings. As illustrated in figure 5, the peak LPFC current and therefore the smoothed line input current increase slightly higher near the zero-crossings of the line input voltage. This reduces the amount of cross-over distortion in the line input current and improves the shape of the current reducing the THD and harmonics to low levels. ILPFC PFC pin near peak region of rectified AC line near zero-crossing region of rectified AC line Figure 5: PFC on-time modulation. 4. DC Bus Over-Voltage Protection (OVP) The VBUS pin includes output over-voltage protection (OVP). Should the VBUS pin feedback voltage exceed the internal over-voltage protection threshold (VBUSOV+) then the PFC gate drive will turn off until the VBUS pin voltage again falls below the over-voltage restart threshold (VBUSOV-) to resume normal operation. 13 2016-02-17 IRS2505LPBF 5. Over-Current Protection (OCP) As well as sensing the output voltage feedback, the VBUS input also includes a cycle-by-cycle, AC-coupled, over-current protection (OCP) function. The external network required to combine these two inputs is shown in figure 6. The high-frequency ramp shaped voltage produced across the current-sensing resistor (RCS) is coupled onto the VBUS feedback with an external series resistor (R1) and capacitor (C1) as shown in figure 7. An internal over-current protection circuit detects the difference between the peak and average of the combined signal so that if the triangularshaped voltage peak at the VBUS input exceeds VBUSREG by VBUSOC+ the gate drive is immediately driven low. The capacitor CVBUS is added to make the current sense signal more triangular so that its peak value will be close to half its average. The OCP function will safely limit the peak current in each switching cycle to prevent MOSFET damage during low AC line conditions, overload or during fast mains voltage interrupts. It should be remembered that in any Boost converter it is not possible to incorporate full output current control or short circuit protection by controlling the switching of MPFC. Shorting the output should be avoided as it will short the input and blow a fuse! DC Bus Voltage Boost Switching Node RBUS1 C1 MPFC R1 VBUS 5 CVBUS COM VCS RBUS2 RCS 2 Figure 6: AC-coupled over-current protection circuit. VCS t VBUS VBUSOC+ DC Offset (from DC bus measurement) t PFC t Normal Mode OCP Mode Figure 7: OCP circuit timing diagram. 14 2016-02-17 IRS2505LPBF Package Details: 5 Lead SOT23 15 2016-02-17 IRS2505LPBF Tape and Reel Details: 5 Lead SOT23 16 2016-02-17 IRS2505LPBF Tape and Reel Details: 5 Lead SOT23 17 2016-02-17 IRS2505LPBF Part Marking Information: 5 Lead SOT23 Top Marking YW LC Lot Code Date Code Bottom Marking B IR Logo Part no. 18 2016-02-17 IRS2505LPBF Revision History Major changes since the last revision Date June 20, 2013 September 2, 2015 February 17, 2016 Description of change First Release Updated block diagram and functional description. Added test limits for multiple parameters. Added blanking time for cycle by cycle over-current protection Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2015 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 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Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 19 2016-02-17