IS31FL3235
28 CHANNELS LED DRIVER
October 2021
GENERAL DESCRIPTION
FEATURES
IS31FL3235 is comprised of 28 constant current
channels each with independent PWM control,
designed for driving LEDs. The output current of each
channel can be set at up to 38mA (Max.) by an external
resistor and independently scaled by a factor of 1, 1/2,
1/3 and 1/4. The average LED current of each channel
can be changed in 256 steps by changing the PWM
duty cycle through an I2C interface.
The chip can be turned off by pulling the SDB pin low or
by using the software shutdown feature to reduce
power consumption.
IS31FL3235 is available in QFN-36 (4mm × 4mm)
package. It operates from 2.7V to 5.5V over the
temperature range of -40°C to +85°C.
2.7V to 5.5V supply
I2C interface, automatic address increment
function
Internal reset register
Modulate LED brightness with 256 steps PWM
Each channel can be controlled independently
Each channel can be scaled independently by 1,
1/2, 1/3 and 1/4
ESD HBM 8kV
-40°C to +85°C temperature range
QFN-36 (4mm × 4mm) package
APPLICATIONS
Mobile phones and other hand-held devices for
LED display
LED in home appliances
TYPICAL APPLICATION CIRCUIT
Figure 1
Typical Application Circuit
Note 1: The maximum global output current is set up to 23mA when REXT= 3.3kΩ. The maximum global output current can be set by external
resistor, REXT. Please refer to the detail information in Page 10.
Note 2: The IC should be placed far away from the mobile antenna in order to prevent the EMI.
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Rev. E, 10/21/2021
1
IS31FL3235
PIN CONFIGURATION
28 OUT28
29 SDB
30 AD
31 VCC
32 GND
33 R_EXT
34 SDA
OUT6 5
23 OUT23
OUT7 6
22 OUT22
OUT8 7
21 OUT21
OUT9 8
20 OUT20
OUT10 9
19 OUT19
OUT18 18
24 OUT24
OUT17 17
OUT5 4
OUT16 16
25 OUT25
OUT15 15
OUT4 3
GND 14
26 OUT26
OUT14 13
OUT3 2
OUT13 12
27 OUT27
OUT12 11
OUT2 1
OUT11 10
QFN-36
35 SCL
Pin Configuration (Top View)
36 OUT1
Package
PIN DESCRIPTION
No.
Pin
Description
1 ~ 13
OUT2 ~ OUT14
Output channel 2~14 for LEDs.
14，32
GND
Ground.
15 ~ 28
OUT15 ~ OUT28
Output channel 15~28 for LEDs.
29
SDB
Shutdown the chip when pulled low.
30
AD
I2C address setting.
31
VCC
Power supply.
33
R_EXT
Input terminal used to connect an external resistor.
This regulates the global output current.
34
SDA
I2C serial data.
35
SCL
I2C serial clock.
36
OUT1
Output channel 1 for LEDs.
Thermal Pad
Connect to GND.
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IS31FL3235
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Order Part No.
Package
QTY/Reel
IS31FL3235-QFLS2-TR
QFN-36, Lead-free
2500
Copyright © 2021 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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Rev. E, 10/21/2021
3
IS31FL3235
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at SCL, SDA, SDB, OUT1 to OUT28
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA
Package thermal resistance (Mounted on JEDEC standard 4
layer(2s2p) PCB test board), θJA
ESD (HBM)
ESD (CDM)
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~ +150°C
-40°C ~ +85°C
32.9°C/W
±8kV
±1kV
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Typical values are TA = 25°C, VCC = 3.6V.
Symbol
Parameter
Condition
Min.
Typ.
Unit
5.5
V
VCC
Supply voltage
IMAX
Maximum global output current
VCC = 4.2V, VOUT = 0.8V
REXT = 2kΩ, SL = “00” (Note 1)
38
mA
IOUT
Output current
VOUT = 0.6V
REXT = 3.3kΩ, SL = “00”
23
mA
ICC
Quiescent power supply current
REXT = 3.3kΩ
9
mA
ISD
Shutdown current
VSDB = 0V or software shutdown
TA = 25°C, VCC = 3.6V
IOZ
Output leakage current
VSDB = 0V or software shutdown,
VOUT = 5.5V
VEXT
2.7
Max.
2
Output voltage of R-EXT pin
3
5
μA
0.2
μA
1.3
V
Logic Electrical Characteristics (SDA, SCL, SDB)
VIL
Logic “0” input voltage
VCC = 2.7V
VIH
Logic “1” input voltage
VCC = 5.5V
IIL
Logic “0” input current
VINPUT = 0V
5
(Note 2)
nA
IIH
Logic “1” input current
VINPUT = VCC
5
(Note 2)
nA
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Rev. E, 10/21/2021
0.4
1.4
V
V
4
IS31FL3235
DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
400
kHz
fSCL
Serial-Clock frequency
tBUF
Bus free time between a STOP and a START
condition
1.3
μs
tHD, STA
Hold time (repeated) START condition
0.6
μs
tSU, STA
Repeated START condition setup time
0.6
μs
tSU, STO
STOP condition setup time
0.6
μs
tHD, DAT
Data hold time
tSU, DAT
Data setup time
100
ns
tLOW
SCL clock low period
1.3
μs
tHIGH
SCL clock high period
0.7
μs
0.9
μs
tR
Rise time of both SDA and SCL signals,
receiving
(Note 3)
20+0.1Cb
300
ns
tF
Fall time of both SDA and SCL signals,
receiving
(Note 3)
20+0.1Cb
300
ns
Note 1: The recommended minimum value of REXT is 2kΩ, or it may cause a large current.
Note 2: Guaranteed by design.
Note 3: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC.
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IS31FL3235
DETAILED DESCRIPTION
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
I2C INTERFACE
The IS31FL3235 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3235 has a 7-bit slave
address (A7:A1), followed by the R/W bit, A0. Since
IS31FL3235 only supports write operations, A0 must
always be “0”. The value of bits A1 and A2 are decided
by the connection of the AD pin.
After the last bit of the chip address is sent, the master
checks for the IS31FL3235’s acknowledge. The
master releases the SDA line high (through a pull-up
resistor). Then the master sends an SCL pulse. If the
IS31FL3235 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the SDA
line is not low, then the master should send a “STOP”
signal (discussed later) and abort the transfer.
The complete slave address is:
Table 1 Slave Address (Write Only):
Bit
A7:A3
A2:A1
A0
Value
01111
AD
0
Following acknowledge of IS31FL3235, the register
address byte is sent, most significant bit first.
IS31FL3235 must generate another acknowledge
indicating that the register address has been received.
AD connected to GND, AD = 00;
AD connected to VCC, AD = 11;
AD connected to SCL, AD = 01;
AD connected to SDA, AD = 10;
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3235 must generate another acknowledge to
indicate that the data was received.
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31FL3235.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
ADDRESS AUTO INCREMENT
To write multiple bytes of data into IS31FL3235, load
the address of the data register that the first data byte
is intended for. During the IS31FL3235 acknowledge of
receiving the data byte, the internal address pointer will
increment by one. The next data byte sent to
IS31FL3235 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS31FL3235
(Figure 5).
The timing diagram for the I2C is shown in Figure 2.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
Figure 2
Interface timing
Figure 3
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Bit transfer
6
IS31FL3235
Figure 4
Figure 5
Writing to IS31FL3235 (Typical)
Writing to IS31FL3235 (Automatic address increment)
REGISTERS DEFINITIONS
Table 2 Register Function
Address
00h
Name
Function
Table
Shutdown Register
Set software shutdown mode
3
PWM Register
28 channels PWM duty cycle data register
4
Update Register
Load PWM Register and LED Control Register’s
data
-
LED Control Register
Channel 1 to 28 enable bit and current setting
5
4Ah
Global Control Register
Set all channels enable
6
4Fh
Reset Register
Reset all registers into default value
-
05h~20h
25h
2Ah~45h
0000 0000
xxxx xxxx
0000 0000
xxxx xxxx
Table 4 05h~20h PWM Register (OUT1~OUT28)
Table 3 00h Shutdown Register
Bit
D7:D1
D0
Bit
D7:D0
Name
-
SSD
Name
PWM
Default
0000000
0
Default
0000 0000
The Shutdown Register sets software shutdown mode
of IS31FL3235.
SSD
0
1
Default
Software Shutdown Enable
Software shutdown mode
Normal operation
The PWM Registers adjusts LED luminous intensity in
256 steps.
The value of a channel’s PWM Register decides the
average output current for each output, OUT1~OUT28.
The average output current may be computed using
the Formula (1):
I PWM
I OUT 7
D[n] 2 n
256 n0
(1)
Where “n” indicates the bit location in the respective
PWM register.
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IS31FL3235
For example: D7:D0 = 10110101,
IOUT = IMAX (20+22+24+25+27)/256
The IOUT of each channel is setting by the SL bit of LED
Control Register (2Ah~45h). Please refer to the detail
information in Page 10.
25h PWM Update Register
The data sent to the PWM Registers and the LED
Control Registers will be stored in temporary registers.
A write operation of “0000 0000” value to the Update
Register is required to update the registers (05h~20h,
2Ah~45h).
Table 5 2Ah~45h LED Control Register
(OUT1~OUT28)
Bit
D7:D3
D2:D1
D0
Name
-
SL
OUT
Default
00000
00
0
Table 6 4Ah Global Control Register
Bit
D7:D1
D0
Name
-
G_EN
Default
0000000
0
The Global Control Register set all channels enable.
G_EN
0
1
Global LED Enable
Normal operation
Shutdown all LEDs
4Fh Reset Register
Once user writes “0000 0000” data to the Reset
Register, IS31FL3235 will reset all registers to default
value. On initial power-up, the IS31FL3235 registers
are reset to their default values for a blank display.
The LED Control Registers store the on or off state of
each LED and set the output current.
SL
00
01
10
11
Output Current Setting (IOUT)
IMAX
IMAX/2
IMAX/3
IMAX/4
OUT
0
1
LED State
LED off
LED on
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IS31FL3235
FUNCTIONAL BLOCK DIAGRAM
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IS31FL3235
TYPICAL APPLICATION INFORMATION
PWM CONTROL
Table 7 32 Gamma Steps With 256 PWM Steps
The PWM Registers (05h~2Ah) can modulate LED
brightness of 28 channels with 256 steps. For example,
if the data in PWM Register is “0000 0100”, then the
PWM is the fourth step.
C(0)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
1
2
4
6
10
13
18
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
22
28
33
39
46
53
61
69
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
78
86
96
106
116
126
138
149
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
161
173
186
199
212
226
240
255
REXT
The maximum output current of OUT1~OUT28 can be
adjusted by the external resistor, REXT, as described in
Formula (2).
256
224
192
(2)
PWM Data
I MAX
V
x EXT
REXT
x = 58.5, VOUT = 0.8V, VEXT = 1.3V.
160
128
96
The recommended minimum value of REXT is 2kΩ.
64
CURRENT SETTING
32
The current of each LED can be set independently by
the SL bit of LED Control Register (2Ah~45h). The
maximum global current is set by the external register
REXT.
When channels drive different quantity of LEDs, adjust
maximum output current according to quantity of LEDs
to ensure average current of each LED is the same.
For example, set REXT = 3.3kΩ then IMAX = 23mA. If
OUT1 drives two LEDs and OUT2 drives four LEDs, set
the SL bit of LED Control Register (2Ah) to “01” and SL
bit of LED Control Register (2Bh) to “00”. So the current
of OUT1 is IOUT1 = IMAX/2 = 11.5mA and the current of
OUT2 is IOUT2 = IMAX = 23mA. The average current of
each LED is the same.
GAMMA CORRECTION
In order to perform a better visual LED breathing effect
we recommend using a gamma corrected PWM value
to set the LED intensity. This results in a reduced
number of steps for the LED intensity setting, but
causes the change in intensity to appear more linear to
the human eye.
Gamma correction, also known as gamma
compression or encoding, is used to encode linear
luminance to match the non-linear characteristics of
display. Since the IS31FL3235 can modulate the
brightness of the LEDs with 256 steps, a gamma
correction function can be applied when computing
each subsequent LED intensity setting such that the
changes in brightness matches the human eye's
brightness curve.
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Rev. E, 10/21/2021
0
0
4
8
12
16
20
24
28
32
Intensity Steps
Figure 6
Gamma Correction (32 Steps)
Choosing more gamma steps provides for a more
continuous looking breathing effect. This is useful for
very long breathing cycles. The recommended
configuration is defined by the breath cycle T. When
T=1s, choose 32 gamma steps, when T=2s, choose
64 gamma steps. The user must decide the final
number of gamma steps not only by the LED itself, but
also based on the visual performance of the finished
product.
Table 8 64 Gamma Steps With 256 PWM Steps
C(0)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
1
2
3
4
5
6
7
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
8
10
12
14
16
18
20
22
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
24
26
29
32
35
38
41
44
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
47
50
53
57
61
65
69
73
C(32)
C(33)
C(34)
C(35)
C(36)
C(37)
C(38)
C(39)
77
81
85
89
94
99
104
109
C(40)
C(41)
C(42)
C(43)
C(44)
C(45)
C(46)
C(47)
114
119
124
129
134
140
146
152
C(48)
C(49)
C(50)
C(51)
C(52)
C(53)
C(54)
C(55)
158
164
170
176
182
188
195
202
C(56)
C(57)
C(58)
C(59)
C(60)
C(61)
C(62)
C(63)
209
216
223
230
237
244
251
255
10
IS31FL3235
256
SHUTDOWN MODE
224
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
PWM Data
192
160
Software Shutdown
128
By setting SSD bit of the Shutdown Register (00h) to
“0”, the IS31FL3235 will operate in software shutdown
mode. When the IS31FL3235 is in software shutdown
mode, all current sources are switched off.
96
64
32
0
0
Hardware Shutdown
8
16
24
32
40
48
56
64
Intensity Steps
Figure 7
The chip enters hardware shutdown mode when the
SDB pin is pulled low.
Gamma Correction (64 Steps)
Note, the data of 32 gamma steps is the standard value and the data
of 64 gamma steps is the recommended value.
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IS31FL3235
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 8
Classification profile
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Rev. E, 10/21/2021
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IS31FL3235
PACKAGE INFORMATION
QFN-36
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13
IS31FL3235
RECOMMENDED LAND PATTERN
QFN-36
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use.
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IS31FL3235
REVISION HISTORY
Revision
Detail Information
Date
A
Initial release
2012.10.17
B
1. Absolute Maximum Ratings: voltage at OUTx change from 5V to -0.3V~VCC+0.3V
2. Add ESD value
2014.10.11
C
1. Remove GND thermal current
2. Update POD
3. Add RJA, land pattern and revision history
2016.03.24
D
Update land pattern
2017.06.16
E
Add NRND watermark
2021.10.21
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