NCV8664
Linear Regulator,
Low Dropout, Very Low Iq
The NCV8664 is a precision 3.3 V and 5.0 V fixed output, low
dropout integrated voltage regulator with an output current
capability of 150 mA. Careful management of light load current
consumption, combined with a low leakage process, achieve a
typical quiescent current of 22 A.
NCV8664 is pin and functionally compatible with NCV4264 and
NCV4264−2, and it could replace these parts when very low
quiescent current is required.
The output voltage is accurate within ±2.0%, and maximum
dropout voltage is 600 mV at full rated load current.
It is internally protected against input supply reversal, output
overcurrent faults, and excess die temperature. No external
components are required to enable these features.
www.onsemi.com
MARKING
DIAGRAMS
TAB
1
2
3
1
Features
•
•
•
•
•
•
•
•
•
4
3.3 V, 5.0 V Fixed Output
±2.0% Output Accuracy, Over Full Temperature Range
30 A Maximum Quiescent Current at IOUT = 100 A
600 mV Maximum Dropout Voltage at 150 mA Load Current
Wide Input Voltage Operating Range of 4.5 V to 45 V
Internal Fault Protection
♦ −42 V Reverse Voltage
♦ Short Circuit/Overcurrent
♦ Thermal Overload
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
EMC Compliant
These are Pb−Free Devices
1 2
AYW
V664xG
G
SOT−223
ST SUFFIX
CASE 318E
DPAK
DT SUFFIX
CASE 369C
3
V664xxG
ALYWW
1
8
8
1
SOIC−8 Fused
CASE 751
1
V664x
ALYWX
G
xx
= Voltage Rating DPAK
(50 = 5.0 V Version)
(33 = 3.3 V Version)
x
= Voltage Rating SOT223
(5 = 5.0 V Version)
(3 = 3.3 V Version)
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
(SOT−223/DPAK)
PIN
FUNCTION
1
VIN
2,TAB GND
3
VOUT
(SOIC−8 Fused)
PIN
FUNCTION
1
NC
2,
VIN
3
GND
4.
VOUT
5−8.
NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
November, 2018 − Rev. 19
1
Publication Order Number:
NCV8664/D
NCV8664
IN
OUT
Bias Current
Generators
1.3 V
Reference
+
Error
Amp
-
Thermal
Shutdown
GND
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
DPAK/SOT−223
SOIC−8
Symbol
1
2
VIN
2
3
GND
Ground; substrate.
Function
Unregulated input voltage; 4.5 V to 45 V.
3
4
VOUT
Regulated output voltage; collector of the internal PNP pass transistor.
TAB
−
GND
Ground; substrate and best thermal connection to the die.
−
1, 5−8
NC
No Connection.
OPERATING RANGE
Pin Symbol, Parameter
Symbol
Min
Max
Unit
VIN, DC Input Operating Voltage
VIN
4.5
+45
V
Junction Temperature Operating Range
TJ
−40
+150
°C
Symbol
Min
Max
Unit
VIN
−42
+45
V
VOUT
−0.3
+18
V
MAXIMUM RATINGS
Rating
VIN, DC Voltage
VOUT, DC Voltage
Storage Temperature
Tstg
−55
+150
°C
ESD Capability, Human Body Model (Note 1)
VESDHB
4000
−
V
ESD Capability, Machine Model (Note 1)
VESDMIM
200
−
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C)
THERMAL RESISTANCE
Parameter
Symbol
Condition
Min
Max
Unit
Junction−to−Ambient
DPAK
SOT−223
SOIC−8 Fused
RJA
−
−
−
101 (Note 2)
99 (Note 2)
145
°C/W
Junction−to−Case
DPAK
SOT−223
SOIC−8 Fused
RJC
−
−
−
9.0
17
−
°C/W
2. 1 oz., 100 mm2 copper area.
www.onsemi.com
2
NCV8664
LEAD SOLDERING TEMPERATURE AND MSL
Rating
Symbol
Lead Temperature Soldering
Reflow (SMD Styles Only), Lead Free (Note 3)
Min
Max
−
265 pk
3
2
1
−
−
−
Unit
Tsld
Moisture Sensitivity Level
SOT223
DPAK
SOIC−8 Fused
MSL
°C
−
3. Lead Free, 60 sec – 150 sec above 217°C, 40 sec max at peak.
ELECTRICAL CHARACTERISTICS (VIN = 13.5 V, Tj = −40°C to +150°C, unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
5.0 V Version
VOUT
0.1 mA IOUT 150 mA (Note 4)
6.0 V VIN 28 V
4.900
5.000
5.100
V
Output Voltage
5.0 V Version
VOUT
0 mA IOUT 150 mA
5.5 V VIN 28 V
−40°C TJ 125°C
4.900
5.000
5.100
V
Output Voltage
3.3 V Version
VOUT
0.1 mA IOUT 150 mA (Note 4)
4.5 V VIN 28 V
3.234
3.300
3.366
V
Line Regulation
5.0 V Version
VOUT vs. VIN
IOUT = 5.0 mA
6.0 V VIN 28 V
−25
5.0
+25
mV
Line Regulation
3.3 V Version
VOUT vs. VIN
IOUT = 5.0 mA
4.5 V VIN 28 V
−25
5.0
+25
mV
Load Regulation
VOUT vs. IOUT
1.0 mA IOUT 150 mA
(Note 4)
−35
5.0
+35
mV
Dropout Voltage
5.0 V Version
VIN−VOUT
IQ = 100 mA (Notes 4 & 5)
IQ = 150 mA (Notes 4 & 5)
−
−
265
315
500
600
mV
Dropout Voltage
3.3 V Version
VIN−VOUT
IQ = 100 mA (Notes 4 & 7)
IQ = 150 mA (Notes 4 & 7)
−
−
−
−
1.266
1.266
V
Iq
IOUT = 100 A
TJ = 25°C
TJ = −40°C to +85°C
−
−
21
22
29
30
Active Ground Current
IG(ON)
IOUT = 50 mA (Note 4)
IOUT = 150 mA (Note 4)
−
−
1.3
8.0
3
15
mA
Power Supply Rejection
PSRR
VRIPPLE = 0.5 VP−P, F = 100 Hz
−
67
−
dB
Output Capacitor for Stability
5.0 V Version
COUT
ESR
IOUT = 0.1 mA to 150 mA
(Note 4)
10
−
−
−
−
9.0
F
Output Capacitor for Stability
3.3 V Version
COUT
ESR
IOUT = 0.1 mA to 150 mA
(Note 4)
22
−
−
−
−
18
F
Current Limit
IOUT(LIM)
VOUT = 4.5 V (5.0 V Version) (Note 4)
VOUT = 3.0 V (3.3 V Version) (Note 4)
150
150
−
−
500
500
mA
Short Circuit Current Limit
IOUT(SC)
VOUT = 0 V (Note 4)
100
−
500
mA
TTSD
(Note 6)
150
−
200
°C
Quiescent Current
A
PROTECTION
Thermal Shutdown Threshold
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Use pulse loading to limit power dissipation.
5. Dropout voltage = (VIN – VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with VIN = 13.5 V.
6. Not tested in production. Limits are guaranteed by design.
7. VDO = VIN − VOUT. For output voltage set to < 4.5 V, VDO will be constrained by the minimum input voltage.
www.onsemi.com
3
NCV8664
4.5−45 V
Input
II
CIN
1.0 F
Vin
1
100 nF
8664
3
IQ
Vout
Output
COUT
10 F, 5.0 V Version
22 F, 3.3 V Version
2
GND
Figure 2. Measurement Circuit
4.5−45 V
Input
Vin
CIN
100 nF
1
8664
3
Vout
2
Output
COUT
10 F, 5.0 V Version
22 F, 3.3 V Version
GND
Figure 3. Applications Circuit
www.onsemi.com
4
RL
NCV8664
Typical Curves
1000
5.0
OUTPUT VOLTAGE (V)
100
ESR ()
6.0
Maximum ESR
Cout = 10, 22 F
10
1.0
0.1
0
20
40
Vin = 13.5 V
60
80
100
120
140
0
180
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
INPUT VOLTAGE (V)
Figure 4. ESR Characterization, 5.0 V Version
Figure 5. Output Voltage vs. Input Voltage,
5.0 V Version
8.0
0.40
125°C
Vin = 13.5 V
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
160
25°C
7.0
−40°C
6.0
5.0
4.0
3.0
2.0
1.0
0
50
100
150
0.35
8.0
125°C
Vin = 13.5 V
25°C
0.30
−40°C
0.25
0.20
0.15
0.10
0.05
0
200
0
5.0
10
15
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 6. Current Consumption vs. Output
Load, 5.0 V Version
Figure 7. Current Consumption vs. Output
Load (Low Load), 5.0 V Version
45
20
12
Vin = 13.5 V
Iout = 100 A
40
Vin = 13.5 V
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (A)
2.0
LOAD CURRENT (mA)
9.0
0
3.0
1.0
Stable Region
0.01
4.0
35
30
25
20
15
10
5.0
0
−50
0
50
100
150
10
Iout = 150 mA
8.0
6.0
Iout = 100 mA
4.0
2.0
0
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Quiescent Current vs. Temperature,
5.0 V Version
Figure 9. Quiescent Current vs. Temperature,
5.0 V Version
www.onsemi.com
5
NCV8664
Typical Curves
18
0.45
CURRENT CONSUMPTION (mA)
125°C
0.40
DROPOUT (V)
0.35
0.30
25°C
0.25
−40°C
0.20
0.15
0.10
0.05
0
50
100
150
14
12
10
8.0
6.0
10
20
30
40
Figure 10. Dropout Voltage vs. Output Load,
5.0 V Version
Figure 11. Current Consumption vs. Input
Voltage, 5.0 V Version
140
5.08
OUTPUT VOLTAGE (V)
5.10
120
100
TA = 25°C
80
TA = 125°C
60
40
20
0
0
INPUT VOLTAGE (V)
160
0
RL = 100
2.0
0
200
RL = 50
4.0
OUTPUT LOAD (mA)
10
20
30
40
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
−50
50
0
50
100
TEMPERATURE (°C)
Figure 12. Output Current vs. Input Voltage,
5.0 V Version
Figure 13. Output Voltage vs. Temperature,
5.0 V Version
400
350
300
250
200
150
100
Vin = 13.5 V
50
0
−50
0
50
100
TEMPERATURE (°C)
Figure 14. Current Limit vs. Temperature,
5.0 V Version
www.onsemi.com
6
50
Vin = 13.5 V
Load = 10 mA
5.06
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
0
16
150
150
NCV8664
Typical Curves
100
3.5
90
3.0
OUTPUT VOLTAGE (V)
80
ESR ()
70
60
50
40
30
20
Vin = 13.5 V
Cout > 22 F
0
25
50
75
100
0
10
20
30
40
Figure 16. Output Voltage vs. Input Voltage,
3.3 V Version
7.0
0.50
6.0
5.0
4.0
3.0
2.0
1.0
Vin = 13.5 V
50
100
150
200
0.45
125°C
0.40
25°C
−40°C
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
Vin = 13.5 V
5
0
10
15
20
OUTPUT LOAD (mA)
OUTPUT LOAD (mA)
Figure 17. Current Consumption vs. Output
Load, 3.3 V Version
Figure 18. Current Consumption vs. Output
Load (Low Load), 3.3 V Version
45
10
40
9
35
30
25
20
15
10
Vin = 13.5 V
Iout = 100 A
5
0
−40
Iout = 5 mA
Figure 15. ESR Stability, 3.3 V Version
QUIESCENT CURRENT (A)
QUIESCENT CURRENT (mA)
0
150
125°C
25°C
−40°C
0
1.0
INPUT VOLTAGE (V)
8.0
0
1.5
OUTPUT LOAD (mA)
9.0
QUIESCENT CURRENT (A)
125
2.0
0.5
QUIESCENT CURRENT (mA)
10
0
2.5
10
60
110
Iout = 150 mA
8
7
6
5
Iout = 100 mA
4
3
2
1
0
−40
150
25
Vin = 13.5 V
10
60
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Quiescent Current vs. Temperature,
3.3 V Version
Figure 20. Quiescent Current vs. Temperature,
3.3 V Version
www.onsemi.com
7
NCV8664
Typical Curves
7
DROPOUT VOLTAGE (V)
0.40
CURRENT CONSUMPTION (mA)
0.45
125°C
0.35
0.30
25°C
−40°C
0.25
0.20
0.15
0.10
0.05
0
0
50
100
150
6
5
4
3
2
RL = 50
1
RL = 100
0
200
0
10
20
30
40
OUTPUT LOAD (mA)
INPUT VOLTAGE (V)
Figure 21. Dropout Voltage, 3.3 V Version
Figure 22. Current Consumption vs. Input
Voltage, 3.3 V Version
3.50
50
250
3.40
CURRENT LIMIT (mA)
OUTPUT VOLTAGE (V)
3.45
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
−40 −20
Vin = 14 V
Iout = 5 mA
0
20
40
60
80
200
150
100
50
Vin = 13.5 V
0
−40
100 120 125
10
60
110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Output Voltage vs. Temperature,
3.3 V Version
Figure 24. Short Circuit Current Limit vs.
Temperature, 3.3 V Version
www.onsemi.com
8
150
NCV8664
Circuit Description
Calculating Power Dissipation in a Single Output
Linear Regulator
The NCV8664 is a precision trimmed 3.3 V and 5.0 V
fixed output regulator. Careful management of light load
consumption combined with a low leakage process results
in a typical quiescent current of 22 A. The device has
current capability of 150 mA, with 600 mV of dropout
voltage at full rated load current. The regulation is provided
by a PNP pass transistor controlled by an error amplifier
with a bandgap reference. The regulator is protected by
both current limit and short circuit protection. Thermal
shutdown occurs above 150°C to protect the IC during
overloads and extreme ambient temperatures.
The maximum power dissipation for a single output
regulator (Figure 3) is:
PD(max) [VIN(max) VOUT(min)]
IQ(max) VI(max) Iq
(eq. 1)
Where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IQ(max) is the maximum output current for the
application, and Iq is the quiescent current the regulator
consumes at IQ(max).
Once the value of PD(Max) is known, the maximum
permissible value of RJA can be calculated:
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout) and drives the base of
a PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Over saturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. The NCV8664 is equipped with
foldback current protection. This protection is designed to
reduce the current limit during an overcurrent situation.
PJA
150 oC TA
PD
(eq. 2)
The value of RJA can then be compared with those in the
package section of the data sheet. Those packages with
RJA’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C. In some cases, none of
the packages will be sufficient to dissipate the heat
generated by the IC, and an external heat sink will be
required. The current flow and voltages are shown in the
Measurement Circuit Diagram.
Regulator Stability Considerations
The input capacitor CIN in Figure 2 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1 in series
with CIN. The output or compensation capacitor, COUT
helps determine three main characteristics of a linear
regulator: startup delay, load transient response and loop
stability. The capacitor value and type should be based on
cost, availability, size and temperature constraints.
Tantalum, aluminum electrolytic, film, or ceramic
capacitors are all acceptable solutions, however, attention
must be paid to ESR constraints. The aluminum
electrolytic capacitor is the least expensive solution, but, if
the circuit operates at low temperatures (−25°C to −40°C),
both the value and ESR of the capacitor will vary
considerably. The capacitor manufacturer’s data sheet
usually provides this information. The value for the output
capacitor COUT shown in Figure 2 should work for most
applications; however, it is not necessarily the optimized
solution. Stability is guaranteed at values COUT ≥ 10 F and
ESR ≤ 9 for 5.0 V version, and COUT ≥ 22 F and ESR
≤ 18 for 3.3 V version, within the operating temperature
range. Actual limits are shown in a graph in the Typical
Performance Characteristics section.
Heat Sinks
For proper heat sinking of the SOIC−8 Lead device,
connect pins 5 − 8 to the heat sink.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air. Each material in the heat flow path
between the IC and the outside environment will have a
thermal resistance. Like series electrical resistances, these
resistances are summed to determine the value of RJA:
RJA RJC RCS RSA
(eq. 3)
Where:
RJC = the junction−to−case thermal resistance,
RCS = the case−to−heat sink thermal resistance, and
RSA = the heat sink−to−ambient thermal resistance.
RJA appears in the package section of the data sheet.
Like RJA, it too is a function of package type. RCS and
RSA are functions of the package type, heat sink and the
interface between them. These values appear in data sheets
of heat sink manufacturers. Thermal, mounting, and heat
sinking are discussed in the ON Semiconductor application
note AN1040/D, available on the ON Semiconductor
Website.
www.onsemi.com
9
NCV8664
EMC−Characteristics: Conducted Susceptibility
Direct Power Injection: 33 dBm forward power CW
Acceptance Criteria: Amplitude Dev. max 2% of Output
Voltage
All EMC−Characteristics are based on limited samples
and not part of production testing, according to
47A/658/CD IEC62132−4 (Direct Power Injection)
Test Conditions
Supply Voltage
Temperature
Load
VIN = 12 V
TA = 23°C ±5°C
RL = 35
U1
X1
VIN_HF
1
F3
FERRITE
VIN
VOUT
GND
C1
C2 +
10 F
X2
VIN_MON
NCV8664
2
47 nF
X3
VOUT_HF
3
C3
10 nF
C4
10 F
+
F1
FERRITE
X4
VOUT_MON
F2
FERRITE
X5
GND_HF
X6
GND_MON
Figure 25. Test Circuit
40
40
VIN−pin pass 33 dBm
VOUT−pin pass 33 dBm
30
VOUT (dBm)
VIN (dBm)
30
20
10
0
20
10
1
10
100
1000
0
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. Typical VIN−pin Susceptibility
Figure 27. Typical VOUT−pin Susceptibility
www.onsemi.com
10
NCV8664
160
140
JA (°C/W)
120
SOIC−8 Fused
100
SOT223
80
60
DPAK
40
20
0
0
100
200
300
400
COPPER AREA
500
600
700
(mm2)
Figure 28. qJA vs. Copper Spreader Area
1000
SOT223
100
SOIC−8 Fused
R(t) (°C/W)
10
DPAK
1
0.1
0.01
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 29. Single−Pulse Heating Curves
ORDERING INFORMATION
Marking
Package
Shipping†
NCV8664D50R2G
V6645
SOIC−8 Fused
(Pb−Free)
2500 / Tape & Reel
NCV8664D50G
V6645
SOIC−8 Fused
(Pb−Free)
98 Units / Rail
NCV8664DT50RKG
V66450G
DPAK
(Pb−Free)
2500 / Tape & Reel
NCV8664DT33RKG
V66433G
DPAK
(Pb−Free)
2500 / Tape & Reel
NCV8664ST50T3G
V6645
SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV8664ST33T3G
V6643
SOT−223
(Pb−Free)
4000 / Tape & Reel
Device*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
C
A
b3
B
c2
4
L3
Z
D
1
2
H
DETAIL A
3
L4
NOTE 7
c
SIDE VIEW
b2
e
b
0.005 (0.13)
TOP VIEW
BOTTOM VIEW
C
M
Z
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
BOTTOM VIEW
A1
L1
DETAIL A
Z
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
2.58
0.102
1.60
0.063
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
6.17
0.243
SCALE 3:1
AYWW
XXX
XXXXXG
XXXXXX
A
L
Y
WW
G
3.00
0.118
5.80
0.228
XXXXXXG
ALYWW
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
http://onsemi.com
DPAK SINGLE GAUGE SURFACE
1 MOUNT
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION. REQ. BY L. GAN
24 SEP 2001
A
ADDED STYLE 8. REQ. BY S. ALLEN.
06 AUG 2008
B
ADDED STYLE 9. REQ. BY D. WARNER.
16 JAN 2009
C
ADDED STYLE 10. REQ. BY S. ALLEN.
09 JUN 2009
D
RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE.
29 JUN 2010
E
ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAMBALIZA.
06 FEB 2014
F
ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA.
21 JUL 2015
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. F
Case Outline Number:
369C
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
STATUS:
98ASB42564B
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
SOIC−8, NB
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
3
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
STATUS:
98ASB42564B
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
SOIC−8, NB
http://onsemi.com
2
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 2 OFXXX
3
DOCUMENT NUMBER:
98ASB42564B
PAGE 3 OF 3
ISSUE
REVISION
DATE
AB
ADDED STYLE 25. REQ. BY S. CHANG.
15 MAR 2004
AC
ADDED CORRECTED MARKING DIAGRAMS. REQ. BY S. FARRETTA.
13 AUG 2004
AD
CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY S. FARRETTA.
18 NOV 2004
AE
UPDATED SCALE ON FOOTPRINT. REQ. BY S. WEST.
31 JAN 2005
AF
UPDATED MARKING DIAGRAMS. REQ. BY S. WEST. ADDED STYLE 26. REQ. BY
S. CHANG.
14 APR 2005
AG
ADDED STYLE 27. REQ. BY S. CHANG.
30 JUN 2005
AH
ADDED STYLE 28. REQ. BY S. CHANG.
09 MAR 2006
AJ
ADDED STYLE 29. REQ. BY D. HELZER.
19 SEP 2007
AK
ADDED STYLE 30. REQ. BY I. CAMBALIZA.
16 FEB 2011
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2011
February, 2011 − Rev. 07AK
Case Outline Number:
751
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
◊
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
工商网监
湘ICP备2023018690号
