MPC9446FA

Freescale Semiconductor Technical Data 2.5 V and 3.3 V LVCMOS Clock Fanout Buffer The MPC9446 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9446 is specified for the extended temperature range of –40°C to 85°C. MPC9446 Rev. 3, 08/2005 MPC9446 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5 V AND 3.3 V LVCMOS CLOCK DISTRIBUTION BUFFER Features • • • • • • • • • • • Configurable 10 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply Wide range output clock frequency up to 250 MHz Designed for mid-range to high-performance telecom, networking and computer applications Supports applications requiring clock redundancy Maximum output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank Tristable outputs 32-lead LQFP package 32-lead Pb-free package available Ambient operating temperature range of –40 to 85°C FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. VCC 25k CCLK0 Bank A VCC 25k CCLK1 CCLK_SEL 0 CLK 0 1 CLK ÷ 2 1 QA0 QA1 25k 0 QA2 Bank B QB0 QB1 1 QB2 QC0 Bank C FSELA 25k FSELB 25k FSELC 0 QC1 1 QC2 QC3 25k MR/OE 25k VCCC VCCB QB2 GND QB1 VCCB QB0 GND Figure 1. MPC9446 Logic Diagram VCCB is internally connected to VCC 24 23 22 21 20 19 18 17 VCCA 25 16 QC3 QA2 26 15 GND GND 27 14 QC2 QA1 28 13 VCCC VCCA 29 12 QC1 QA0 30 11 GND GND 31 10 QC0 MR/OE 32 9 VCCC 1 2 3 4 5 6 7 8 CCLK_SEL VCC CCLK0 CCLK1 FSELA FSELB FSELC GND MPC9446 Figure 2. Pinout: 32-Lead Package Pinout (Top View) MPC9446 2 Advanced Clock Drivers Devices Freescale Semiconductor Table 1. Pin Configuration Pin I/O Type Function CCLK0,1 Input LVCMOS LVCMOS clock inputs FSELA, FSELB, FSELC Input LVCMOS Output bank divide select input MR/OE Input LVCMOS Internal reset and output (high impedance) control Supply Negative voltage supply (GND) Supply Positive voltage supply for output banks Supply Positive voltage supply for core (VCC) GND VCCA, VCCB (1), VCCC VCC QA0 – QA2 Output LVCMOS Bank A outputs QB0 – QB2 Output LVCMOS Bank B outputs QC0 – QC3 Output LVCMOS Bank C outputs 1. VCCB is internally connected to VCC. Table 2. Supported Single and Dual Supply Configurations VCC(1) VCCA(2) VCCB(3) VCCC(4) GND 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0V Mixed Voltage Supply 3.3 V 3.3 V or 2.5 V 3.3 V 3.3 V or 2.5 V 0V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 0V Supply Voltage Configuration 1. 2. 3. 4. VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels. Table 3. Function Table (Controls) Control Default 0 1 CCLK_SEL 0 CCLK0 CCLK1 FSELA 0 fQA0:2 = fREF fQA0:2 = fREF ÷ 2 FSELB 0 fQB0:2 = fREF fQB0:2 = fREF ÷ 2 FSELC 0 fQC0:3 = fREF fQC0:3 = fREF ÷ 2 MR/OE 0 Outputs enabled Internal reset outputs disabled (tristate) Table 4. Absolute Maximum Ratings(1) Symbol Min Max Unit VCC Supply Voltage –0.3 3.6 V VIN DC Input Voltage –0.3 VCC+0.3 V DC Output Voltage –0.3 VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C VOUT IIN IOUT TS Characteristics Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. MPC9446 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 5. General Specifications Symbol Characteristics Min Typ Max Unit VCC ÷ 2 VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF CIN Input Capacitance 4.0 pF Condition V Per output Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40°C to +85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage –0.3 0.8 V LVCMOS 200 µA VIN = GND or VIN = VCC V IOH = –24 mA(2) V V IOL = 24 mA(2) IOL = 12 mA IIN Input Current (1) VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance ICCQ (3) 2.4 0.55 0.30 Ω 14 – 17 Maximum Quiescent Supply Current 2.0 mA All VCC Pins 1. Input pull-up / pull-down resistors influence input current. 2. The MPC9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40°C to +85°C)(1) Symbol fref Characteristics Min Input Frequency fMAX Maximum Output Frequency tP, REF Reference Input Pulse Width tr, tf CCLK Input Rise/Fall Time tPLH tPHL Propagation Delay ÷1 output ÷2 output Max Unit 0 Typ 250(2) MHz 0 0 250(2) 125 MHz MHz 1.4 CCLK0,1 to any Q CCLK0,1 to any Q 2.2 2.2 Condition FSELx = 0 FSELx = 1 ns 2.8 2.8 1.0(3) ns 4.45 4.2 ns ns 0.8 to 2.0 V tPLZ, HZ Output Disable Time 10 ns tPZL, LZ Output Enable Time 10 ns tsk(O) Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider 150 200 350 ps ps ps tsk(PP) Device-to-Device Skew 2.25 ns 200 ps 53 55 % % DCREF = 50% DCREF = 25%–75% 1.0 ns 0.55 to 2.4 V Skew(4) tSK(P) Output Pulse DCQ Output Duty Cycle tr, tf Output Rise/Fall Time ÷1 output ÷2 output 47 45 0.1 50 50 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%. MPC9446 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input High Voltage 1.7 VCC + 0.3 V LVCMOS VIL Input Low Voltage –0.3 0.7 V LVCMOS VOH Output High Voltage 1.8 V IOH = –15 mA(1) VOL Output Low Voltage 0.6 V IOL = 15 mA ±200 µA VIN = GND or VIN = VCC 2.0 mA All VCC Pins ZOUT ICCQ Output Impedance 17 – 20 Input Current(2) IIN (3) (2) Ω Maximum Quiescent Supply Current 1. The MPC9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per output. 2. Input pull-up / pull-down resistors influence input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1) Symbol fref Characteristics Min Input Frequency fMAX Maximum Output Frequency tP, REF Reference Input Pulse Width tr, tf CCLK Input Rise/Fall Time tPLH tPHL Propagation Delay ÷1 output ÷2 output Max Unit 0 Typ 250(2) MHz 0 0 250(2) 125 MHz MHz 1.4 CCLK0,1 to any Q CCLK0,1 to any Q ns 5.6 5.5 ns ns 2.6 2.6 Output Disable Time 10 ns tPZL, LZ Output Enable Time 10 ns tsk(O) Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider 150 200 350 ps ps ps tsk(PP) Device-to-Device Skew 3.0 ns 200 ps Skew(4) Output Pulse DCQ Output Duty Cycle tr, tf Output Rise/Fall Time ÷1 or ÷2 output 45 FSELx = 0 FSELx = 1 ns 1.0(3) tPLZ, HZ tSK(P) Condition 50 0.1 0.7 to 1.7 V 55 % DCREF = 50% 1.0 ns 0.6 to 1.8 V 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%. Table 10. AC Characteristics (VCC = 3.3 V + 5%, VCCA, VCCB, VCCC = 2.5 V + 5% or 3.3 V + 5%, TA = –40°C to +85°C)(1) (2) Symbol Characteristics tsk(O) Output-to-Output Skew Within one bank Any output bank, same output divider Any output, Any output divider tsk(PP) Device-to-Device Skew tPLH,HL Propagation Delay tSK(P) Output Pulse Skew(3) DCQ Output Duty Cycle Min CCLK0,1 to any Q ÷1 or ÷2 output Typ Max Unit 150 250 350 ps ps ps 2.5 ns 250 ps 55 % Condition See 3.3 V Table 45 50 DCREF = 50% 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank. 3. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency dependent: DCQ = (0.5 ± tSK(P) • fOUT). MPC9446 Advanced Clock Drivers Devices Freescale Semiconductor 5 APPLICATIONS INFORMATION 14Ω VS (Z0 ÷ (RS + R0 + Z0)) 50 Ω || 50 Ω 36 Ω || 36 Ω 14 Ω 3.0 (25 ÷ (18 + 14 + 25) 1.31 V At the load end, the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 MPC9446 Output Buffer IN VL = Z0 = RS = R0 = VL = = Voltage (V) Driving Transmission Lines The MPC9446 clock driver was designed to drive highspeed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to VCC÷2. This technique draws a fairly high level of DC current, and thus, only a single terminated line can be driven by each output of the MPC9446 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9446 clock driver is effectively doubled due to its capability to drive multiple lines. 0 RS = 36Ω ZO = 50Ω OutA 2 4 6 8 Time (ns) 10 12 14 Figure 4. Single versus Dual Waveforms MPC9446 Output Buffer RS = 36Ω ZO = 50Ω RS = 36Ω ZO = 50Ω OutB0 14Ω IN OutB1 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9446 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9446. The output waveform in Figure 4 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 5 should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC9446 Output Buffer RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω 25 Ω = 25 Ω Figure 5. Optimized Dual Line Termination MPC9446 6 Advanced Clock Drivers Devices Freescale Semiconductor MPC9446 DUT Pulse Generator Z = 50Ω ZO = 50 Ω ZO = 50Ω RT = 50Ω RT = 50Ω VTT VTT Figure 6. CCLK0, 1 MPC9446 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V tF VCC = 3.3V VCC = 2.5V 2.4 1.8V 0.55 0.6V VCC VCC÷2 CCLK GND VCC VCC÷2 Qx tR GND t(LH) Figure 7. Output Transition Time Test Reference VCC VCC÷2 t(HL) Figure 8. Propagation Delay (tPD) Test Reference VCC CCLK VCC÷2 GND VCC VCC÷2 GND VCC VCC÷2 QX GND tSK(LH) tSK(HL) GND t(LH) The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device. Figure 9. Output-to-Output Skew tSK(LH, HL) t(HL) tSK(P) = | tPLH – tPHL | Figure 10. Output Pulse Skew (tSK(P)) Test Reference VCC VCC÷2 GND tP TN T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 11. Output Duty Cycle (DC) TN+1 TJIT(CC) = |TN-TN+1| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. Figure 12. Cycle-to-Cycle Jitter MPC9446 Advanced Clock Drivers Devices Freescale Semiconductor 7 PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC9446 8 Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC9446 Advanced Clock Drivers Devices Freescale Semiconductor 9 PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC9446 10 Advanced Clock Drivers Devices Freescale Semiconductor NOTES MPC9446 Advanced Clock Drivers Devices Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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