FDMC8360LET40

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMC8360LET40 N-Channel Shielded Gate Power Trench® MOSFET 40 V, 141 A, 2.1 mΩ Features General Description „ Shielded Gate MOSFET Technology This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that incorporates shielded gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. „ Max rDS(on) = 2.1 mΩ at VGS = 10 V, ID = 27 A „ Max rDS(on) = 3.1 mΩ at VGS = 4.5 V, ID = 22 A „ High Performance Technology for Extremely Low rDS(on) „ Termination is Lead-free „ 100% UIL Tested Application „ RoHS Compliant „ DC-DC Conversion Pin 1 Pin 1 S D Top D D Power33 S S S D S D S D G D G D Bottom MOSFET Maximum Ratings TA = 25 °C unless otherwise noted. Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous -Continuous TJ, TSTG ±20 V 141 TC = 100 °C (Note 5) 100 TA = 25 °C (Note 1a) 27 -Pulsed PD Units V (Note 5) Single Pulse Avalanche Energy EAS Ratings 40 Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C (Note 4) 658 (Note 3) 253 75 (Note 1a) Operating and Storage Junction Temperature Range 2.8 -55 to +175 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient (Note 1) 2.0 (Note 1a) 53 °C/W Package Marking and Ordering Information Device Marking FDMC8360LET Device FDMC8360LET40 ©2015 Fairchild Semiconductor Corporation FDMC8360LET40 Rev.1.0 Package Power33 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET September 2015 Symbol Parameter Test Conditions Min. Typ. Max. Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3.0 V 40 V 20 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 27 A 1.4 2.1 rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 22 A 2.1 3.1 VGS = 10 V, ID = 27 A, TJ = 150 °C 2.3 3.5 VDD = 5 V, ID = 27 A 138 VDS = 20 V, VGS = 0 V, f = 1 MHz 3785 5300 pF 1220 1710 pF gFS Forward Transconductance 1.0 1.7 -6 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance 0.1 57 80 pF 0.8 1.6 Ω 14 26 ns Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 20 V, ID = 27 A, VGS = 10 V, RGEN = 6 Ω 8 16 ns 35 57 ns 7 14 ns Total Gate Charge VGS = 0 V to 10 V 57 80 nC Qg(TOT) Total Gate Charge 38 Gate to Source Charge VGS = 0 V to 4.5 V VDD = 20 V, ID = 27 A 27 Qgs 9.9 nC Qgd Gate to Drain “Miller” Charge 8.1 nC nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 27 A (Note 2) 0.8 1.3 VGS = 0 V, IS = 1.9 A (Note 2) 0.7 1.2 V 47 76 ns 30 48 nC IF = 27 A, di/dt = 100 A/μs V Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b) 125°C/W when mounted on a minimum pad a) 53°C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 253 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 13 A, VDD = 40 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 42 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2015 Fairchild Semiconductor Corporation FDMC8360LET40 Rev.1.0 2 www.fairchildsemi.com FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted. 10 VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 300 VGS = 4 V 225 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 4.5 V 150 VGS = 3.5 V 75 VGS = 3 V 0 0 1 2 8 VGS = 3.5 V 6 VGS = 4 V 4 2 VGS = 4.5 V 0 3 0 60 VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 20 10 TJ = 25 oC 5 TJ = 150 oC 4 6 8 10 Figure 4. On-Resistance vs. Gate to Source Voltage IS, REVERSE DRAIN CURRENT (A) 240 ID, DRAIN CURRENT (A) ID = 27 A 15 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VDS = 5 V 180 oC 120 TJ = 25 oC 60 TJ = -55 oC 0 4 300 100 VGS = 0 V 10 TJ = 175 oC 1 TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.001 0.0 5 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs. Source Current ©2015 Fairchild Semiconductor Corporation FDMC8360LET40 Rev.1.0 300 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 2 300 3 240 0 Figure 3. Normalized On Resistance vs. Junction Temperature 2 180 Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 1.9 ID = 27 A 1.8 VGS = 10 V 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -75 -50 -25 0 25 50 75 100 125 150 175 TJ, JUNCTION TEMPERATURE (oC) 1 VGS = 10 V 120 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics TJ = 175 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 3 1.2 www.fairchildsemi.com FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted. 10000 Ciss ID = 27 A 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 20 V 6 VDD = 25 V 4 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 12 24 36 48 10 0.1 60 Figure 7. Gate Charge Characteristics 40 150 ID, DRAIN CURRENT (A) TJ = 25 oC TJ = 125 oC 10 TJ = 150 oC 120 VGS = 10 V 90 60 VGS = 6 V 30 o RθJC = 2.0 C/W 1 0.001 0.01 0.1 1 10 100 0 25 500 50 75 175 P(PK), PEAK TRANSIENT POWER (W) 100000 10 us 100 THIS AREA IS LIMITED BY rDS(on) 1 ms 10 ms RθJC = 2.0 oC/W 100 ms/DC CURVE BENT TO MEASURED DATA 1 10 100 200 TC = 25 oC 1000 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2015 Fairchild Semiconductor Corporation FDMC8360LET40 Rev.1.0 SINGLE PULSE RθJC = 2.0 oC/W 10000 100 us SINGLE PULSE TJ = MAX RATED TC = 25 oC 0.1 0.1 150 Figure 10. Maximum Continuous Drain Current vs. Case Temperature 1000 1 125 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 10 100 o tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) 10 Figure 8. Capacitance vs. Drain to Source Voltage 100 IAS, AVALANCHE CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: ZθJC(t) = r(t) x RθJC RθJC = 2.0 oC/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve ©2015 Fairchild Semiconductor Corporation FDMC8360LET40 Rev.1.0 5 www.fairchildsemi.com FDMC8360LET40 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted. 3.40 3.20 PKG CL 8 2.37 MIN A (0.45) 8 B 5 PKG CL 3.40 3.20 PKG CL SYM CL 5 2.15 MIN (0.40) (0.65) 0.70 MIN PIN 1 INDICATOR 1 4 1 4 0.65 1.95 SEE DETAIL A 0.42 MIN (8X) LAND PATTERN RECOMMENDATION 1.95 0.10 C A B 0.37 (8X) 0.27 0.65 1 4 0.50 0.30 PKG CL 2.05 1.85 5 8 (0.34) (0.52 TYP) (0.33) TYP (2.27) 0.10 C 0.80 0.70 0.08 C 0.25 0.15 0.05 0.00 C SEATING PLANE SCALE: 2X NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. BA, DATED OCTOBER 2002. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN08HREV1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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