NB6L14MMNR2G

NB6L14M 2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer Multi-Level Inputs with Internal Termination http://onsemi.com Description MARKING DIAGRAM* The NB6L14M is a 3.0 GHz differential 1:4 CML clock or data fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB6L14M to accept various logic standards, such as LVPECL, CML, or LVDS logic levels. The 16 mA differential CML outputs provide matching internal 50 W terminations and produce 400 mV output swings when externally terminated with a 50 W resistor to VCC. The VREFAC reference output can be used to rebias capacitor-coupled differential or single-ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB6L14M is a member of the ECLinPS MAX™ family of high performance clock and data products. 16 1 QFN-16 MN SUFFIX CASE 485G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) Features *For additional marking information, refer to Application Note AND8002/D. •Input Clock Frequency > 3.0 GHz •Input Data Rate > 2.5 Gb/s •< 20 ps Within Device Output Skew •350 ps Typical Propagation Delay •90 ps Typical Rise and Fall Times •Differential CML Outputs, 340 mV Amplitude, Typical •CML Mode Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V •Internal Input and Output Termination Resistors, 50 W •VREFAC Reference Output Voltage •-40°C to +85°C Ambient Operating Temperature •Available in 3 mm x 3 mm 16 Pin QFN •These are Pb-Free Devices NB6L 14M ALYWG G Q0 Q0 Q1 Q1 IN VT IN Q2 D EN Q Q2 Q3 VREFAC Q3 Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2008 April, 2008 - Rev. 3 1 Publication Order Number: NB6L14M/D NB6L14M Q0 Q0 Q0 16 15 VCC GND 14 /Q0 Exposed Pad (EP) 13 Q1 Q1 1 12 IN Q1 2 11 VT Q2 3 10 VREFAC Q2 4 9 5 6 7 8 Q3 Q3 VCC EN /Q1 IN VT 50 W IN 50 W Q2 /Q2 IN D EN Q CLK VREFAC Q3 /Q3 Figure 2. QFN-16 Pinout (Top View) Figure 3. Logic Diagram Table 1. EN TRUTH TABLE IN IN EN Q0:Q3 Q0:Q3 0 1 x 1 0 x 1 1 0 0 1 0+ 1 0 1+ + = On next negative transition of the input signal (IN). x = Don't care. Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 CML Output Non-inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 2 Q1 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC . 3 Q2 CML Output Non-inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 4 Q2 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 5 Q3 CML Output Non-inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 6 Q3 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 7 VCC - 8 EN LVTTL/LVCMOS 9 IN LVPECL, CML, LVDS 10 VREFAC Positive Supply Voltage Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal pullup resistor and defaults HIGH when left open. Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT. Output Voltage Reference for capacitor-coupled inputs, only. Internal 100 W center-tapped Termination Pin for IN and IN. 11 VT 12 IN LVPECL, CML, LVDS 13 GND - Negative Supply Voltage 14 VCC - Positive Supply Voltage 15 Q0 CML Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 16 Q0 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. - EP - Non-inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT. The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self-oscillation. http://onsemi.com 2 NB6L14M Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Mode Moisture Sensitivity (Note 2) Flammability Rating > 2 kV > 200 V QFN-16 Level 1 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in Transistor Count 167 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VIo Positive Input/Output GND = 0 V IIN Input Current Condition 2 -0.5 V  VIo  VCC + 0.5 V Rating Unit 4.0 V 4.5 V 50 mA 2.0 mA -40 to +85 °C Source or Sink Current (IN/IN) IVREFAC Sink/Source Current TA Operating Temperature Range Tstg Storage Temperature Range -65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) (Note 3) 0 lfpm 500 lfpm QFN-16 QFN-16 42 35 °C/W °C/W qJC Thermal Resistance (Junction-to-Case) 2S2P (Note 3) QFN-16 4 °C/W Tsol Wave Solder 265 °C Pb-Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L14M Table 5. DC CHARACTERISTICS, Multi-Level Inputs, CML Outputs VCC = 2.375 V to 3.63 V, GND = 0 V, TA = -40°C to +85°C Symbol ICC Characteristic Min Typ Max Unit 80 100 130 mA VCC - 40 3260 2460 VCC - 10 3290 2490 VCC 3300 2500 mV VCC = 3.3 V VCC = 2.5 V VCC - 500 2800 2000 VCC - 400 2900 2100 VCC - 300 3000 2200 mV VCC = 3.3 V VCC = 2.5 V Power Supply Current (Inputs and Outputs Open) CML OUTPUT (Notes 4 and 5) VOH VOL Output HIGH Voltage Output LOW Voltage DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (See Figures 5 and 6) Vth Input Threshold Reference Voltage Range (Note 6) 1100 VCC - 100 mV VIH Single-Ended Input High Voltage Vth + 100 VCC mV VIL Single-Ended Input LOW Voltage GND Vth - 100 mV VISE Single-Ended Input Voltage Amplitude (VIH - VIL) 200 VCC - GND mV VCC - 1325 mV VREFAC VREFAC Output Reference Voltage (VCC  2.5 V) VCC - 1525 VCC - 1425 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 7 and 8) (Note 7) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage GND VIHD - 100 mV VID Differential Input Voltage (IN-IN) (VIHD-VILD) 100 VCC - GND mV VCMR Input Common Mode Range (Differential Configuration) (Note 8) 950 VCC – 50 mV IIH Input HIGH Current IN/IN (VT Open) -150 +150 mA IIL Input LOW Current IN/IN (VT Open) -150 +150 mA LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS VIH Input HIGH Voltage 2.0 VCC V VIL Input LOW Voltage GND 0.8 V IIH Input HIGH Current, VCC = VIN = 3.63 V -150 +150 mA IIL Input LOW Current, VCC = 3.63 V, VIN = 0 V -150 +150 mA TERMINATION RESISTORS RTIN Internal Input Termination Resistor (IN to VT) 40 50 60 W RDIFF_IN Differential Input Resistance (IN to IN) 80 100 120 W RTOUT Internal Output Termination Resistor 40 50 60 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. CML outputs loaded with 50 W to VCC for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single-ended mode. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 8. VCMR minimum varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L14M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = -40°C to +85°C (Note 9) Symbol VOUTPP Characteristic Min Typ 180 100 340 250 Max Output Voltage Amplitude (@ VINPPmin) (Note 10) fin ≤ 2.5 GHz 2.5 GHz ≤ fin ≤ 3.0 GHz mV fDATA Maximum Operating Data Rate tPD Propagation Delay tS Set-Up Time (Note 11) EN to IN, IN 300 tH Hold Time (Note 11) EN to IN, IN 300 tSKEW Within-Device Skew (Note 12) Device-to-Device Skew (Note 13) tDC Output Clock Duty Cycle (Referenced Duty Cycle = 50%) tJITTER RMS Random Jitter (Note 14) Peak-to-Peak Data Dependent Jitter (Note 15) VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) tr,tf Output Rise/Fall Times (20%-80%) 2.5 IN to Q Unit 230 350 Gb/s 480 ps ps ps 5.0 20 80 ps 50 60 % fIN ≤ 3.0 GHz 0.2 0.5 fDATA≤ 3.0 Gb/s 20 fin ≤ 3.0 GHz 40 ps 100 90 VCC - GND mV 150 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (minimum) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20%-80%). 10. Input and output voltage swing is a single-ended measurement operating in differential mode. 11. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold times do not apply. 12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions. 13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 23-1 and K28.5 at 2.5 Gb/s. http://onsemi.com 5 NB6L14M INn VTn INn 50 W 50 W Figure 4. Input Structure VCC Vthmax IN VIH VIHmax VILmax Vth VIH Vth VIL Vth VIL IN VIHmin Vthmin Vth VILmin GND Figure 6. Vth Diagram Figure 5. Differential Input Driven Single-Ended VCC VIH(MAX) VIL IN VIH VID = VIHD - VILD VCMR VIL IN VIH Figure 7. Differential Inputs Driven Differentially VIL(MIN) GND Figure 8. VCMR Diagram IN VINPP = VIH(IN) - VIL(IN) IN Q VOUTPP = VOH(Q) - VOL(Q) Q tPD tPD Figure 9. AC Reference Measurement http://onsemi.com 6 NB6L14M VCC VCC VCC NB6L14M ZO = 50 W CML Driver VCC ZO = 50 W IN 50 W VT = VCC - 2 V ZO = 50 W LVDS Driver 50 W NB6L14M IN 50 W VT = Open ZO = 50 W IN 50 W IN GND GND GND GND Figure 10. CML Interface Figure 11. LVDS Interface VCC VCC NB6L14M ZO = 50 W CML Driver IN 50 W VT = VCC ZO = 50 W 50 W IN GND GND Figure 12. Standard 50 W Load CML Interface VCC VCC ZO = 50 W Differential Driver VCC VCC NB6L14M ZO = 50 W IN 50 W VT = VREF_AC* ZO = 50 W Single-Ended Driver 50 W IN GND NB6L14M IN 50 W VT = VREF_AC* 50 W IN GND GND Figure 13. Capacitor-Coupled Differential Interface (VT Connected to VREFAC) GND Figure 14. Capacitor-Coupled Single-Ended Interface (VT Connected to VREFAC) *VREFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com 7 (Open) VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NB6L14M 800 700 600 500 400 300 200 100 0 0 1 2 3 3.5 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 15. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) EN VCC/2 VCC/2 tS tH /IN IN VINPP tpd /Q VOUTPP Q Figure 16. EN Timing Diagram VCC 50 W 50 W Q Q 16 mA GND Figure 17. CML Output Structure http://onsemi.com 8 NB6L14M VCC 50 W Z = 50 W 50 W Q Driver Device D Receiver Device Z = 50 W Q D Figure 18. Typical CML Termination for Output Driver and Device Evaluation ORDERING INFORMATION Package Shipping† NB6L14MMNG QFN-16, 3x3 mm (Pb-Free) 123 Units / Rail NB6L14MMNR2G QFN-16, 3x3 mm (Pb-Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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